utils/TableGen/CodeGenTarget.h

   1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines wrappers for the Target class and related global
  10 // functionality.  This makes it easier to access the data and provides a single
  11 // place that needs to check it for validity.  All of these classes abort
  12 // on error conditions.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
  17 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
  18
  19 #include "CodeGenHwModes.h"
  20 #include "CodeGenInstruction.h"
  21 #include "CodeGenRegisters.h"
  22 #include "InfoByHwMode.h"
  23 #include "SDNodeProperties.h"
  24 #include "llvm/Support/raw_ostream.h"
  25 #include "llvm/TableGen/Record.h"
  26 #include <algorithm>
  27
  28 namespace llvm {
  29
  30 struct CodeGenRegister;
  31 class CodeGenSchedModels;
  32 class CodeGenTarget;
  33
  34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
  35 /// record corresponds to.
  36 MVT::SimpleValueType getValueType(Record *Rec);
  37
  38 StringRef getName(MVT::SimpleValueType T);
  39 StringRef getEnumName(MVT::SimpleValueType T);
  40
  41 /// getQualifiedName - Return the name of the specified record, with a
  42 /// namespace qualifier if the record contains one.
  43 std::string getQualifiedName(const Record *R);
  44
  45 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
  46 ///
  47 class CodeGenTarget {
  48   RecordKeeper &Records;
  49   Record *TargetRec;
  50
  51   mutable DenseMap<const Record*,
  52                    std::unique_ptr<CodeGenInstruction>> Instructions;
  53   mutable std::unique_ptr<CodeGenRegBank> RegBank;
  54   mutable std::vector<Record*> RegAltNameIndices;
  55   mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
  56   CodeGenHwModes CGH;
  57   void ReadRegAltNameIndices() const;
  58   void ReadInstructions() const;
  59   void ReadLegalValueTypes() const;
  60
  61   mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
  62
  63   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
  64   mutable unsigned NumPseudoInstructions = 0;
  65 public:
  66   CodeGenTarget(RecordKeeper &Records);
  67   ~CodeGenTarget();
  68
  69   Record *getTargetRecord() const { return TargetRec; }
  70   const StringRef getName() const;
  71
  72   /// getInstNamespace - Return the target-specific instruction namespace.
  73   ///
  74   StringRef getInstNamespace() const;
  75
  76   /// getInstructionSet - Return the InstructionSet object.
  77   ///
  78   Record *getInstructionSet() const;
  79
  80   /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
  81   /// this target.
  82   ///
  83   bool getAllowRegisterRenaming() const;
  84
  85   /// getAsmParser - Return the AssemblyParser definition for this target.
  86   ///
  87   Record *getAsmParser() const;
  88
  89   /// getAsmParserVariant - Return the AssmblyParserVariant definition for
  90   /// this target.
  91   ///
  92   Record *getAsmParserVariant(unsigned i) const;
  93
  94   /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
  95   /// available for this target.
  96   ///
  97   unsigned getAsmParserVariantCount() const;
  98
  99   /// getAsmWriter - Return the AssemblyWriter definition for this target.
 100   ///
 101   Record *getAsmWriter() const;
 102
 103   /// getRegBank - Return the register bank description.
 104   CodeGenRegBank &getRegBank() const;
 105
 106   /// getRegisterByName - If there is a register with the specific AsmName,
 107   /// return it.
 108   const CodeGenRegister *getRegisterByName(StringRef Name) const;
 109
 110   const std::vector<Record*> &getRegAltNameIndices() const {
 111     if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
 112     return RegAltNameIndices;
 113   }
 114
 115   const CodeGenRegisterClass &getRegisterClass(Record *R) const {
 116     return *getRegBank().getRegClass(R);
 117   }
 118
 119   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
 120   /// specified physical register.
 121   std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
 122
 123   ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
 124     if (LegalValueTypes.empty())
 125       ReadLegalValueTypes();
 126     return LegalValueTypes;
 127   }
 128
 129   CodeGenSchedModels &getSchedModels() const;
 130
 131   const CodeGenHwModes &getHwModes() const { return CGH; }
 132
 133 private:
 134   DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
 135   getInstructions() const {
 136     if (Instructions.empty()) ReadInstructions();
 137     return Instructions;
 138   }
 139 public:
 140
 141   CodeGenInstruction &getInstruction(const Record *InstRec) const {
 142     if (Instructions.empty()) ReadInstructions();
 143     auto I = Instructions.find(InstRec);
 144     assert(I != Instructions.end() && "Not an instruction");
 145     return *I->second;
 146   }
 147
 148   /// Returns the number of predefined instructions.
 149   static unsigned getNumFixedInstructions();
 150
 151   /// Returns the number of pseudo instructions.
 152   unsigned getNumPseudoInstructions() const {
 153     if (InstrsByEnum.empty())
 154       ComputeInstrsByEnum();
 155     return NumPseudoInstructions;
 156   }
 157
 158   /// Return all of the instructions defined by the target, ordered by their
 159   /// enum value.
 160   /// The following order of instructions is also guaranteed:
 161   /// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
 162   /// - pseudo instructions in lexicographical order sorted by name;
 163   /// - other instructions in lexicographical order sorted by name.
 164   ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const {
 165     if (InstrsByEnum.empty())
 166       ComputeInstrsByEnum();
 167     return InstrsByEnum;
 168   }
 169
 170   typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
 171   inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
 172   inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
 173
 174
 175   /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
 176   ///
 177   bool isLittleEndianEncoding() const;
 178
 179   /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
 180   /// encodings, reverse the bit order of all instructions.
 181   void reverseBitsForLittleEndianEncoding();
 182
 183   /// guessInstructionProperties - should we just guess unset instruction
 184   /// properties?
 185   bool guessInstructionProperties() const;
 186
 187 private:
 188   void ComputeInstrsByEnum() const;
 189 };
 190
 191 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
 192 /// tablegen class in TargetSelectionDAG.td
 193 class ComplexPattern {
 194   MVT::SimpleValueType Ty;
 195   unsigned NumOperands;
 196   std::string SelectFunc;
 197   std::vector<Record*> RootNodes;
 198   unsigned Properties; // Node properties
 199   unsigned Complexity;
 200 public:
 201   ComplexPattern(Record *R);
 202
 203   MVT::SimpleValueType getValueType() const { return Ty; }
 204   unsigned getNumOperands() const { return NumOperands; }
 205   const std::string &getSelectFunc() const { return SelectFunc; }
 206   const std::vector<Record*> &getRootNodes() const {
 207     return RootNodes;
 208   }
 209   bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
 210   unsigned getComplexity() const { return Complexity; }
 211 };
 212
 213 } // End llvm namespace
 214
 215 #endif