| blob | d1fd4b2676289de30ff3d3a3c240a06ed5161439 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
3 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
5 define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
6 ; CHECK-MVE-LABEL: fneg_float16_t:
7 ; CHECK-MVE: @ %bb.0: @ %entry
8 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[0]
9 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[1]
10 ; CHECK-MVE-NEXT: vmov s4, r0
11 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
12 ; CHECK-MVE-NEXT: vmov r0, s4
13 ; CHECK-MVE-NEXT: vmov s4, r1
14 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
15 ; CHECK-MVE-NEXT: vmov r1, s4
16 ; CHECK-MVE-NEXT: vmov.16 q1[0], r0
17 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2]
18 ; CHECK-MVE-NEXT: vmov.16 q1[1], r1
19 ; CHECK-MVE-NEXT: vmov s8, r0
20 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
21 ; CHECK-MVE-NEXT: vmov r0, s8
22 ; CHECK-MVE-NEXT: vmov.16 q1[2], r0
23 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
24 ; CHECK-MVE-NEXT: vmov s8, r0
25 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
26 ; CHECK-MVE-NEXT: vmov r0, s8
27 ; CHECK-MVE-NEXT: vmov.16 q1[3], r0
28 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[4]
29 ; CHECK-MVE-NEXT: vmov s8, r0
30 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
31 ; CHECK-MVE-NEXT: vmov r0, s8
32 ; CHECK-MVE-NEXT: vmov.16 q1[4], r0
33 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[5]
34 ; CHECK-MVE-NEXT: vmov s8, r0
35 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
36 ; CHECK-MVE-NEXT: vmov r0, s8
37 ; CHECK-MVE-NEXT: vmov.16 q1[5], r0
38 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[6]
39 ; CHECK-MVE-NEXT: vmov s8, r0
40 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
41 ; CHECK-MVE-NEXT: vmov r0, s8
42 ; CHECK-MVE-NEXT: vmov.16 q1[6], r0
43 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[7]
44 ; CHECK-MVE-NEXT: vmov s0, r0
45 ; CHECK-MVE-NEXT: vneg.f16 s0, s0
46 ; CHECK-MVE-NEXT: vmov r0, s0
47 ; CHECK-MVE-NEXT: vmov.16 q1[7], r0
48 ; CHECK-MVE-NEXT: vmov q0, q1
49 ; CHECK-MVE-NEXT: bx lr
50 ;
51 ; CHECK-MVEFP-LABEL: fneg_float16_t:
52 ; CHECK-MVEFP: @ %bb.0: @ %entry
53 ; CHECK-MVEFP-NEXT: vneg.f16 q0, q0
54 ; CHECK-MVEFP-NEXT: bx lr
55 entry:
56 %0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src
57 ret <8 x half> %0
58 }
60 define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {
61 ; CHECK-MVE-LABEL: fneg_float32_t:
62 ; CHECK-MVE: @ %bb.0: @ %entry
63 ; CHECK-MVE-NEXT: vneg.f32 s7, s3
64 ; CHECK-MVE-NEXT: vneg.f32 s6, s2
65 ; CHECK-MVE-NEXT: vneg.f32 s5, s1
66 ; CHECK-MVE-NEXT: vneg.f32 s4, s0
67 ; CHECK-MVE-NEXT: vmov q0, q1
68 ; CHECK-MVE-NEXT: bx lr
69 ;
70 ; CHECK-MVEFP-LABEL: fneg_float32_t:
71 ; CHECK-MVEFP: @ %bb.0: @ %entry
72 ; CHECK-MVEFP-NEXT: vneg.f32 q0, q0
73 ; CHECK-MVEFP-NEXT: bx lr
74 entry:
75 %0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src
76 ret <4 x float> %0
77 }
79 define arm_aapcs_vfpcc <2 x double> @fneg_float64_t(<2 x double> %src) {
80 ; CHECK-LABEL: fneg_float64_t:
81 ; CHECK: @ %bb.0: @ %entry
82 ; CHECK-NEXT: .save {r4, r5, r7, lr}
83 ; CHECK-NEXT: push {r4, r5, r7, lr}
84 ; CHECK-NEXT: .vsave {d8, d9}
85 ; CHECK-NEXT: vpush {d8, d9}
86 ; CHECK-NEXT: vmov q4, q0
87 ; CHECK-NEXT: vldr d0, .LCPI2_0
88 ; CHECK-NEXT: vmov r2, r3, d9
89 ; CHECK-NEXT: vmov r4, r5, d0
90 ; CHECK-NEXT: mov r0, r4
91 ; CHECK-NEXT: mov r1, r5
92 ; CHECK-NEXT: bl __aeabi_dsub
93 ; CHECK-NEXT: vmov r2, r3, d8
94 ; CHECK-NEXT: vmov d9, r0, r1
95 ; CHECK-NEXT: mov r0, r4
96 ; CHECK-NEXT: mov r1, r5
97 ; CHECK-NEXT: bl __aeabi_dsub
98 ; CHECK-NEXT: vmov d8, r0, r1
99 ; CHECK-NEXT: vmov q0, q4
100 ; CHECK-NEXT: vpop {d8, d9}
101 ; CHECK-NEXT: pop {r4, r5, r7, pc}
102 ; CHECK-NEXT: .p2align 3
103 ; CHECK-NEXT: @ %bb.1:
104 ; CHECK-NEXT: .LCPI2_0:
105 ; CHECK-NEXT: .long 0 @ double -0
106 ; CHECK-NEXT: .long 2147483648
107 entry:
108 %0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src
109 ret <2 x double> %0
110 }
112 define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
113 ; CHECK-MVE-LABEL: fabs_float16_t:
114 ; CHECK-MVE: @ %bb.0: @ %entry
115 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[0]
116 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[1]
117 ; CHECK-MVE-NEXT: vmov s4, r0
118 ; CHECK-MVE-NEXT: vabs.f16 s4, s4
119 ; CHECK-MVE-NEXT: vmov r0, s4
120 ; CHECK-MVE-NEXT: vmov s4, r1
121 ; CHECK-MVE-NEXT: vabs.f16 s4, s4
122 ; CHECK-MVE-NEXT: vmov r1, s4
123 ; CHECK-MVE-NEXT: vmov.16 q1[0], r0
124 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2]
125 ; CHECK-MVE-NEXT: vmov.16 q1[1], r1
126 ; CHECK-MVE-NEXT: vmov s8, r0
127 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
128 ; CHECK-MVE-NEXT: vmov r0, s8
129 ; CHECK-MVE-NEXT: vmov.16 q1[2], r0
130 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
131 ; CHECK-MVE-NEXT: vmov s8, r0
132 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
133 ; CHECK-MVE-NEXT: vmov r0, s8
134 ; CHECK-MVE-NEXT: vmov.16 q1[3], r0
135 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[4]
136 ; CHECK-MVE-NEXT: vmov s8, r0
137 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
138 ; CHECK-MVE-NEXT: vmov r0, s8
139 ; CHECK-MVE-NEXT: vmov.16 q1[4], r0
140 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[5]
141 ; CHECK-MVE-NEXT: vmov s8, r0
142 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
143 ; CHECK-MVE-NEXT: vmov r0, s8
144 ; CHECK-MVE-NEXT: vmov.16 q1[5], r0
145 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[6]
146 ; CHECK-MVE-NEXT: vmov s8, r0
147 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
148 ; CHECK-MVE-NEXT: vmov r0, s8
149 ; CHECK-MVE-NEXT: vmov.16 q1[6], r0
150 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[7]
151 ; CHECK-MVE-NEXT: vmov s0, r0
152 ; CHECK-MVE-NEXT: vabs.f16 s0, s0
153 ; CHECK-MVE-NEXT: vmov r0, s0
154 ; CHECK-MVE-NEXT: vmov.16 q1[7], r0
155 ; CHECK-MVE-NEXT: vmov q0, q1
156 ; CHECK-MVE-NEXT: bx lr
157 ;
158 ; CHECK-MVEFP-LABEL: fabs_float16_t:
159 ; CHECK-MVEFP: @ %bb.0: @ %entry
160 ; CHECK-MVEFP-NEXT: vabs.f16 q0, q0
161 ; CHECK-MVEFP-NEXT: bx lr
162 entry:
163 %0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src)
164 ret <8 x half> %0
165 }
167 define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
168 ; CHECK-MVE-LABEL: fabs_float32_t:
169 ; CHECK-MVE: @ %bb.0: @ %entry
170 ; CHECK-MVE-NEXT: vabs.f32 s7, s3
171 ; CHECK-MVE-NEXT: vabs.f32 s6, s2
172 ; CHECK-MVE-NEXT: vabs.f32 s5, s1
173 ; CHECK-MVE-NEXT: vabs.f32 s4, s0
174 ; CHECK-MVE-NEXT: vmov q0, q1
175 ; CHECK-MVE-NEXT: bx lr
176 ;
177 ; CHECK-MVEFP-LABEL: fabs_float32_t:
178 ; CHECK-MVEFP: @ %bb.0: @ %entry
179 ; CHECK-MVEFP-NEXT: vabs.f32 q0, q0
180 ; CHECK-MVEFP-NEXT: bx lr
181 entry:
182 %0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src)
183 ret <4 x float> %0
184 }
186 define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) {
187 ; CHECK-LABEL: fabs_float64_t:
188 ; CHECK: @ %bb.0: @ %entry
189 ; CHECK-NEXT: vldr d2, .LCPI5_0
190 ; CHECK-NEXT: vmov r12, r3, d0
191 ; CHECK-NEXT: vmov r0, r1, d2
192 ; CHECK-NEXT: vmov r0, r2, d1
193 ; CHECK-NEXT: lsrs r1, r1, #31
194 ; CHECK-NEXT: bfi r2, r1, #31, #1
195 ; CHECK-NEXT: bfi r3, r1, #31, #1
196 ; CHECK-NEXT: vmov d1, r0, r2
197 ; CHECK-NEXT: vmov d0, r12, r3
198 ; CHECK-NEXT: bx lr
199 ; CHECK-NEXT: .p2align 3
200 ; CHECK-NEXT: @ %bb.1:
201 ; CHECK-NEXT: .LCPI5_0:
202 ; CHECK-NEXT: .long 0 @ double 0
203 ; CHECK-NEXT: .long 0
204 entry:
205 %0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src)
206 ret <2 x double> %0
207 }
209 declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
210 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
211 declare <2 x double> @llvm.fabs.v2f64(<2 x double>)