1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
4 ; First, a simple example from Clang. The registers could plausibly be
5 ; different, but probably won't be.
7 %struct.foo = type { i8, [2 x i8], i8 }
9 define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
10 ; CHECK-LABEL: from_clang:
11 ; CHECK: // %bb.0: // %entry
12 ; CHECK-NEXT: mov w8, #135
13 ; CHECK-NEXT: and w8, w0, w8
14 ; CHECK-NEXT: bfi w8, w1, #3, #4
15 ; CHECK-NEXT: and x9, x0, #0xffffff00
16 ; CHECK-NEXT: orr x0, x8, x9
19 %f.coerce.fca.0.extract = extractvalue [1 x i64] %f.coerce, 0
20 %tmp.sroa.0.0.extract.trunc = trunc i64 %f.coerce.fca.0.extract to i32
21 %bf.value = shl i32 %n, 3
22 %0 = and i32 %bf.value, 120
23 %f.sroa.0.0.insert.ext.masked = and i32 %tmp.sroa.0.0.extract.trunc, 135
24 %1 = or i32 %f.sroa.0.0.insert.ext.masked, %0
25 %f.sroa.0.0.extract.trunc = zext i32 %1 to i64
26 %tmp1.sroa.1.1.insert.insert = and i64 %f.coerce.fca.0.extract, 4294967040
27 %tmp1.sroa.0.0.insert.insert = or i64 %f.sroa.0.0.extract.trunc, %tmp1.sroa.1.1.insert.insert
28 %.fca.0.insert = insertvalue [1 x i64] undef, i64 %tmp1.sroa.0.0.insert.insert, 0
29 ret [1 x i64] %.fca.0.insert
32 define void @test_whole32(i32* %existing, i32* %new) {
33 ; CHECK-LABEL: test_whole32:
35 ; CHECK-NEXT: ldr w8, [x0]
36 ; CHECK-NEXT: ldr w9, [x1]
37 ; CHECK-NEXT: bfi w8, w9, #26, #5
38 ; CHECK-NEXT: str w8, [x0]
40 %oldval = load volatile i32, i32* %existing
41 %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
43 %newval = load volatile i32, i32* %new
44 %newval_shifted = shl i32 %newval, 26
45 %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000
47 %combined = or i32 %oldval_keep, %newval_masked
48 store volatile i32 %combined, i32* %existing
53 define void @test_whole64(i64* %existing, i64* %new) {
54 ; CHECK-LABEL: test_whole64:
56 ; CHECK-NEXT: ldr x8, [x0]
57 ; CHECK-NEXT: ldr x9, [x1]
58 ; CHECK-NEXT: bfi x8, x9, #26, #14
59 ; CHECK-NEXT: str x8, [x0]
61 %oldval = load volatile i64, i64* %existing
62 %oldval_keep = and i64 %oldval, 18446742974265032703 ; = 0xffffff0003ffffffL
64 %newval = load volatile i64, i64* %new
65 %newval_shifted = shl i64 %newval, 26
66 %newval_masked = and i64 %newval_shifted, 1099444518912 ; = 0xfffc000000
68 %combined = or i64 %oldval_keep, %newval_masked
69 store volatile i64 %combined, i64* %existing
74 define void @test_whole32_from64(i64* %existing, i64* %new) {
75 ; CHECK-LABEL: test_whole32_from64:
77 ; CHECK-NEXT: ldr x8, [x0]
78 ; CHECK-NEXT: ldr x9, [x1]
79 ; CHECK-NEXT: and x8, x8, #0xffff0000
80 ; CHECK-NEXT: bfxil x8, x9, #0, #16
81 ; CHECK-NEXT: str x8, [x0]
83 %oldval = load volatile i64, i64* %existing
84 %oldval_keep = and i64 %oldval, 4294901760 ; = 0xffff0000
86 %newval = load volatile i64, i64* %new
87 %newval_masked = and i64 %newval, 65535 ; = 0xffff
89 %combined = or i64 %oldval_keep, %newval_masked
90 store volatile i64 %combined, i64* %existing
95 define void @test_32bit_masked(i32 *%existing, i32 *%new) {
96 ; CHECK-LABEL: test_32bit_masked:
98 ; CHECK-NEXT: ldr w8, [x0]
99 ; CHECK-NEXT: ldr w9, [x1]
100 ; CHECK-NEXT: mov w10, #135
101 ; CHECK-NEXT: and w8, w8, w10
102 ; CHECK-NEXT: bfi w8, w9, #3, #4
103 ; CHECK-NEXT: str w8, [x0]
105 %oldval = load volatile i32, i32* %existing
106 %oldval_keep = and i32 %oldval, 135 ; = 0x87
108 %newval = load volatile i32, i32* %new
109 %newval_shifted = shl i32 %newval, 3
110 %newval_masked = and i32 %newval_shifted, 120 ; = 0x78
112 %combined = or i32 %oldval_keep, %newval_masked
113 store volatile i32 %combined, i32* %existing
118 define void @test_64bit_masked(i64 *%existing, i64 *%new) {
119 ; CHECK-LABEL: test_64bit_masked:
121 ; CHECK-NEXT: ldr x8, [x0]
122 ; CHECK-NEXT: ldr x9, [x1]
123 ; CHECK-NEXT: and x8, x8, #0xff00000000
124 ; CHECK-NEXT: bfi x8, x9, #40, #8
125 ; CHECK-NEXT: str x8, [x0]
127 %oldval = load volatile i64, i64* %existing
128 %oldval_keep = and i64 %oldval, 1095216660480 ; = 0xff_0000_0000
130 %newval = load volatile i64, i64* %new
131 %newval_shifted = shl i64 %newval, 40
132 %newval_masked = and i64 %newval_shifted, 280375465082880 ; = 0xff00_0000_0000
134 %combined = or i64 %newval_masked, %oldval_keep
135 store volatile i64 %combined, i64* %existing
140 ; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
141 define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
142 ; CHECK-LABEL: test_32bit_complexmask:
144 ; CHECK-NEXT: ldr w8, [x0]
145 ; CHECK-NEXT: ldr w9, [x1]
146 ; CHECK-NEXT: mov w10, #647
147 ; CHECK-NEXT: and w8, w8, w10
148 ; CHECK-NEXT: bfi w8, w9, #3, #4
149 ; CHECK-NEXT: str w8, [x0]
151 %oldval = load volatile i32, i32* %existing
152 %oldval_keep = and i32 %oldval, 647 ; = 0x287
154 %newval = load volatile i32, i32* %new
155 %newval_shifted = shl i32 %newval, 3
156 %newval_masked = and i32 %newval_shifted, 120 ; = 0x278
158 %combined = or i32 %oldval_keep, %newval_masked
159 store volatile i32 %combined, i32* %existing
164 ; Neither mask is a contiguous set of 1s. BFI can't be used
165 define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
166 ; CHECK-LABEL: test_32bit_badmask:
168 ; CHECK-NEXT: ldr w8, [x0]
169 ; CHECK-NEXT: ldr w9, [x1]
170 ; CHECK-NEXT: mov w10, #135
171 ; CHECK-NEXT: mov w11, #632
172 ; CHECK-NEXT: and w8, w8, w10
173 ; CHECK-NEXT: and w9, w11, w9, lsl #3
174 ; CHECK-NEXT: orr w8, w8, w9
175 ; CHECK-NEXT: str w8, [x0]
177 %oldval = load volatile i32, i32* %existing
178 %oldval_keep = and i32 %oldval, 135 ; = 0x87
180 %newval = load volatile i32, i32* %new
181 %newval_shifted = shl i32 %newval, 3
182 %newval_masked = and i32 %newval_shifted, 632 ; = 0x278
184 %combined = or i32 %oldval_keep, %newval_masked
185 store volatile i32 %combined, i32* %existing
191 define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
192 ; CHECK-LABEL: test_64bit_badmask:
194 ; CHECK-NEXT: ldr x8, [x0]
195 ; CHECK-NEXT: ldr x9, [x1]
196 ; CHECK-NEXT: mov w10, #135
197 ; CHECK-NEXT: and x8, x8, x10
198 ; CHECK-NEXT: lsl w9, w9, #3
199 ; CHECK-NEXT: mov w10, #664
200 ; CHECK-NEXT: and x9, x9, x10
201 ; CHECK-NEXT: orr x8, x8, x9
202 ; CHECK-NEXT: str x8, [x0]
204 %oldval = load volatile i64, i64* %existing
205 %oldval_keep = and i64 %oldval, 135 ; = 0x87
207 %newval = load volatile i64, i64* %new
208 %newval_shifted = shl i64 %newval, 3
209 %newval_masked = and i64 %newval_shifted, 664 ; = 0x278
211 %combined = or i64 %oldval_keep, %newval_masked
212 store volatile i64 %combined, i64* %existing
217 ; Bitfield insert where there's a left-over shr needed at the beginning
218 ; (e.g. result of str.bf1 = str.bf2)
219 define void @test_32bit_with_shr(i32* %existing, i32* %new) {
220 ; CHECK-LABEL: test_32bit_with_shr:
222 ; CHECK-NEXT: ldr w8, [x0]
223 ; CHECK-NEXT: ldr w9, [x1]
224 ; CHECK-NEXT: lsr w9, w9, #14
225 ; CHECK-NEXT: bfi w8, w9, #26, #5
226 ; CHECK-NEXT: str w8, [x0]
228 %oldval = load volatile i32, i32* %existing
229 %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
231 %newval = load i32, i32* %new
232 %newval_shifted = shl i32 %newval, 12
233 %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000
235 %combined = or i32 %oldval_keep, %newval_masked
236 store volatile i32 %combined, i32* %existing
241 ; Bitfield insert where the second or operand is a better match to be folded into the BFM
242 define void @test_32bit_opnd1_better(i32* %existing, i32* %new) {
243 ; CHECK-LABEL: test_32bit_opnd1_better:
245 ; CHECK-NEXT: ldr w8, [x0]
246 ; CHECK-NEXT: ldr w9, [x1]
247 ; CHECK-NEXT: and w8, w8, #0xffff
248 ; CHECK-NEXT: bfi w8, w9, #16, #8
249 ; CHECK-NEXT: str w8, [x0]
251 %oldval = load volatile i32, i32* %existing
252 %oldval_keep = and i32 %oldval, 65535 ; 0x0000ffff
254 %newval = load i32, i32* %new
255 %newval_shifted = shl i32 %newval, 16
256 %newval_masked = and i32 %newval_shifted, 16711680 ; 0x00ff0000
258 %combined = or i32 %oldval_keep, %newval_masked
259 store volatile i32 %combined, i32* %existing
264 ; Tests when all the bits from one operand are not useful
265 define i32 @test_nouseful_bits(i8 %a, i32 %b) {
266 ; CHECK-LABEL: test_nouseful_bits:
268 ; CHECK-NEXT: orr w8, w0, w8, lsl #8
269 ; CHECK-NEXT: mov w9, w0
270 ; CHECK-NEXT: bfi w9, w8, #8, #24
271 ; CHECK-NEXT: bfi w0, w9, #8, #24
272 ; CHECK-NEXT: lsl w0, w0, #8
274 %conv = zext i8 %a to i32 ; 0 0 0 A
275 %shl = shl i32 %b, 8 ; B2 B1 B0 0
276 %or = or i32 %conv, %shl ; B2 B1 B0 A
277 %shl.1 = shl i32 %or, 8 ; B1 B0 A 0
278 %or.1 = or i32 %conv, %shl.1 ; B1 B0 A A
279 %shl.2 = shl i32 %or.1, 8 ; B0 A A 0
280 %or.2 = or i32 %conv, %shl.2 ; B0 A A A
281 %shl.3 = shl i32 %or.2, 8 ; A A A 0
282 %or.3 = or i32 %conv, %shl.3 ; A A A A
283 %shl.4 = shl i32 %or.3, 8 ; A A A 0
287 define void @test_nouseful_strb(i32* %ptr32, i8* %ptr8, i32 %x) {
288 ; CHECK-LABEL: test_nouseful_strb:
289 ; CHECK: // %bb.0: // %entry
290 ; CHECK-NEXT: ldr w8, [x0]
291 ; CHECK-NEXT: bfxil w8, w2, #16, #3
292 ; CHECK-NEXT: strb w8, [x1]
295 %0 = load i32, i32* %ptr32, align 8
296 %and = and i32 %0, -8
297 %shr = lshr i32 %x, 16
298 %and1 = and i32 %shr, 7
299 %or = or i32 %and, %and1
300 %trunc = trunc i32 %or to i8
301 store i8 %trunc, i8* %ptr8
305 define void @test_nouseful_strh(i32* %ptr32, i16* %ptr16, i32 %x) {
306 ; CHECK-LABEL: test_nouseful_strh:
307 ; CHECK: // %bb.0: // %entry
308 ; CHECK-NEXT: ldr w8, [x0]
309 ; CHECK-NEXT: bfxil w8, w2, #16, #4
310 ; CHECK-NEXT: strh w8, [x1]
313 %0 = load i32, i32* %ptr32, align 8
314 %and = and i32 %0, -16
315 %shr = lshr i32 %x, 16
316 %and1 = and i32 %shr, 15
317 %or = or i32 %and, %and1
318 %trunc = trunc i32 %or to i16
319 store i16 %trunc, i16* %ptr16
323 define void @test_nouseful_sturb(i32* %ptr32, i8* %ptr8, i32 %x) {
324 ; CHECK-LABEL: test_nouseful_sturb:
325 ; CHECK: // %bb.0: // %entry
326 ; CHECK-NEXT: ldr w8, [x0]
327 ; CHECK-NEXT: bfxil w8, w2, #16, #3
328 ; CHECK-NEXT: sturb w8, [x1, #-1]
331 %0 = load i32, i32* %ptr32, align 8
332 %and = and i32 %0, -8
333 %shr = lshr i32 %x, 16
334 %and1 = and i32 %shr, 7
335 %or = or i32 %and, %and1
336 %trunc = trunc i32 %or to i8
337 %gep = getelementptr i8, i8* %ptr8, i64 -1
338 store i8 %trunc, i8* %gep
342 define void @test_nouseful_sturh(i32* %ptr32, i16* %ptr16, i32 %x) {
343 ; CHECK-LABEL: test_nouseful_sturh:
344 ; CHECK: // %bb.0: // %entry
345 ; CHECK-NEXT: ldr w8, [x0]
346 ; CHECK-NEXT: bfxil w8, w2, #16, #4
347 ; CHECK-NEXT: sturh w8, [x1, #-2]
350 %0 = load i32, i32* %ptr32, align 8
351 %and = and i32 %0, -16
352 %shr = lshr i32 %x, 16
353 %and1 = and i32 %shr, 15
354 %or = or i32 %and, %and1
355 %trunc = trunc i32 %or to i16
356 %gep = getelementptr i16, i16* %ptr16, i64 -1
357 store i16 %trunc, i16* %gep
361 ; The next set of tests generate a BFXIL from 'or (and X, Mask0Imm),
362 ; (and Y, Mask1Imm)' iff Mask0Imm and ~Mask1Imm are equivalent and one of the
363 ; MaskImms is a shifted mask (e.g., 0x000ffff0).
365 define i32 @test_or_and_and1(i32 %a, i32 %b) {
366 ; CHECK-LABEL: test_or_and_and1:
367 ; CHECK: // %bb.0: // %entry
368 ; CHECK-NEXT: lsr w8, w1, #4
369 ; CHECK-NEXT: bfi w0, w8, #4, #12
372 %and = and i32 %a, -65521 ; 0xffff000f
373 %and1 = and i32 %b, 65520 ; 0x0000fff0
374 %or = or i32 %and1, %and
378 define i32 @test_or_and_and2(i32 %a, i32 %b) {
379 ; CHECK-LABEL: test_or_and_and2:
380 ; CHECK: // %bb.0: // %entry
381 ; CHECK-NEXT: lsr w8, w0, #4
382 ; CHECK-NEXT: bfi w1, w8, #4, #12
383 ; CHECK-NEXT: mov w0, w1
386 %and = and i32 %a, 65520 ; 0x0000fff0
387 %and1 = and i32 %b, -65521 ; 0xffff000f
388 %or = or i32 %and1, %and
392 define i64 @test_or_and_and3(i64 %a, i64 %b) {
393 ; CHECK-LABEL: test_or_and_and3:
394 ; CHECK: // %bb.0: // %entry
395 ; CHECK-NEXT: lsr x8, x1, #16
396 ; CHECK-NEXT: bfi x0, x8, #16, #32
399 %and = and i64 %a, -281474976645121 ; 0xffff00000000ffff
400 %and1 = and i64 %b, 281474976645120 ; 0x0000ffffffff0000
401 %or = or i64 %and1, %and
405 ; Don't convert 'and' with multiple uses.
406 define i32 @test_or_and_and4(i32 %a, i32 %b, i32* %ptr) {
407 ; CHECK-LABEL: test_or_and_and4:
408 ; CHECK: // %bb.0: // %entry
409 ; CHECK-NEXT: and w8, w0, #0xffff000f
410 ; CHECK-NEXT: and w9, w1, #0xfff0
411 ; CHECK-NEXT: orr w0, w9, w8
412 ; CHECK-NEXT: str w8, [x2]
415 %and = and i32 %a, -65521
416 store i32 %and, i32* %ptr, align 4
417 %and2 = and i32 %b, 65520
418 %or = or i32 %and2, %and
422 ; Don't convert 'and' with multiple uses.
423 define i32 @test_or_and_and5(i32 %a, i32 %b, i32* %ptr) {
424 ; CHECK-LABEL: test_or_and_and5:
425 ; CHECK: // %bb.0: // %entry
426 ; CHECK-NEXT: and w8, w1, #0xfff0
427 ; CHECK-NEXT: and w9, w0, #0xffff000f
428 ; CHECK-NEXT: orr w0, w8, w9
429 ; CHECK-NEXT: str w8, [x2]
432 %and = and i32 %b, 65520
433 store i32 %and, i32* %ptr, align 4
434 %and1 = and i32 %a, -65521
435 %or = or i32 %and, %and1
439 define i32 @test1(i32 %a) {
440 ; CHECK-LABEL: test1:
442 ; CHECK-NEXT: mov w8, #5
443 ; CHECK-NEXT: bfxil w0, w8, #0, #4
445 %1 = and i32 %a, -16 ; 0xfffffff0
446 %2 = or i32 %1, 5 ; 0x00000005
450 define i32 @test2(i32 %a) {
451 ; CHECK-LABEL: test2:
453 ; CHECK-NEXT: mov w8, #10
454 ; CHECK-NEXT: bfi w0, w8, #22, #4
456 %1 = and i32 %a, -62914561 ; 0xfc3fffff
457 %2 = or i32 %1, 41943040 ; 0x06400000
461 define i64 @test3(i64 %a) {
462 ; CHECK-LABEL: test3:
464 ; CHECK-NEXT: mov x8, #5
465 ; CHECK-NEXT: bfxil x0, x8, #0, #3
467 %1 = and i64 %a, -8 ; 0xfffffffffffffff8
468 %2 = or i64 %1, 5 ; 0x0000000000000005
472 define i64 @test4(i64 %a) {
473 ; CHECK-LABEL: test4:
475 ; CHECK-NEXT: mov x8, #9
476 ; CHECK-NEXT: bfi x0, x8, #1, #7
478 %1 = and i64 %a, -255 ; 0xffffffffffffff01
479 %2 = or i64 %1, 18 ; 0x0000000000000012
483 ; Don't generate BFI/BFXIL if the immediate can be encoded in the ORR.
484 define i32 @test5(i32 %a) {
485 ; CHECK-LABEL: test5:
487 ; CHECK-NEXT: and w8, w0, #0xfffffff0
488 ; CHECK-NEXT: orr w0, w8, #0x6
490 %1 = and i32 %a, 4294967280 ; 0xfffffff0
491 %2 = or i32 %1, 6 ; 0x00000006
495 ; BFXIL will use the same constant as the ORR, so we don't care how the constant
496 ; is materialized (it's an equal cost either way).
497 define i32 @test6(i32 %a) {
498 ; CHECK-LABEL: test6:
500 ; CHECK-NEXT: mov w8, #23250
501 ; CHECK-NEXT: movk w8, #11, lsl #16
502 ; CHECK-NEXT: bfxil w0, w8, #0, #20
504 %1 = and i32 %a, 4293918720 ; 0xfff00000
505 %2 = or i32 %1, 744146 ; 0x000b5ad2
509 ; BFIs that require the same number of instruction to materialize the constant
510 ; as the original ORR are okay.
511 define i32 @test7(i32 %a) {
512 ; CHECK-LABEL: test7:
514 ; CHECK-NEXT: mov w8, #44393
515 ; CHECK-NEXT: movk w8, #5, lsl #16
516 ; CHECK-NEXT: bfi w0, w8, #1, #19
518 %1 = and i32 %a, 4293918721 ; 0xfff00001
519 %2 = or i32 %1, 744146 ; 0x000b5ad2
523 ; BFIs that require more instructions to materialize the constant as compared
524 ; to the original ORR are not okay. In this case we would be replacing the
525 ; 'and' with a 'movk', which would decrease ILP while using the same number of
527 define i64 @test8(i64 %a) {
528 ; CHECK-LABEL: test8:
530 ; CHECK-NEXT: mov x9, #2035482624
531 ; CHECK-NEXT: and x8, x0, #0xff000000000000ff
532 ; CHECK-NEXT: movk x9, #36694, lsl #32
533 ; CHECK-NEXT: orr x0, x8, x9
535 %1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff
536 %2 = or i64 %1, 157601565442048 ; 0x00008f5679530000
540 ; This test exposed an issue with an overly aggressive assert. The bit of code
541 ; that is expected to catch this case is unable to deal with the trunc, which
542 ; results in a failing check due to a mismatch between the BFI opcode and
543 ; the expected value type of the OR.
544 define i32 @test9(i64 %b, i32 %e) {
545 ; CHECK-LABEL: test9:
547 ; CHECK-NEXT: lsr x0, x0, #12
548 ; CHECK-NEXT: lsr w8, w1, #23
549 ; CHECK-NEXT: bfi w0, w8, #23, #9
550 ; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
553 %d = trunc i64 %c to i32
554 %f = and i32 %d, 8388607
555 %g = and i32 %e, -8388608
560 define <2 x i32> @test_complex_type(<2 x i32>* %addr, i64 %in, i64* %bf ) {
561 ; CHECK-LABEL: test_complex_type:
563 ; CHECK-NEXT: ldr d0, [x0], #8
564 ; CHECK-NEXT: orr x8, x0, x1, lsl #32
565 ; CHECK-NEXT: str x8, [x2]
567 %vec = load <2 x i32>, <2 x i32>* %addr
569 %vec.next = getelementptr <2 x i32>, <2 x i32>* %addr, i32 1
570 %lo = ptrtoint <2 x i32>* %vec.next to i64
572 %hi = shl i64 %in, 32
573 %both = or i64 %lo, %hi
574 store i64 %both, i64* %bf