| blob | 6a9a9225183780698ddbfc1c8b8e43613c05f01c |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
4 ; At the moment, BuildSREMEqFold does not handle nonsplat vectors.
6 ; Odd+Even divisors
7 define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
8 ; CHECK-LABEL: test_srem_odd_even:
9 ; CHECK: // %bb.0:
10 ; CHECK-NEXT: adrp x8, .LCPI0_0
11 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
12 ; CHECK-NEXT: adrp x8, .LCPI0_1
13 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_1]
14 ; CHECK-NEXT: adrp x8, .LCPI0_2
15 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
16 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
17 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
18 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI0_2]
19 ; CHECK-NEXT: adrp x8, .LCPI0_3
20 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
21 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_3]
22 ; CHECK-NEXT: neg v3.4s, v3.4s
23 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
24 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
25 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
26 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
27 ; CHECK-NEXT: movi v1.4s, #1
28 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
29 ; CHECK-NEXT: ret
30 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
31 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
32 %ret = zext <4 x i1> %cmp to <4 x i32>
33 ret <4 x i32> %ret
34 }
36 ;==============================================================================;
38 ; One all-ones divisor in odd divisor
39 define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
40 ; CHECK-LABEL: test_srem_odd_allones_eq:
41 ; CHECK: // %bb.0:
42 ; CHECK-NEXT: adrp x8, .LCPI1_0
43 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
44 ; CHECK-NEXT: adrp x8, .LCPI1_1
45 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_1]
46 ; CHECK-NEXT: adrp x8, .LCPI1_2
47 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI1_2]
48 ; CHECK-NEXT: adrp x8, .LCPI1_3
49 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
50 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
51 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
52 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI1_3]
53 ; CHECK-NEXT: adrp x8, .LCPI1_4
54 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
55 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_4]
56 ; CHECK-NEXT: neg v3.4s, v3.4s
57 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
58 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
59 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
60 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
61 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
62 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
63 ; CHECK-NEXT: movi v1.4s, #1
64 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
65 ; CHECK-NEXT: ret
66 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
67 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
68 %ret = zext <4 x i1> %cmp to <4 x i32>
69 ret <4 x i32> %ret
70 }
71 define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
72 ; CHECK-LABEL: test_srem_odd_allones_ne:
73 ; CHECK: // %bb.0:
74 ; CHECK-NEXT: adrp x8, .LCPI2_0
75 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
76 ; CHECK-NEXT: adrp x8, .LCPI2_1
77 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_1]
78 ; CHECK-NEXT: adrp x8, .LCPI2_2
79 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_2]
80 ; CHECK-NEXT: adrp x8, .LCPI2_3
81 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
82 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
83 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
84 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI2_3]
85 ; CHECK-NEXT: adrp x8, .LCPI2_4
86 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
87 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_4]
88 ; CHECK-NEXT: neg v3.4s, v3.4s
89 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
90 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
91 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
92 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
93 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
94 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
95 ; CHECK-NEXT: mvn v0.16b, v0.16b
96 ; CHECK-NEXT: movi v1.4s, #1
97 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
98 ; CHECK-NEXT: ret
99 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
100 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
101 %ret = zext <4 x i1> %cmp to <4 x i32>
102 ret <4 x i32> %ret
103 }
105 ; One all-ones divisor in even divisor
106 define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
107 ; CHECK-LABEL: test_srem_even_allones_eq:
108 ; CHECK: // %bb.0:
109 ; CHECK-NEXT: adrp x8, .LCPI3_0
110 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
111 ; CHECK-NEXT: adrp x8, .LCPI3_1
112 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
113 ; CHECK-NEXT: adrp x8, .LCPI3_2
114 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI3_2]
115 ; CHECK-NEXT: adrp x8, .LCPI3_3
116 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
117 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
118 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
119 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI3_3]
120 ; CHECK-NEXT: adrp x8, .LCPI3_4
121 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
122 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_4]
123 ; CHECK-NEXT: neg v3.4s, v3.4s
124 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
125 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
126 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
127 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
128 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
129 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
130 ; CHECK-NEXT: movi v1.4s, #1
131 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
132 ; CHECK-NEXT: ret
133 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
134 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
135 %ret = zext <4 x i1> %cmp to <4 x i32>
136 ret <4 x i32> %ret
137 }
138 define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
139 ; CHECK-LABEL: test_srem_even_allones_ne:
140 ; CHECK: // %bb.0:
141 ; CHECK-NEXT: adrp x8, .LCPI4_0
142 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
143 ; CHECK-NEXT: adrp x8, .LCPI4_1
144 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_1]
145 ; CHECK-NEXT: adrp x8, .LCPI4_2
146 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI4_2]
147 ; CHECK-NEXT: adrp x8, .LCPI4_3
148 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
149 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
150 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
151 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI4_3]
152 ; CHECK-NEXT: adrp x8, .LCPI4_4
153 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
154 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_4]
155 ; CHECK-NEXT: neg v3.4s, v3.4s
156 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
157 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
158 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
159 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
160 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
161 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
162 ; CHECK-NEXT: mvn v0.16b, v0.16b
163 ; CHECK-NEXT: movi v1.4s, #1
164 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
165 ; CHECK-NEXT: ret
166 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
167 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
168 %ret = zext <4 x i1> %cmp to <4 x i32>
169 ret <4 x i32> %ret
170 }
172 ; One all-ones divisor in odd+even divisor
173 define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
174 ; CHECK-LABEL: test_srem_odd_even_allones_eq:
175 ; CHECK: // %bb.0:
176 ; CHECK-NEXT: adrp x8, .LCPI5_0
177 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
178 ; CHECK-NEXT: adrp x8, .LCPI5_1
179 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_1]
180 ; CHECK-NEXT: adrp x8, .LCPI5_2
181 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI5_2]
182 ; CHECK-NEXT: adrp x8, .LCPI5_3
183 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
184 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
185 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
186 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI5_3]
187 ; CHECK-NEXT: adrp x8, .LCPI5_4
188 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
189 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_4]
190 ; CHECK-NEXT: neg v3.4s, v3.4s
191 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
192 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
193 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
194 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
195 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
196 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
197 ; CHECK-NEXT: movi v1.4s, #1
198 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
199 ; CHECK-NEXT: ret
200 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
201 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
202 %ret = zext <4 x i1> %cmp to <4 x i32>
203 ret <4 x i32> %ret
204 }
205 define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
206 ; CHECK-LABEL: test_srem_odd_even_allones_ne:
207 ; CHECK: // %bb.0:
208 ; CHECK-NEXT: adrp x8, .LCPI6_0
209 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
210 ; CHECK-NEXT: adrp x8, .LCPI6_1
211 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
212 ; CHECK-NEXT: adrp x8, .LCPI6_2
213 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI6_2]
214 ; CHECK-NEXT: adrp x8, .LCPI6_3
215 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
216 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
217 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
218 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI6_3]
219 ; CHECK-NEXT: adrp x8, .LCPI6_4
220 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
221 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_4]
222 ; CHECK-NEXT: neg v3.4s, v3.4s
223 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
224 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
225 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
226 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
227 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
228 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
229 ; CHECK-NEXT: mvn v0.16b, v0.16b
230 ; CHECK-NEXT: movi v1.4s, #1
231 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
232 ; CHECK-NEXT: ret
233 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
234 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
235 %ret = zext <4 x i1> %cmp to <4 x i32>
236 ret <4 x i32> %ret
237 }
239 ;------------------------------------------------------------------------------;
241 ; One power-of-two divisor in odd divisor
242 define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
243 ; CHECK-LABEL: test_srem_odd_poweroftwo:
244 ; CHECK: // %bb.0:
245 ; CHECK-NEXT: adrp x8, .LCPI7_0
246 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
247 ; CHECK-NEXT: adrp x8, .LCPI7_1
248 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_1]
249 ; CHECK-NEXT: adrp x8, .LCPI7_2
250 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
251 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
252 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
253 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI7_2]
254 ; CHECK-NEXT: adrp x8, .LCPI7_3
255 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
256 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_3]
257 ; CHECK-NEXT: neg v3.4s, v3.4s
258 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
259 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
260 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
261 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
262 ; CHECK-NEXT: movi v1.4s, #1
263 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
264 ; CHECK-NEXT: ret
265 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
266 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
267 %ret = zext <4 x i1> %cmp to <4 x i32>
268 ret <4 x i32> %ret
269 }
271 ; One power-of-two divisor in even divisor
272 define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
273 ; CHECK-LABEL: test_srem_even_poweroftwo:
274 ; CHECK: // %bb.0:
275 ; CHECK-NEXT: adrp x8, .LCPI8_0
276 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
277 ; CHECK-NEXT: adrp x8, .LCPI8_1
278 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_1]
279 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
280 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
281 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
282 ; CHECK-NEXT: add v1.4s, v1.4s, v0.4s
283 ; CHECK-NEXT: sshr v3.4s, v1.4s, #3
284 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
285 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
286 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
287 ; CHECK-NEXT: movi v1.4s, #1
288 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
289 ; CHECK-NEXT: ret
290 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
291 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
292 %ret = zext <4 x i1> %cmp to <4 x i32>
293 ret <4 x i32> %ret
294 }
296 ; One power-of-two divisor in odd+even divisor
297 define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
298 ; CHECK-LABEL: test_srem_odd_even_poweroftwo:
299 ; CHECK: // %bb.0:
300 ; CHECK-NEXT: adrp x8, .LCPI9_0
301 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]
302 ; CHECK-NEXT: adrp x8, .LCPI9_1
303 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_1]
304 ; CHECK-NEXT: adrp x8, .LCPI9_2
305 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
306 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
307 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
308 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI9_2]
309 ; CHECK-NEXT: adrp x8, .LCPI9_3
310 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
311 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI9_3]
312 ; CHECK-NEXT: neg v3.4s, v3.4s
313 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
314 ; CHECK-NEXT: usra v3.4s, v1.4s, #31
315 ; CHECK-NEXT: mls v0.4s, v3.4s, v2.4s
316 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
317 ; CHECK-NEXT: movi v1.4s, #1
318 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
319 ; CHECK-NEXT: ret
320 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
321 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
322 %ret = zext <4 x i1> %cmp to <4 x i32>
323 ret <4 x i32> %ret
324 }
326 ;------------------------------------------------------------------------------;
328 ; One one divisor in odd divisor
329 define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
330 ; CHECK-LABEL: test_srem_odd_one:
331 ; CHECK: // %bb.0:
332 ; CHECK-NEXT: adrp x8, .LCPI10_0
333 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI10_0]
334 ; CHECK-NEXT: adrp x8, .LCPI10_1
335 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_1]
336 ; CHECK-NEXT: adrp x8, .LCPI10_2
337 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI10_2]
338 ; CHECK-NEXT: adrp x8, .LCPI10_3
339 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
340 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
341 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
342 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI10_3]
343 ; CHECK-NEXT: adrp x8, .LCPI10_4
344 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
345 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_4]
346 ; CHECK-NEXT: neg v3.4s, v3.4s
347 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
348 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
349 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
350 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
351 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
352 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
353 ; CHECK-NEXT: movi v1.4s, #1
354 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
355 ; CHECK-NEXT: ret
356 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
357 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
358 %ret = zext <4 x i1> %cmp to <4 x i32>
359 ret <4 x i32> %ret
360 }
362 ; One one divisor in even divisor
363 define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
364 ; CHECK-LABEL: test_srem_even_one:
365 ; CHECK: // %bb.0:
366 ; CHECK-NEXT: adrp x8, .LCPI11_0
367 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI11_0]
368 ; CHECK-NEXT: adrp x8, .LCPI11_1
369 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_1]
370 ; CHECK-NEXT: adrp x8, .LCPI11_2
371 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI11_2]
372 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
373 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
374 ; CHECK-NEXT: adrp x8, .LCPI11_3
375 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
376 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI11_3]
377 ; CHECK-NEXT: neg v2.4s, v2.4s
378 ; CHECK-NEXT: add v1.4s, v1.4s, v0.4s
379 ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
380 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
381 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
382 ; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
383 ; CHECK-NEXT: mls v0.4s, v1.4s, v4.4s
384 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
385 ; CHECK-NEXT: movi v1.4s, #1
386 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
387 ; CHECK-NEXT: ret
388 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
389 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
390 %ret = zext <4 x i1> %cmp to <4 x i32>
391 ret <4 x i32> %ret
392 }
394 ; One one divisor in odd+even divisor
395 define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
396 ; CHECK-LABEL: test_srem_odd_even_one:
397 ; CHECK: // %bb.0:
398 ; CHECK-NEXT: adrp x8, .LCPI12_0
399 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]
400 ; CHECK-NEXT: adrp x8, .LCPI12_1
401 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_1]
402 ; CHECK-NEXT: adrp x8, .LCPI12_2
403 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI12_2]
404 ; CHECK-NEXT: adrp x8, .LCPI12_3
405 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
406 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
407 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
408 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI12_3]
409 ; CHECK-NEXT: adrp x8, .LCPI12_4
410 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
411 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_4]
412 ; CHECK-NEXT: neg v3.4s, v3.4s
413 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
414 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
415 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
416 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
417 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
418 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
419 ; CHECK-NEXT: movi v1.4s, #1
420 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
421 ; CHECK-NEXT: ret
422 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
423 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
424 %ret = zext <4 x i1> %cmp to <4 x i32>
425 ret <4 x i32> %ret
426 }
428 ;==============================================================================;
430 ; One all-ones divisor and power-of-two divisor divisor in odd divisor
431 define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
432 ; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo:
433 ; CHECK: // %bb.0:
434 ; CHECK-NEXT: adrp x8, .LCPI13_0
435 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0]
436 ; CHECK-NEXT: adrp x8, .LCPI13_1
437 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_1]
438 ; CHECK-NEXT: adrp x8, .LCPI13_2
439 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI13_2]
440 ; CHECK-NEXT: adrp x8, .LCPI13_3
441 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
442 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
443 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
444 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI13_3]
445 ; CHECK-NEXT: adrp x8, .LCPI13_4
446 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
447 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_4]
448 ; CHECK-NEXT: neg v3.4s, v3.4s
449 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
450 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
451 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
452 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
453 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
454 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
455 ; CHECK-NEXT: movi v1.4s, #1
456 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
457 ; CHECK-NEXT: ret
458 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
459 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
460 %ret = zext <4 x i1> %cmp to <4 x i32>
461 ret <4 x i32> %ret
462 }
464 ; One all-ones divisor and power-of-two divisor divisor in even divisor
465 define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
466 ; CHECK-LABEL: test_srem_even_allones_and_poweroftwo:
467 ; CHECK: // %bb.0:
468 ; CHECK-NEXT: adrp x8, .LCPI14_0
469 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]
470 ; CHECK-NEXT: adrp x8, .LCPI14_1
471 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_1]
472 ; CHECK-NEXT: adrp x8, .LCPI14_2
473 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI14_2]
474 ; CHECK-NEXT: adrp x8, .LCPI14_3
475 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
476 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
477 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
478 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI14_3]
479 ; CHECK-NEXT: adrp x8, .LCPI14_4
480 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
481 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_4]
482 ; CHECK-NEXT: neg v3.4s, v3.4s
483 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
484 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
485 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
486 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
487 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
488 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
489 ; CHECK-NEXT: movi v1.4s, #1
490 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
491 ; CHECK-NEXT: ret
492 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
493 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
494 %ret = zext <4 x i1> %cmp to <4 x i32>
495 ret <4 x i32> %ret
496 }
498 ; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
499 define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
500 ; CHECK-LABEL: test_srem_odd_even_allones_and_poweroftwo:
501 ; CHECK: // %bb.0:
502 ; CHECK-NEXT: adrp x8, .LCPI15_0
503 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
504 ; CHECK-NEXT: adrp x8, .LCPI15_1
505 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]
506 ; CHECK-NEXT: adrp x8, .LCPI15_2
507 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI15_2]
508 ; CHECK-NEXT: adrp x8, .LCPI15_3
509 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
510 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
511 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
512 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI15_3]
513 ; CHECK-NEXT: adrp x8, .LCPI15_4
514 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
515 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_4]
516 ; CHECK-NEXT: neg v3.4s, v3.4s
517 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
518 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
519 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
520 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
521 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
522 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
523 ; CHECK-NEXT: movi v1.4s, #1
524 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
525 ; CHECK-NEXT: ret
526 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
527 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
528 %ret = zext <4 x i1> %cmp to <4 x i32>
529 ret <4 x i32> %ret
530 }
532 ;------------------------------------------------------------------------------;
534 ; One all-ones divisor and one one divisor in odd divisor
535 define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
536 ; CHECK-LABEL: test_srem_odd_allones_and_one:
537 ; CHECK: // %bb.0:
538 ; CHECK-NEXT: adrp x8, .LCPI16_0
539 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
540 ; CHECK-NEXT: adrp x8, .LCPI16_1
541 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_1]
542 ; CHECK-NEXT: adrp x8, .LCPI16_2
543 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI16_2]
544 ; CHECK-NEXT: adrp x8, .LCPI16_3
545 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
546 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
547 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
548 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI16_3]
549 ; CHECK-NEXT: adrp x8, .LCPI16_4
550 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
551 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI16_4]
552 ; CHECK-NEXT: neg v3.4s, v3.4s
553 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
554 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
555 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
556 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
557 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
558 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
559 ; CHECK-NEXT: movi v1.4s, #1
560 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
561 ; CHECK-NEXT: ret
562 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
563 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
564 %ret = zext <4 x i1> %cmp to <4 x i32>
565 ret <4 x i32> %ret
566 }
568 ; One all-ones divisor and one one divisor in even divisor
569 define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
570 ; CHECK-LABEL: test_srem_even_allones_and_one:
571 ; CHECK: // %bb.0:
572 ; CHECK-NEXT: adrp x8, .LCPI17_0
573 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
574 ; CHECK-NEXT: adrp x8, .LCPI17_1
575 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_1]
576 ; CHECK-NEXT: adrp x8, .LCPI17_2
577 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI17_2]
578 ; CHECK-NEXT: adrp x8, .LCPI17_3
579 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
580 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
581 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
582 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI17_3]
583 ; CHECK-NEXT: adrp x8, .LCPI17_4
584 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
585 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI17_4]
586 ; CHECK-NEXT: neg v3.4s, v3.4s
587 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
588 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
589 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
590 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
591 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
592 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
593 ; CHECK-NEXT: movi v1.4s, #1
594 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
595 ; CHECK-NEXT: ret
596 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
597 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
598 %ret = zext <4 x i1> %cmp to <4 x i32>
599 ret <4 x i32> %ret
600 }
602 ; One all-ones divisor and one one divisor in odd+even divisor
603 define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
604 ; CHECK-LABEL: test_srem_odd_even_allones_and_one:
605 ; CHECK: // %bb.0:
606 ; CHECK-NEXT: adrp x8, .LCPI18_0
607 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]
608 ; CHECK-NEXT: adrp x8, .LCPI18_1
609 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_1]
610 ; CHECK-NEXT: adrp x8, .LCPI18_2
611 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI18_2]
612 ; CHECK-NEXT: adrp x8, .LCPI18_3
613 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
614 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
615 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
616 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI18_3]
617 ; CHECK-NEXT: adrp x8, .LCPI18_4
618 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
619 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI18_4]
620 ; CHECK-NEXT: neg v3.4s, v3.4s
621 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
622 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
623 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
624 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
625 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
626 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
627 ; CHECK-NEXT: movi v1.4s, #1
628 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
629 ; CHECK-NEXT: ret
630 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
631 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
632 %ret = zext <4 x i1> %cmp to <4 x i32>
633 ret <4 x i32> %ret
634 }
636 ;------------------------------------------------------------------------------;
638 ; One power-of-two divisor divisor and one divisor in odd divisor
639 define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
640 ; CHECK-LABEL: test_srem_odd_poweroftwo_and_one:
641 ; CHECK: // %bb.0:
642 ; CHECK-NEXT: adrp x8, .LCPI19_0
643 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
644 ; CHECK-NEXT: adrp x8, .LCPI19_1
645 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI19_1]
646 ; CHECK-NEXT: adrp x8, .LCPI19_2
647 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI19_2]
648 ; CHECK-NEXT: adrp x8, .LCPI19_3
649 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
650 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
651 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
652 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI19_3]
653 ; CHECK-NEXT: adrp x8, .LCPI19_4
654 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
655 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI19_4]
656 ; CHECK-NEXT: neg v3.4s, v3.4s
657 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
658 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
659 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
660 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
661 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
662 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
663 ; CHECK-NEXT: movi v1.4s, #1
664 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
665 ; CHECK-NEXT: ret
666 %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
667 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
668 %ret = zext <4 x i1> %cmp to <4 x i32>
669 ret <4 x i32> %ret
670 }
672 ; One power-of-two divisor divisor and one divisor in even divisor
673 define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
674 ; CHECK-LABEL: test_srem_even_poweroftwo_and_one:
675 ; CHECK: // %bb.0:
676 ; CHECK-NEXT: adrp x8, .LCPI20_0
677 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0]
678 ; CHECK-NEXT: adrp x8, .LCPI20_1
679 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_1]
680 ; CHECK-NEXT: adrp x8, .LCPI20_2
681 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI20_2]
682 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
683 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
684 ; CHECK-NEXT: adrp x8, .LCPI20_3
685 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
686 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI20_3]
687 ; CHECK-NEXT: neg v2.4s, v2.4s
688 ; CHECK-NEXT: add v1.4s, v1.4s, v0.4s
689 ; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s
690 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
691 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
692 ; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
693 ; CHECK-NEXT: mls v0.4s, v1.4s, v4.4s
694 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
695 ; CHECK-NEXT: movi v1.4s, #1
696 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
697 ; CHECK-NEXT: ret
698 %srem = srem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
699 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
700 %ret = zext <4 x i1> %cmp to <4 x i32>
701 ret <4 x i32> %ret
702 }
704 ; One power-of-two divisor divisor and one divisor in odd+even divisor
705 define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
706 ; CHECK-LABEL: test_srem_odd_even_poweroftwo_and_one:
707 ; CHECK: // %bb.0:
708 ; CHECK-NEXT: adrp x8, .LCPI21_0
709 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_0]
710 ; CHECK-NEXT: adrp x8, .LCPI21_1
711 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_1]
712 ; CHECK-NEXT: adrp x8, .LCPI21_2
713 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI21_2]
714 ; CHECK-NEXT: adrp x8, .LCPI21_3
715 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
716 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
717 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
718 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI21_3]
719 ; CHECK-NEXT: adrp x8, .LCPI21_4
720 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
721 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI21_4]
722 ; CHECK-NEXT: neg v3.4s, v3.4s
723 ; CHECK-NEXT: sshl v3.4s, v1.4s, v3.4s
724 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
725 ; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
726 ; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
727 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
728 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
729 ; CHECK-NEXT: movi v1.4s, #1
730 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
731 ; CHECK-NEXT: ret
732 %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
733 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
734 %ret = zext <4 x i1> %cmp to <4 x i32>
735 ret <4 x i32> %ret
736 }
738 ;------------------------------------------------------------------------------;
740 define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
741 ; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
742 ; CHECK: // %bb.0:
743 ; CHECK-NEXT: adrp x8, .LCPI22_0
744 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0]
745 ; CHECK-NEXT: adrp x8, .LCPI22_1
746 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_1]
747 ; CHECK-NEXT: adrp x8, .LCPI22_2
748 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
749 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
750 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
751 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI22_2]
752 ; CHECK-NEXT: adrp x8, .LCPI22_3
753 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
754 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI22_3]
755 ; CHECK-NEXT: neg v4.4s, v4.4s
756 ; CHECK-NEXT: movi v3.2d, #0x000000ffffffff
757 ; CHECK-NEXT: sshl v4.4s, v1.4s, v4.4s
758 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
759 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
760 ; CHECK-NEXT: add v1.4s, v4.4s, v1.4s
761 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
762 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
763 ; CHECK-NEXT: movi v1.4s, #1
764 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
765 ; CHECK-NEXT: ret
766 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
767 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
768 %ret = zext <4 x i1> %cmp to <4 x i32>
769 ret <4 x i32> %ret
770 }
772 define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
773 ; CHECK-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
774 ; CHECK: // %bb.0:
775 ; CHECK-NEXT: adrp x8, .LCPI23_0
776 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0]
777 ; CHECK-NEXT: adrp x8, .LCPI23_1
778 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_1]
779 ; CHECK-NEXT: adrp x8, .LCPI23_2
780 ; CHECK-NEXT: smull2 v4.2d, v0.4s, v1.4s
781 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
782 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
783 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI23_2]
784 ; CHECK-NEXT: adrp x8, .LCPI23_3
785 ; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
786 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI23_3]
787 ; CHECK-NEXT: neg v4.4s, v4.4s
788 ; CHECK-NEXT: movi v3.2d, #0x000000ffffffff
789 ; CHECK-NEXT: sshl v4.4s, v1.4s, v4.4s
790 ; CHECK-NEXT: ushr v1.4s, v1.4s, #31
791 ; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
792 ; CHECK-NEXT: add v1.4s, v4.4s, v1.4s
793 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
794 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
795 ; CHECK-NEXT: movi v1.4s, #1
796 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
797 ; CHECK-NEXT: ret
798 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
799 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
800 %ret = zext <4 x i1> %cmp to <4 x i32>
801 ret <4 x i32> %ret
802 }