| blob | 3718b6bbc9de88a3b3b6fd1a57f3e9a02a9e7d94 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>)
36 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
37 ; CHECK-LABEL: v16i8:
38 ; CHECK: // %bb.0:
39 ; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b
40 ; CHECK-NEXT: cmge v1.16b, v1.16b, #0
41 ; CHECK-NEXT: cmge v0.16b, v0.16b, #0
42 ; CHECK-NEXT: cmge v5.16b, v2.16b, #0
43 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
44 ; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b
45 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v5.16b
46 ; CHECK-NEXT: movi v3.16b, #127
47 ; CHECK-NEXT: mvn v5.16b, v4.16b
48 ; CHECK-NEXT: mvn v1.16b, v1.16b
49 ; CHECK-NEXT: mvn v0.16b, v0.16b
50 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
51 ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
52 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
53 ; CHECK-NEXT: ret
54 %z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
55 ret <16 x i8> %z
56 }
58 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
59 ; CHECK-LABEL: v32i8:
60 ; CHECK: // %bb.0:
61 ; CHECK-NEXT: sub v4.16b, v0.16b, v2.16b
62 ; CHECK-NEXT: cmlt v16.16b, v4.16b, #0
63 ; CHECK-NEXT: movi v6.16b, #127
64 ; CHECK-NEXT: sub v7.16b, v1.16b, v3.16b
65 ; CHECK-NEXT: mvn v17.16b, v16.16b
66 ; CHECK-NEXT: bsl v6.16b, v16.16b, v17.16b
67 ; CHECK-NEXT: cmlt v16.16b, v7.16b, #0
68 ; CHECK-NEXT: movi v5.16b, #127
69 ; CHECK-NEXT: mvn v17.16b, v16.16b
70 ; CHECK-NEXT: bsl v5.16b, v16.16b, v17.16b
71 ; CHECK-NEXT: cmge v2.16b, v2.16b, #0
72 ; CHECK-NEXT: cmge v0.16b, v0.16b, #0
73 ; CHECK-NEXT: cmge v16.16b, v4.16b, #0
74 ; CHECK-NEXT: cmge v3.16b, v3.16b, #0
75 ; CHECK-NEXT: cmge v1.16b, v1.16b, #0
76 ; CHECK-NEXT: cmeq v2.16b, v0.16b, v2.16b
77 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v16.16b
78 ; CHECK-NEXT: cmge v16.16b, v7.16b, #0
79 ; CHECK-NEXT: cmeq v3.16b, v1.16b, v3.16b
80 ; CHECK-NEXT: cmeq v1.16b, v1.16b, v16.16b
81 ; CHECK-NEXT: mvn v2.16b, v2.16b
82 ; CHECK-NEXT: mvn v3.16b, v3.16b
83 ; CHECK-NEXT: mvn v0.16b, v0.16b
84 ; CHECK-NEXT: mvn v1.16b, v1.16b
85 ; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
86 ; CHECK-NEXT: and v1.16b, v3.16b, v1.16b
87 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
88 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
89 ; CHECK-NEXT: ret
90 %z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
91 ret <32 x i8> %z
92 }
94 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
95 ; CHECK-LABEL: v64i8:
96 ; CHECK: // %bb.0:
97 ; CHECK-NEXT: sub v16.16b, v0.16b, v4.16b
98 ; CHECK-NEXT: cmlt v24.16b, v16.16b, #0
99 ; CHECK-NEXT: movi v18.16b, #127
100 ; CHECK-NEXT: sub v19.16b, v1.16b, v5.16b
101 ; CHECK-NEXT: mvn v25.16b, v24.16b
102 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
103 ; CHECK-NEXT: cmlt v24.16b, v19.16b, #0
104 ; CHECK-NEXT: movi v20.16b, #127
105 ; CHECK-NEXT: sub v21.16b, v2.16b, v6.16b
106 ; CHECK-NEXT: mvn v25.16b, v24.16b
107 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
108 ; CHECK-NEXT: cmlt v24.16b, v21.16b, #0
109 ; CHECK-NEXT: movi v22.16b, #127
110 ; CHECK-NEXT: sub v23.16b, v3.16b, v7.16b
111 ; CHECK-NEXT: mvn v25.16b, v24.16b
112 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
113 ; CHECK-NEXT: cmlt v24.16b, v23.16b, #0
114 ; CHECK-NEXT: movi v17.16b, #127
115 ; CHECK-NEXT: mvn v25.16b, v24.16b
116 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
117 ; CHECK-NEXT: cmge v4.16b, v4.16b, #0
118 ; CHECK-NEXT: cmge v0.16b, v0.16b, #0
119 ; CHECK-NEXT: cmge v24.16b, v16.16b, #0
120 ; CHECK-NEXT: cmge v5.16b, v5.16b, #0
121 ; CHECK-NEXT: cmge v1.16b, v1.16b, #0
122 ; CHECK-NEXT: cmeq v4.16b, v0.16b, v4.16b
123 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v24.16b
124 ; CHECK-NEXT: cmge v24.16b, v19.16b, #0
125 ; CHECK-NEXT: cmge v6.16b, v6.16b, #0
126 ; CHECK-NEXT: cmge v2.16b, v2.16b, #0
127 ; CHECK-NEXT: cmeq v5.16b, v1.16b, v5.16b
128 ; CHECK-NEXT: cmeq v1.16b, v1.16b, v24.16b
129 ; CHECK-NEXT: cmge v24.16b, v21.16b, #0
130 ; CHECK-NEXT: mvn v4.16b, v4.16b
131 ; CHECK-NEXT: mvn v0.16b, v0.16b
132 ; CHECK-NEXT: cmge v7.16b, v7.16b, #0
133 ; CHECK-NEXT: cmge v3.16b, v3.16b, #0
134 ; CHECK-NEXT: cmeq v6.16b, v2.16b, v6.16b
135 ; CHECK-NEXT: cmeq v2.16b, v2.16b, v24.16b
136 ; CHECK-NEXT: cmge v24.16b, v23.16b, #0
137 ; CHECK-NEXT: and v0.16b, v4.16b, v0.16b
138 ; CHECK-NEXT: mvn v4.16b, v5.16b
139 ; CHECK-NEXT: mvn v1.16b, v1.16b
140 ; CHECK-NEXT: cmeq v7.16b, v3.16b, v7.16b
141 ; CHECK-NEXT: cmeq v3.16b, v3.16b, v24.16b
142 ; CHECK-NEXT: and v1.16b, v4.16b, v1.16b
143 ; CHECK-NEXT: mvn v4.16b, v6.16b
144 ; CHECK-NEXT: mvn v2.16b, v2.16b
145 ; CHECK-NEXT: and v2.16b, v4.16b, v2.16b
146 ; CHECK-NEXT: mvn v4.16b, v7.16b
147 ; CHECK-NEXT: mvn v3.16b, v3.16b
148 ; CHECK-NEXT: and v3.16b, v4.16b, v3.16b
149 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
150 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
151 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
152 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
153 ; CHECK-NEXT: ret
154 %z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
155 ret <64 x i8> %z
156 }
158 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
159 ; CHECK-LABEL: v8i16:
160 ; CHECK: // %bb.0:
161 ; CHECK-NEXT: sub v2.8h, v0.8h, v1.8h
162 ; CHECK-NEXT: cmge v1.8h, v1.8h, #0
163 ; CHECK-NEXT: cmge v0.8h, v0.8h, #0
164 ; CHECK-NEXT: cmge v5.8h, v2.8h, #0
165 ; CHECK-NEXT: cmlt v4.8h, v2.8h, #0
166 ; CHECK-NEXT: cmeq v1.8h, v0.8h, v1.8h
167 ; CHECK-NEXT: cmeq v0.8h, v0.8h, v5.8h
168 ; CHECK-NEXT: mvni v3.8h, #128, lsl #8
169 ; CHECK-NEXT: mvn v5.16b, v4.16b
170 ; CHECK-NEXT: mvn v1.16b, v1.16b
171 ; CHECK-NEXT: mvn v0.16b, v0.16b
172 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
173 ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
174 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
175 ; CHECK-NEXT: ret
176 %z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
177 ret <8 x i16> %z
178 }
180 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
181 ; CHECK-LABEL: v16i16:
182 ; CHECK: // %bb.0:
183 ; CHECK-NEXT: sub v4.8h, v0.8h, v2.8h
184 ; CHECK-NEXT: cmlt v16.8h, v4.8h, #0
185 ; CHECK-NEXT: mvni v6.8h, #128, lsl #8
186 ; CHECK-NEXT: sub v7.8h, v1.8h, v3.8h
187 ; CHECK-NEXT: mvn v17.16b, v16.16b
188 ; CHECK-NEXT: bsl v6.16b, v16.16b, v17.16b
189 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
190 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
191 ; CHECK-NEXT: mvn v17.16b, v16.16b
192 ; CHECK-NEXT: bsl v5.16b, v16.16b, v17.16b
193 ; CHECK-NEXT: cmge v2.8h, v2.8h, #0
194 ; CHECK-NEXT: cmge v0.8h, v0.8h, #0
195 ; CHECK-NEXT: cmge v16.8h, v4.8h, #0
196 ; CHECK-NEXT: cmge v3.8h, v3.8h, #0
197 ; CHECK-NEXT: cmge v1.8h, v1.8h, #0
198 ; CHECK-NEXT: cmeq v2.8h, v0.8h, v2.8h
199 ; CHECK-NEXT: cmeq v0.8h, v0.8h, v16.8h
200 ; CHECK-NEXT: cmge v16.8h, v7.8h, #0
201 ; CHECK-NEXT: cmeq v3.8h, v1.8h, v3.8h
202 ; CHECK-NEXT: cmeq v1.8h, v1.8h, v16.8h
203 ; CHECK-NEXT: mvn v2.16b, v2.16b
204 ; CHECK-NEXT: mvn v3.16b, v3.16b
205 ; CHECK-NEXT: mvn v0.16b, v0.16b
206 ; CHECK-NEXT: mvn v1.16b, v1.16b
207 ; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
208 ; CHECK-NEXT: and v1.16b, v3.16b, v1.16b
209 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
210 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
211 ; CHECK-NEXT: ret
212 %z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
213 ret <16 x i16> %z
214 }
216 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
217 ; CHECK-LABEL: v32i16:
218 ; CHECK: // %bb.0:
219 ; CHECK-NEXT: sub v16.8h, v0.8h, v4.8h
220 ; CHECK-NEXT: cmlt v24.8h, v16.8h, #0
221 ; CHECK-NEXT: mvni v18.8h, #128, lsl #8
222 ; CHECK-NEXT: sub v19.8h, v1.8h, v5.8h
223 ; CHECK-NEXT: mvn v25.16b, v24.16b
224 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
225 ; CHECK-NEXT: cmlt v24.8h, v19.8h, #0
226 ; CHECK-NEXT: mvni v20.8h, #128, lsl #8
227 ; CHECK-NEXT: sub v21.8h, v2.8h, v6.8h
228 ; CHECK-NEXT: mvn v25.16b, v24.16b
229 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
230 ; CHECK-NEXT: cmlt v24.8h, v21.8h, #0
231 ; CHECK-NEXT: mvni v22.8h, #128, lsl #8
232 ; CHECK-NEXT: sub v23.8h, v3.8h, v7.8h
233 ; CHECK-NEXT: mvn v25.16b, v24.16b
234 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
235 ; CHECK-NEXT: cmlt v24.8h, v23.8h, #0
236 ; CHECK-NEXT: mvni v17.8h, #128, lsl #8
237 ; CHECK-NEXT: mvn v25.16b, v24.16b
238 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
239 ; CHECK-NEXT: cmge v4.8h, v4.8h, #0
240 ; CHECK-NEXT: cmge v0.8h, v0.8h, #0
241 ; CHECK-NEXT: cmge v24.8h, v16.8h, #0
242 ; CHECK-NEXT: cmge v5.8h, v5.8h, #0
243 ; CHECK-NEXT: cmge v1.8h, v1.8h, #0
244 ; CHECK-NEXT: cmeq v4.8h, v0.8h, v4.8h
245 ; CHECK-NEXT: cmeq v0.8h, v0.8h, v24.8h
246 ; CHECK-NEXT: cmge v24.8h, v19.8h, #0
247 ; CHECK-NEXT: cmge v6.8h, v6.8h, #0
248 ; CHECK-NEXT: cmge v2.8h, v2.8h, #0
249 ; CHECK-NEXT: cmeq v5.8h, v1.8h, v5.8h
250 ; CHECK-NEXT: cmeq v1.8h, v1.8h, v24.8h
251 ; CHECK-NEXT: cmge v24.8h, v21.8h, #0
252 ; CHECK-NEXT: mvn v4.16b, v4.16b
253 ; CHECK-NEXT: mvn v0.16b, v0.16b
254 ; CHECK-NEXT: cmge v7.8h, v7.8h, #0
255 ; CHECK-NEXT: cmge v3.8h, v3.8h, #0
256 ; CHECK-NEXT: cmeq v6.8h, v2.8h, v6.8h
257 ; CHECK-NEXT: cmeq v2.8h, v2.8h, v24.8h
258 ; CHECK-NEXT: cmge v24.8h, v23.8h, #0
259 ; CHECK-NEXT: and v0.16b, v4.16b, v0.16b
260 ; CHECK-NEXT: mvn v4.16b, v5.16b
261 ; CHECK-NEXT: mvn v1.16b, v1.16b
262 ; CHECK-NEXT: cmeq v7.8h, v3.8h, v7.8h
263 ; CHECK-NEXT: cmeq v3.8h, v3.8h, v24.8h
264 ; CHECK-NEXT: and v1.16b, v4.16b, v1.16b
265 ; CHECK-NEXT: mvn v4.16b, v6.16b
266 ; CHECK-NEXT: mvn v2.16b, v2.16b
267 ; CHECK-NEXT: and v2.16b, v4.16b, v2.16b
268 ; CHECK-NEXT: mvn v4.16b, v7.16b
269 ; CHECK-NEXT: mvn v3.16b, v3.16b
270 ; CHECK-NEXT: and v3.16b, v4.16b, v3.16b
271 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
272 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
273 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
274 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
275 ; CHECK-NEXT: ret
276 %z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
277 ret <32 x i16> %z
278 }
280 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
281 ; CHECK-LABEL: v8i8:
282 ; CHECK: // %bb.0:
283 ; CHECK-NEXT: ldr d0, [x0]
284 ; CHECK-NEXT: ldr d1, [x1]
285 ; CHECK-NEXT: movi v2.8b, #127
286 ; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
287 ; CHECK-NEXT: cmge v1.8b, v1.8b, #0
288 ; CHECK-NEXT: cmge v0.8b, v0.8b, #0
289 ; CHECK-NEXT: cmge v5.8b, v3.8b, #0
290 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
291 ; CHECK-NEXT: cmeq v1.8b, v0.8b, v1.8b
292 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v5.8b
293 ; CHECK-NEXT: mvn v5.8b, v4.8b
294 ; CHECK-NEXT: mvn v1.8b, v1.8b
295 ; CHECK-NEXT: mvn v0.8b, v0.8b
296 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
297 ; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
298 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
299 ; CHECK-NEXT: str d0, [x2]
300 ; CHECK-NEXT: ret
301 %x = load <8 x i8>, <8 x i8>* %px
302 %y = load <8 x i8>, <8 x i8>* %py
303 %z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
304 store <8 x i8> %z, <8 x i8>* %pz
305 ret void
306 }
308 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
309 ; CHECK-LABEL: v4i8:
310 ; CHECK: // %bb.0:
311 ; CHECK-NEXT: ldrb w8, [x0]
312 ; CHECK-NEXT: ldrb w9, [x1]
313 ; CHECK-NEXT: ldrb w10, [x0, #1]
314 ; CHECK-NEXT: ldrb w11, [x1, #1]
315 ; CHECK-NEXT: ldrb w12, [x0, #2]
316 ; CHECK-NEXT: fmov s0, w8
317 ; CHECK-NEXT: ldrb w8, [x1, #2]
318 ; CHECK-NEXT: fmov s1, w9
319 ; CHECK-NEXT: mov v0.h[1], w10
320 ; CHECK-NEXT: ldrb w9, [x0, #3]
321 ; CHECK-NEXT: ldrb w10, [x1, #3]
322 ; CHECK-NEXT: mov v1.h[1], w11
323 ; CHECK-NEXT: mov v0.h[2], w12
324 ; CHECK-NEXT: mov v1.h[2], w8
325 ; CHECK-NEXT: mov v0.h[3], w9
326 ; CHECK-NEXT: mov v1.h[3], w10
327 ; CHECK-NEXT: shl v1.4h, v1.4h, #8
328 ; CHECK-NEXT: shl v0.4h, v0.4h, #8
329 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
330 ; CHECK-NEXT: cmge v1.4h, v1.4h, #0
331 ; CHECK-NEXT: cmge v0.4h, v0.4h, #0
332 ; CHECK-NEXT: cmge v5.4h, v3.4h, #0
333 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
334 ; CHECK-NEXT: cmeq v1.4h, v0.4h, v1.4h
335 ; CHECK-NEXT: cmeq v0.4h, v0.4h, v5.4h
336 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
337 ; CHECK-NEXT: mvn v5.8b, v4.8b
338 ; CHECK-NEXT: mvn v1.8b, v1.8b
339 ; CHECK-NEXT: mvn v0.8b, v0.8b
340 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
341 ; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
342 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
343 ; CHECK-NEXT: sshr v0.4h, v0.4h, #8
344 ; CHECK-NEXT: xtn v0.8b, v0.8h
345 ; CHECK-NEXT: str s0, [x2]
346 ; CHECK-NEXT: ret
347 %x = load <4 x i8>, <4 x i8>* %px
348 %y = load <4 x i8>, <4 x i8>* %py
349 %z = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
350 store <4 x i8> %z, <4 x i8>* %pz
351 ret void
352 }
354 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
355 ; CHECK-LABEL: v2i8:
356 ; CHECK: // %bb.0:
357 ; CHECK-NEXT: ldrb w8, [x0]
358 ; CHECK-NEXT: ldrb w9, [x1]
359 ; CHECK-NEXT: ldrb w10, [x0, #1]
360 ; CHECK-NEXT: ldrb w11, [x1, #1]
361 ; CHECK-NEXT: fmov s0, w8
362 ; CHECK-NEXT: fmov s2, w9
363 ; CHECK-NEXT: mov v0.s[1], w10
364 ; CHECK-NEXT: mov v2.s[1], w11
365 ; CHECK-NEXT: shl v2.2s, v2.2s, #24
366 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
367 ; CHECK-NEXT: sub v3.2s, v0.2s, v2.2s
368 ; CHECK-NEXT: cmge v2.2s, v2.2s, #0
369 ; CHECK-NEXT: cmge v0.2s, v0.2s, #0
370 ; CHECK-NEXT: cmge v5.2s, v3.2s, #0
371 ; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
372 ; CHECK-NEXT: cmeq v2.2s, v0.2s, v2.2s
373 ; CHECK-NEXT: cmeq v0.2s, v0.2s, v5.2s
374 ; CHECK-NEXT: mvni v1.2s, #128, lsl #24
375 ; CHECK-NEXT: mvn v5.8b, v4.8b
376 ; CHECK-NEXT: mvn v2.8b, v2.8b
377 ; CHECK-NEXT: mvn v0.8b, v0.8b
378 ; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
379 ; CHECK-NEXT: and v0.8b, v2.8b, v0.8b
380 ; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
381 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
382 ; CHECK-NEXT: mov w8, v0.s[1]
383 ; CHECK-NEXT: fmov w9, s0
384 ; CHECK-NEXT: strb w8, [x2, #1]
385 ; CHECK-NEXT: strb w9, [x2]
386 ; CHECK-NEXT: ret
387 %x = load <2 x i8>, <2 x i8>* %px
388 %y = load <2 x i8>, <2 x i8>* %py
389 %z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
390 store <2 x i8> %z, <2 x i8>* %pz
391 ret void
392 }
394 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
395 ; CHECK-LABEL: v4i16:
396 ; CHECK: // %bb.0:
397 ; CHECK-NEXT: ldr d0, [x0]
398 ; CHECK-NEXT: ldr d1, [x1]
399 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
400 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
401 ; CHECK-NEXT: cmge v1.4h, v1.4h, #0
402 ; CHECK-NEXT: cmge v0.4h, v0.4h, #0
403 ; CHECK-NEXT: cmge v5.4h, v3.4h, #0
404 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
405 ; CHECK-NEXT: cmeq v1.4h, v0.4h, v1.4h
406 ; CHECK-NEXT: cmeq v0.4h, v0.4h, v5.4h
407 ; CHECK-NEXT: mvn v5.8b, v4.8b
408 ; CHECK-NEXT: mvn v1.8b, v1.8b
409 ; CHECK-NEXT: mvn v0.8b, v0.8b
410 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
411 ; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
412 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
413 ; CHECK-NEXT: str d0, [x2]
414 ; CHECK-NEXT: ret
415 %x = load <4 x i16>, <4 x i16>* %px
416 %y = load <4 x i16>, <4 x i16>* %py
417 %z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
418 store <4 x i16> %z, <4 x i16>* %pz
419 ret void
420 }
422 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
423 ; CHECK-LABEL: v2i16:
424 ; CHECK: // %bb.0:
425 ; CHECK-NEXT: ldrh w8, [x0]
426 ; CHECK-NEXT: ldrh w9, [x1]
427 ; CHECK-NEXT: ldrh w10, [x0, #2]
428 ; CHECK-NEXT: ldrh w11, [x1, #2]
429 ; CHECK-NEXT: fmov s0, w8
430 ; CHECK-NEXT: fmov s2, w9
431 ; CHECK-NEXT: mov v0.s[1], w10
432 ; CHECK-NEXT: mov v2.s[1], w11
433 ; CHECK-NEXT: shl v2.2s, v2.2s, #16
434 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
435 ; CHECK-NEXT: sub v3.2s, v0.2s, v2.2s
436 ; CHECK-NEXT: cmge v2.2s, v2.2s, #0
437 ; CHECK-NEXT: cmge v0.2s, v0.2s, #0
438 ; CHECK-NEXT: cmge v5.2s, v3.2s, #0
439 ; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
440 ; CHECK-NEXT: cmeq v2.2s, v0.2s, v2.2s
441 ; CHECK-NEXT: cmeq v0.2s, v0.2s, v5.2s
442 ; CHECK-NEXT: mvni v1.2s, #128, lsl #24
443 ; CHECK-NEXT: mvn v5.8b, v4.8b
444 ; CHECK-NEXT: mvn v2.8b, v2.8b
445 ; CHECK-NEXT: mvn v0.8b, v0.8b
446 ; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
447 ; CHECK-NEXT: and v0.8b, v2.8b, v0.8b
448 ; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
449 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
450 ; CHECK-NEXT: mov w8, v0.s[1]
451 ; CHECK-NEXT: fmov w9, s0
452 ; CHECK-NEXT: strh w8, [x2, #2]
453 ; CHECK-NEXT: strh w9, [x2]
454 ; CHECK-NEXT: ret
455 %x = load <2 x i16>, <2 x i16>* %px
456 %y = load <2 x i16>, <2 x i16>* %py
457 %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
458 store <2 x i16> %z, <2 x i16>* %pz
459 ret void
460 }
462 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
463 ; CHECK-LABEL: v12i8:
464 ; CHECK: // %bb.0:
465 ; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b
466 ; CHECK-NEXT: cmge v1.16b, v1.16b, #0
467 ; CHECK-NEXT: cmge v0.16b, v0.16b, #0
468 ; CHECK-NEXT: cmge v5.16b, v2.16b, #0
469 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
470 ; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b
471 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v5.16b
472 ; CHECK-NEXT: movi v3.16b, #127
473 ; CHECK-NEXT: mvn v5.16b, v4.16b
474 ; CHECK-NEXT: mvn v1.16b, v1.16b
475 ; CHECK-NEXT: mvn v0.16b, v0.16b
476 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
477 ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
478 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
479 ; CHECK-NEXT: ret
480 %z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
481 ret <12 x i8> %z
482 }
484 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
485 ; CHECK-LABEL: v12i16:
486 ; CHECK: // %bb.0:
487 ; CHECK-NEXT: ldp q0, q1, [x0]
488 ; CHECK-NEXT: ldp q3, q2, [x1]
489 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
490 ; CHECK-NEXT: mvni v4.8h, #128, lsl #8
491 ; CHECK-NEXT: sub v6.8h, v1.8h, v2.8h
492 ; CHECK-NEXT: cmlt v16.8h, v6.8h, #0
493 ; CHECK-NEXT: sub v7.8h, v0.8h, v3.8h
494 ; CHECK-NEXT: mvn v17.16b, v16.16b
495 ; CHECK-NEXT: bsl v5.16b, v16.16b, v17.16b
496 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
497 ; CHECK-NEXT: mvn v17.16b, v16.16b
498 ; CHECK-NEXT: bsl v4.16b, v16.16b, v17.16b
499 ; CHECK-NEXT: cmge v2.8h, v2.8h, #0
500 ; CHECK-NEXT: cmge v1.8h, v1.8h, #0
501 ; CHECK-NEXT: cmge v16.8h, v6.8h, #0
502 ; CHECK-NEXT: cmge v3.8h, v3.8h, #0
503 ; CHECK-NEXT: cmge v0.8h, v0.8h, #0
504 ; CHECK-NEXT: cmeq v2.8h, v1.8h, v2.8h
505 ; CHECK-NEXT: cmeq v1.8h, v1.8h, v16.8h
506 ; CHECK-NEXT: cmge v16.8h, v7.8h, #0
507 ; CHECK-NEXT: cmeq v3.8h, v0.8h, v3.8h
508 ; CHECK-NEXT: cmeq v0.8h, v0.8h, v16.8h
509 ; CHECK-NEXT: mvn v2.16b, v2.16b
510 ; CHECK-NEXT: mvn v3.16b, v3.16b
511 ; CHECK-NEXT: mvn v1.16b, v1.16b
512 ; CHECK-NEXT: mvn v0.16b, v0.16b
513 ; CHECK-NEXT: and v1.16b, v2.16b, v1.16b
514 ; CHECK-NEXT: and v0.16b, v3.16b, v0.16b
515 ; CHECK-NEXT: bsl v1.16b, v5.16b, v6.16b
516 ; CHECK-NEXT: bsl v0.16b, v4.16b, v7.16b
517 ; CHECK-NEXT: str q0, [x2]
518 ; CHECK-NEXT: str d1, [x2, #16]
519 ; CHECK-NEXT: ret
520 %x = load <12 x i16>, <12 x i16>* %px
521 %y = load <12 x i16>, <12 x i16>* %py
522 %z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
523 store <12 x i16> %z, <12 x i16>* %pz
524 ret void
525 }
527 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
528 ; CHECK-LABEL: v1i8:
529 ; CHECK: // %bb.0:
530 ; CHECK-NEXT: ldr b0, [x0]
531 ; CHECK-NEXT: ldr b1, [x1]
532 ; CHECK-NEXT: movi v2.8b, #127
533 ; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
534 ; CHECK-NEXT: cmge v1.8b, v1.8b, #0
535 ; CHECK-NEXT: cmge v0.8b, v0.8b, #0
536 ; CHECK-NEXT: cmge v5.8b, v3.8b, #0
537 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
538 ; CHECK-NEXT: cmeq v1.8b, v0.8b, v1.8b
539 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v5.8b
540 ; CHECK-NEXT: mvn v5.8b, v4.8b
541 ; CHECK-NEXT: mvn v1.8b, v1.8b
542 ; CHECK-NEXT: mvn v0.8b, v0.8b
543 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
544 ; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
545 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
546 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
547 ; CHECK-NEXT: ret
548 %x = load <1 x i8>, <1 x i8>* %px
549 %y = load <1 x i8>, <1 x i8>* %py
550 %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
551 store <1 x i8> %z, <1 x i8>* %pz
552 ret void
553 }
555 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
556 ; CHECK-LABEL: v1i16:
557 ; CHECK: // %bb.0:
558 ; CHECK-NEXT: ldr h0, [x0]
559 ; CHECK-NEXT: ldr h1, [x1]
560 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
561 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
562 ; CHECK-NEXT: cmge v1.4h, v1.4h, #0
563 ; CHECK-NEXT: cmge v0.4h, v0.4h, #0
564 ; CHECK-NEXT: cmge v5.4h, v3.4h, #0
565 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
566 ; CHECK-NEXT: cmeq v1.4h, v0.4h, v1.4h
567 ; CHECK-NEXT: cmeq v0.4h, v0.4h, v5.4h
568 ; CHECK-NEXT: mvn v5.8b, v4.8b
569 ; CHECK-NEXT: mvn v1.8b, v1.8b
570 ; CHECK-NEXT: mvn v0.8b, v0.8b
571 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
572 ; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
573 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
574 ; CHECK-NEXT: str h0, [x2]
575 ; CHECK-NEXT: ret
576 %x = load <1 x i16>, <1 x i16>* %px
577 %y = load <1 x i16>, <1 x i16>* %py
578 %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
579 store <1 x i16> %z, <1 x i16>* %pz
580 ret void
581 }
583 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
584 ; CHECK-LABEL: v16i4:
585 ; CHECK: // %bb.0:
586 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
587 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
588 ; CHECK-NEXT: sub v3.16b, v0.16b, v1.16b
589 ; CHECK-NEXT: cmge v1.16b, v1.16b, #0
590 ; CHECK-NEXT: cmge v0.16b, v0.16b, #0
591 ; CHECK-NEXT: cmge v5.16b, v3.16b, #0
592 ; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
593 ; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b
594 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v5.16b
595 ; CHECK-NEXT: movi v2.16b, #127
596 ; CHECK-NEXT: mvn v5.16b, v4.16b
597 ; CHECK-NEXT: mvn v1.16b, v1.16b
598 ; CHECK-NEXT: mvn v0.16b, v0.16b
599 ; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
600 ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
601 ; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
602 ; CHECK-NEXT: sshr v0.16b, v0.16b, #4
603 ; CHECK-NEXT: ret
604 %z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
605 ret <16 x i4> %z
606 }
608 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
609 ; CHECK-LABEL: v16i1:
610 ; CHECK: // %bb.0:
611 ; CHECK-NEXT: shl v1.16b, v1.16b, #7
612 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
613 ; CHECK-NEXT: sub v3.16b, v0.16b, v1.16b
614 ; CHECK-NEXT: cmge v1.16b, v1.16b, #0
615 ; CHECK-NEXT: cmge v0.16b, v0.16b, #0
616 ; CHECK-NEXT: cmge v5.16b, v3.16b, #0
617 ; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
618 ; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b
619 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v5.16b
620 ; CHECK-NEXT: movi v2.16b, #127
621 ; CHECK-NEXT: mvn v5.16b, v4.16b
622 ; CHECK-NEXT: mvn v1.16b, v1.16b
623 ; CHECK-NEXT: mvn v0.16b, v0.16b
624 ; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
625 ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
626 ; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
627 ; CHECK-NEXT: sshr v0.16b, v0.16b, #7
628 ; CHECK-NEXT: ret
629 %z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
630 ret <16 x i1> %z
631 }
633 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
634 ; CHECK-LABEL: v2i32:
635 ; CHECK: // %bb.0:
636 ; CHECK-NEXT: sub v2.2s, v0.2s, v1.2s
637 ; CHECK-NEXT: cmge v1.2s, v1.2s, #0
638 ; CHECK-NEXT: cmge v0.2s, v0.2s, #0
639 ; CHECK-NEXT: cmge v5.2s, v2.2s, #0
640 ; CHECK-NEXT: cmlt v4.2s, v2.2s, #0
641 ; CHECK-NEXT: cmeq v1.2s, v0.2s, v1.2s
642 ; CHECK-NEXT: cmeq v0.2s, v0.2s, v5.2s
643 ; CHECK-NEXT: mvni v3.2s, #128, lsl #24
644 ; CHECK-NEXT: mvn v5.8b, v4.8b
645 ; CHECK-NEXT: mvn v1.8b, v1.8b
646 ; CHECK-NEXT: mvn v0.8b, v0.8b
647 ; CHECK-NEXT: bsl v3.8b, v4.8b, v5.8b
648 ; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
649 ; CHECK-NEXT: bsl v0.8b, v3.8b, v2.8b
650 ; CHECK-NEXT: ret
651 %z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
652 ret <2 x i32> %z
653 }
655 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
656 ; CHECK-LABEL: v4i32:
657 ; CHECK: // %bb.0:
658 ; CHECK-NEXT: sub v2.4s, v0.4s, v1.4s
659 ; CHECK-NEXT: cmge v1.4s, v1.4s, #0
660 ; CHECK-NEXT: cmge v0.4s, v0.4s, #0
661 ; CHECK-NEXT: cmge v5.4s, v2.4s, #0
662 ; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
663 ; CHECK-NEXT: cmeq v1.4s, v0.4s, v1.4s
664 ; CHECK-NEXT: cmeq v0.4s, v0.4s, v5.4s
665 ; CHECK-NEXT: mvni v3.4s, #128, lsl #24
666 ; CHECK-NEXT: mvn v5.16b, v4.16b
667 ; CHECK-NEXT: mvn v1.16b, v1.16b
668 ; CHECK-NEXT: mvn v0.16b, v0.16b
669 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
670 ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
671 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
672 ; CHECK-NEXT: ret
673 %z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
674 ret <4 x i32> %z
675 }
677 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
678 ; CHECK-LABEL: v8i32:
679 ; CHECK: // %bb.0:
680 ; CHECK-NEXT: sub v4.4s, v0.4s, v2.4s
681 ; CHECK-NEXT: cmlt v16.4s, v4.4s, #0
682 ; CHECK-NEXT: mvni v6.4s, #128, lsl #24
683 ; CHECK-NEXT: sub v7.4s, v1.4s, v3.4s
684 ; CHECK-NEXT: mvn v17.16b, v16.16b
685 ; CHECK-NEXT: bsl v6.16b, v16.16b, v17.16b
686 ; CHECK-NEXT: cmlt v16.4s, v7.4s, #0
687 ; CHECK-NEXT: mvni v5.4s, #128, lsl #24
688 ; CHECK-NEXT: mvn v17.16b, v16.16b
689 ; CHECK-NEXT: bsl v5.16b, v16.16b, v17.16b
690 ; CHECK-NEXT: cmge v2.4s, v2.4s, #0
691 ; CHECK-NEXT: cmge v0.4s, v0.4s, #0
692 ; CHECK-NEXT: cmge v16.4s, v4.4s, #0
693 ; CHECK-NEXT: cmge v3.4s, v3.4s, #0
694 ; CHECK-NEXT: cmge v1.4s, v1.4s, #0
695 ; CHECK-NEXT: cmeq v2.4s, v0.4s, v2.4s
696 ; CHECK-NEXT: cmeq v0.4s, v0.4s, v16.4s
697 ; CHECK-NEXT: cmge v16.4s, v7.4s, #0
698 ; CHECK-NEXT: cmeq v3.4s, v1.4s, v3.4s
699 ; CHECK-NEXT: cmeq v1.4s, v1.4s, v16.4s
700 ; CHECK-NEXT: mvn v2.16b, v2.16b
701 ; CHECK-NEXT: mvn v3.16b, v3.16b
702 ; CHECK-NEXT: mvn v0.16b, v0.16b
703 ; CHECK-NEXT: mvn v1.16b, v1.16b
704 ; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
705 ; CHECK-NEXT: and v1.16b, v3.16b, v1.16b
706 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
707 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
708 ; CHECK-NEXT: ret
709 %z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
710 ret <8 x i32> %z
711 }
713 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
714 ; CHECK-LABEL: v16i32:
715 ; CHECK: // %bb.0:
716 ; CHECK-NEXT: sub v16.4s, v0.4s, v4.4s
717 ; CHECK-NEXT: cmlt v24.4s, v16.4s, #0
718 ; CHECK-NEXT: mvni v18.4s, #128, lsl #24
719 ; CHECK-NEXT: sub v19.4s, v1.4s, v5.4s
720 ; CHECK-NEXT: mvn v25.16b, v24.16b
721 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
722 ; CHECK-NEXT: cmlt v24.4s, v19.4s, #0
723 ; CHECK-NEXT: mvni v20.4s, #128, lsl #24
724 ; CHECK-NEXT: sub v21.4s, v2.4s, v6.4s
725 ; CHECK-NEXT: mvn v25.16b, v24.16b
726 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
727 ; CHECK-NEXT: cmlt v24.4s, v21.4s, #0
728 ; CHECK-NEXT: mvni v22.4s, #128, lsl #24
729 ; CHECK-NEXT: sub v23.4s, v3.4s, v7.4s
730 ; CHECK-NEXT: mvn v25.16b, v24.16b
731 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
732 ; CHECK-NEXT: cmlt v24.4s, v23.4s, #0
733 ; CHECK-NEXT: mvni v17.4s, #128, lsl #24
734 ; CHECK-NEXT: mvn v25.16b, v24.16b
735 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
736 ; CHECK-NEXT: cmge v4.4s, v4.4s, #0
737 ; CHECK-NEXT: cmge v0.4s, v0.4s, #0
738 ; CHECK-NEXT: cmge v24.4s, v16.4s, #0
739 ; CHECK-NEXT: cmge v5.4s, v5.4s, #0
740 ; CHECK-NEXT: cmge v1.4s, v1.4s, #0
741 ; CHECK-NEXT: cmeq v4.4s, v0.4s, v4.4s
742 ; CHECK-NEXT: cmeq v0.4s, v0.4s, v24.4s
743 ; CHECK-NEXT: cmge v24.4s, v19.4s, #0
744 ; CHECK-NEXT: cmge v6.4s, v6.4s, #0
745 ; CHECK-NEXT: cmge v2.4s, v2.4s, #0
746 ; CHECK-NEXT: cmeq v5.4s, v1.4s, v5.4s
747 ; CHECK-NEXT: cmeq v1.4s, v1.4s, v24.4s
748 ; CHECK-NEXT: cmge v24.4s, v21.4s, #0
749 ; CHECK-NEXT: mvn v4.16b, v4.16b
750 ; CHECK-NEXT: mvn v0.16b, v0.16b
751 ; CHECK-NEXT: cmge v7.4s, v7.4s, #0
752 ; CHECK-NEXT: cmge v3.4s, v3.4s, #0
753 ; CHECK-NEXT: cmeq v6.4s, v2.4s, v6.4s
754 ; CHECK-NEXT: cmeq v2.4s, v2.4s, v24.4s
755 ; CHECK-NEXT: cmge v24.4s, v23.4s, #0
756 ; CHECK-NEXT: and v0.16b, v4.16b, v0.16b
757 ; CHECK-NEXT: mvn v4.16b, v5.16b
758 ; CHECK-NEXT: mvn v1.16b, v1.16b
759 ; CHECK-NEXT: cmeq v7.4s, v3.4s, v7.4s
760 ; CHECK-NEXT: cmeq v3.4s, v3.4s, v24.4s
761 ; CHECK-NEXT: and v1.16b, v4.16b, v1.16b
762 ; CHECK-NEXT: mvn v4.16b, v6.16b
763 ; CHECK-NEXT: mvn v2.16b, v2.16b
764 ; CHECK-NEXT: and v2.16b, v4.16b, v2.16b
765 ; CHECK-NEXT: mvn v4.16b, v7.16b
766 ; CHECK-NEXT: mvn v3.16b, v3.16b
767 ; CHECK-NEXT: and v3.16b, v4.16b, v3.16b
768 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
769 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
770 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
771 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
772 ; CHECK-NEXT: ret
773 %z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
774 ret <16 x i32> %z
775 }
777 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
778 ; CHECK-LABEL: v2i64:
779 ; CHECK: // %bb.0:
780 ; CHECK-NEXT: sub v2.2d, v0.2d, v1.2d
781 ; CHECK-NEXT: cmge v1.2d, v1.2d, #0
782 ; CHECK-NEXT: cmge v0.2d, v0.2d, #0
783 ; CHECK-NEXT: cmge v5.2d, v2.2d, #0
784 ; CHECK-NEXT: mov x8, #9223372036854775807
785 ; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
786 ; CHECK-NEXT: cmeq v1.2d, v0.2d, v1.2d
787 ; CHECK-NEXT: cmeq v0.2d, v0.2d, v5.2d
788 ; CHECK-NEXT: dup v4.2d, x8
789 ; CHECK-NEXT: mvn v5.16b, v3.16b
790 ; CHECK-NEXT: mvn v1.16b, v1.16b
791 ; CHECK-NEXT: mvn v0.16b, v0.16b
792 ; CHECK-NEXT: bsl v4.16b, v3.16b, v5.16b
793 ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
794 ; CHECK-NEXT: bsl v0.16b, v4.16b, v2.16b
795 ; CHECK-NEXT: ret
796 %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
797 ret <2 x i64> %z
798 }
800 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
801 ; CHECK-LABEL: v4i64:
802 ; CHECK: // %bb.0:
803 ; CHECK-NEXT: sub v4.2d, v0.2d, v2.2d
804 ; CHECK-NEXT: mov x8, #9223372036854775807
805 ; CHECK-NEXT: cmlt v6.2d, v4.2d, #0
806 ; CHECK-NEXT: dup v7.2d, x8
807 ; CHECK-NEXT: sub v5.2d, v1.2d, v3.2d
808 ; CHECK-NEXT: mvn v16.16b, v6.16b
809 ; CHECK-NEXT: mov v17.16b, v7.16b
810 ; CHECK-NEXT: bsl v17.16b, v6.16b, v16.16b
811 ; CHECK-NEXT: cmlt v6.2d, v5.2d, #0
812 ; CHECK-NEXT: mvn v16.16b, v6.16b
813 ; CHECK-NEXT: bsl v7.16b, v6.16b, v16.16b
814 ; CHECK-NEXT: cmge v2.2d, v2.2d, #0
815 ; CHECK-NEXT: cmge v0.2d, v0.2d, #0
816 ; CHECK-NEXT: cmge v6.2d, v4.2d, #0
817 ; CHECK-NEXT: cmge v3.2d, v3.2d, #0
818 ; CHECK-NEXT: cmge v1.2d, v1.2d, #0
819 ; CHECK-NEXT: cmeq v2.2d, v0.2d, v2.2d
820 ; CHECK-NEXT: cmeq v0.2d, v0.2d, v6.2d
821 ; CHECK-NEXT: cmge v6.2d, v5.2d, #0
822 ; CHECK-NEXT: cmeq v3.2d, v1.2d, v3.2d
823 ; CHECK-NEXT: cmeq v1.2d, v1.2d, v6.2d
824 ; CHECK-NEXT: mvn v2.16b, v2.16b
825 ; CHECK-NEXT: mvn v3.16b, v3.16b
826 ; CHECK-NEXT: mvn v0.16b, v0.16b
827 ; CHECK-NEXT: mvn v1.16b, v1.16b
828 ; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
829 ; CHECK-NEXT: and v1.16b, v3.16b, v1.16b
830 ; CHECK-NEXT: bsl v0.16b, v17.16b, v4.16b
831 ; CHECK-NEXT: bsl v1.16b, v7.16b, v5.16b
832 ; CHECK-NEXT: ret
833 %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
834 ret <4 x i64> %z
835 }
837 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
838 ; CHECK-LABEL: v8i64:
839 ; CHECK: // %bb.0:
840 ; CHECK-NEXT: sub v16.2d, v0.2d, v4.2d
841 ; CHECK-NEXT: mov x8, #9223372036854775807
842 ; CHECK-NEXT: sub v17.2d, v1.2d, v5.2d
843 ; CHECK-NEXT: cmlt v20.2d, v16.2d, #0
844 ; CHECK-NEXT: dup v21.2d, x8
845 ; CHECK-NEXT: sub v18.2d, v2.2d, v6.2d
846 ; CHECK-NEXT: cmlt v22.2d, v17.2d, #0
847 ; CHECK-NEXT: mvn v24.16b, v20.16b
848 ; CHECK-NEXT: mov v25.16b, v21.16b
849 ; CHECK-NEXT: cmlt v23.2d, v18.2d, #0
850 ; CHECK-NEXT: bsl v25.16b, v20.16b, v24.16b
851 ; CHECK-NEXT: mvn v20.16b, v22.16b
852 ; CHECK-NEXT: mov v24.16b, v21.16b
853 ; CHECK-NEXT: sub v19.2d, v3.2d, v7.2d
854 ; CHECK-NEXT: bsl v24.16b, v22.16b, v20.16b
855 ; CHECK-NEXT: mvn v20.16b, v23.16b
856 ; CHECK-NEXT: mov v22.16b, v21.16b
857 ; CHECK-NEXT: bsl v22.16b, v23.16b, v20.16b
858 ; CHECK-NEXT: cmlt v20.2d, v19.2d, #0
859 ; CHECK-NEXT: mvn v23.16b, v20.16b
860 ; CHECK-NEXT: bsl v21.16b, v20.16b, v23.16b
861 ; CHECK-NEXT: cmge v4.2d, v4.2d, #0
862 ; CHECK-NEXT: cmge v0.2d, v0.2d, #0
863 ; CHECK-NEXT: cmge v20.2d, v16.2d, #0
864 ; CHECK-NEXT: cmge v5.2d, v5.2d, #0
865 ; CHECK-NEXT: cmge v1.2d, v1.2d, #0
866 ; CHECK-NEXT: cmeq v4.2d, v0.2d, v4.2d
867 ; CHECK-NEXT: cmeq v0.2d, v0.2d, v20.2d
868 ; CHECK-NEXT: cmge v20.2d, v17.2d, #0
869 ; CHECK-NEXT: cmge v6.2d, v6.2d, #0
870 ; CHECK-NEXT: cmge v2.2d, v2.2d, #0
871 ; CHECK-NEXT: cmeq v5.2d, v1.2d, v5.2d
872 ; CHECK-NEXT: cmeq v1.2d, v1.2d, v20.2d
873 ; CHECK-NEXT: cmge v20.2d, v18.2d, #0
874 ; CHECK-NEXT: mvn v4.16b, v4.16b
875 ; CHECK-NEXT: mvn v0.16b, v0.16b
876 ; CHECK-NEXT: cmge v7.2d, v7.2d, #0
877 ; CHECK-NEXT: cmge v3.2d, v3.2d, #0
878 ; CHECK-NEXT: cmeq v6.2d, v2.2d, v6.2d
879 ; CHECK-NEXT: cmeq v2.2d, v2.2d, v20.2d
880 ; CHECK-NEXT: cmge v20.2d, v19.2d, #0
881 ; CHECK-NEXT: and v0.16b, v4.16b, v0.16b
882 ; CHECK-NEXT: mvn v4.16b, v5.16b
883 ; CHECK-NEXT: mvn v1.16b, v1.16b
884 ; CHECK-NEXT: cmeq v7.2d, v3.2d, v7.2d
885 ; CHECK-NEXT: cmeq v3.2d, v3.2d, v20.2d
886 ; CHECK-NEXT: and v1.16b, v4.16b, v1.16b
887 ; CHECK-NEXT: mvn v4.16b, v6.16b
888 ; CHECK-NEXT: mvn v2.16b, v2.16b
889 ; CHECK-NEXT: and v2.16b, v4.16b, v2.16b
890 ; CHECK-NEXT: mvn v4.16b, v7.16b
891 ; CHECK-NEXT: mvn v3.16b, v3.16b
892 ; CHECK-NEXT: and v3.16b, v4.16b, v3.16b
893 ; CHECK-NEXT: bsl v0.16b, v25.16b, v16.16b
894 ; CHECK-NEXT: bsl v1.16b, v24.16b, v17.16b
895 ; CHECK-NEXT: bsl v2.16b, v22.16b, v18.16b
896 ; CHECK-NEXT: bsl v3.16b, v21.16b, v19.16b
897 ; CHECK-NEXT: ret
898 %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
899 ret <8 x i64> %z
900 }
902 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
903 ; CHECK-LABEL: v2i128:
904 ; CHECK: // %bb.0:
905 ; CHECK-NEXT: cmp x7, #0 // =0
906 ; CHECK-NEXT: cset w9, ge
907 ; CHECK-NEXT: csinc w9, w9, wzr, ne
908 ; CHECK-NEXT: cmp x3, #0 // =0
909 ; CHECK-NEXT: cset w10, ge
910 ; CHECK-NEXT: csinc w10, w10, wzr, ne
911 ; CHECK-NEXT: cmp w10, w9
912 ; CHECK-NEXT: cset w9, ne
913 ; CHECK-NEXT: subs x11, x2, x6
914 ; CHECK-NEXT: sbcs x12, x3, x7
915 ; CHECK-NEXT: cmp x12, #0 // =0
916 ; CHECK-NEXT: cset w13, ge
917 ; CHECK-NEXT: mov x8, #9223372036854775807
918 ; CHECK-NEXT: csinc w13, w13, wzr, ne
919 ; CHECK-NEXT: cinv x14, x8, ge
920 ; CHECK-NEXT: cmp w10, w13
921 ; CHECK-NEXT: cset w13, ne
922 ; CHECK-NEXT: asr x10, x12, #63
923 ; CHECK-NEXT: tst w9, w13
924 ; CHECK-NEXT: csel x3, x14, x12, ne
925 ; CHECK-NEXT: csel x2, x10, x11, ne
926 ; CHECK-NEXT: cmp x5, #0 // =0
927 ; CHECK-NEXT: cset w9, ge
928 ; CHECK-NEXT: csinc w9, w9, wzr, ne
929 ; CHECK-NEXT: cmp x1, #0 // =0
930 ; CHECK-NEXT: cset w10, ge
931 ; CHECK-NEXT: csinc w10, w10, wzr, ne
932 ; CHECK-NEXT: cmp w10, w9
933 ; CHECK-NEXT: cset w9, ne
934 ; CHECK-NEXT: subs x11, x0, x4
935 ; CHECK-NEXT: sbcs x12, x1, x5
936 ; CHECK-NEXT: cmp x12, #0 // =0
937 ; CHECK-NEXT: cset w13, ge
938 ; CHECK-NEXT: csinc w13, w13, wzr, ne
939 ; CHECK-NEXT: cinv x8, x8, ge
940 ; CHECK-NEXT: cmp w10, w13
941 ; CHECK-NEXT: cset w10, ne
942 ; CHECK-NEXT: tst w9, w10
943 ; CHECK-NEXT: asr x9, x12, #63
944 ; CHECK-NEXT: csel x9, x9, x11, ne
945 ; CHECK-NEXT: csel x1, x8, x12, ne
946 ; CHECK-NEXT: fmov d0, x9
947 ; CHECK-NEXT: mov v0.d[1], x1
948 ; CHECK-NEXT: fmov x0, d0
949 ; CHECK-NEXT: ret
950 %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
951 ret <2 x i128> %z
952 }