1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.uadd.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128>, <2 x i128>)
35 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
38 ; CHECK-NEXT: mvn v2.16b, v1.16b
39 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
40 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
42 %z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
46 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
49 ; CHECK-NEXT: mvn v4.16b, v2.16b
50 ; CHECK-NEXT: mvn v5.16b, v3.16b
51 ; CHECK-NEXT: umin v0.16b, v0.16b, v4.16b
52 ; CHECK-NEXT: umin v1.16b, v1.16b, v5.16b
53 ; CHECK-NEXT: add v0.16b, v0.16b, v2.16b
54 ; CHECK-NEXT: add v1.16b, v1.16b, v3.16b
56 %z = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
60 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
63 ; CHECK-NEXT: mvn v16.16b, v4.16b
64 ; CHECK-NEXT: umin v0.16b, v0.16b, v16.16b
65 ; CHECK-NEXT: mvn v16.16b, v5.16b
66 ; CHECK-NEXT: umin v1.16b, v1.16b, v16.16b
67 ; CHECK-NEXT: mvn v16.16b, v6.16b
68 ; CHECK-NEXT: umin v2.16b, v2.16b, v16.16b
69 ; CHECK-NEXT: mvn v16.16b, v7.16b
70 ; CHECK-NEXT: umin v3.16b, v3.16b, v16.16b
71 ; CHECK-NEXT: add v0.16b, v0.16b, v4.16b
72 ; CHECK-NEXT: add v1.16b, v1.16b, v5.16b
73 ; CHECK-NEXT: add v2.16b, v2.16b, v6.16b
74 ; CHECK-NEXT: add v3.16b, v3.16b, v7.16b
76 %z = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
80 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
83 ; CHECK-NEXT: mvn v2.16b, v1.16b
84 ; CHECK-NEXT: umin v0.8h, v0.8h, v2.8h
85 ; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
87 %z = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
91 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
92 ; CHECK-LABEL: v16i16:
94 ; CHECK-NEXT: mvn v4.16b, v2.16b
95 ; CHECK-NEXT: mvn v5.16b, v3.16b
96 ; CHECK-NEXT: umin v0.8h, v0.8h, v4.8h
97 ; CHECK-NEXT: umin v1.8h, v1.8h, v5.8h
98 ; CHECK-NEXT: add v0.8h, v0.8h, v2.8h
99 ; CHECK-NEXT: add v1.8h, v1.8h, v3.8h
101 %z = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
105 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
106 ; CHECK-LABEL: v32i16:
108 ; CHECK-NEXT: mvn v16.16b, v4.16b
109 ; CHECK-NEXT: umin v0.8h, v0.8h, v16.8h
110 ; CHECK-NEXT: mvn v16.16b, v5.16b
111 ; CHECK-NEXT: umin v1.8h, v1.8h, v16.8h
112 ; CHECK-NEXT: mvn v16.16b, v6.16b
113 ; CHECK-NEXT: umin v2.8h, v2.8h, v16.8h
114 ; CHECK-NEXT: mvn v16.16b, v7.16b
115 ; CHECK-NEXT: umin v3.8h, v3.8h, v16.8h
116 ; CHECK-NEXT: add v0.8h, v0.8h, v4.8h
117 ; CHECK-NEXT: add v1.8h, v1.8h, v5.8h
118 ; CHECK-NEXT: add v2.8h, v2.8h, v6.8h
119 ; CHECK-NEXT: add v3.8h, v3.8h, v7.8h
121 %z = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
125 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
128 ; CHECK-NEXT: ldr d0, [x1]
129 ; CHECK-NEXT: ldr d1, [x0]
130 ; CHECK-NEXT: mvn v2.8b, v0.8b
131 ; CHECK-NEXT: umin v1.8b, v1.8b, v2.8b
132 ; CHECK-NEXT: add v0.8b, v1.8b, v0.8b
133 ; CHECK-NEXT: str d0, [x2]
135 %x = load <8 x i8>, <8 x i8>* %px
136 %y = load <8 x i8>, <8 x i8>* %py
137 %z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
138 store <8 x i8> %z, <8 x i8>* %pz
142 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
145 ; CHECK-NEXT: ldrb w9, [x1]
146 ; CHECK-NEXT: ldrb w8, [x0]
147 ; CHECK-NEXT: ldrb w11, [x1, #1]
148 ; CHECK-NEXT: ldrb w10, [x0, #1]
149 ; CHECK-NEXT: fmov s1, w9
150 ; CHECK-NEXT: ldrb w9, [x1, #2]
151 ; CHECK-NEXT: fmov s0, w8
152 ; CHECK-NEXT: ldrb w8, [x0, #2]
153 ; CHECK-NEXT: mov v1.h[1], w11
154 ; CHECK-NEXT: ldrb w11, [x1, #3]
155 ; CHECK-NEXT: mov v0.h[1], w10
156 ; CHECK-NEXT: ldrb w10, [x0, #3]
157 ; CHECK-NEXT: mov v1.h[2], w9
158 ; CHECK-NEXT: mov v0.h[2], w8
159 ; CHECK-NEXT: mov v1.h[3], w11
160 ; CHECK-NEXT: mov v0.h[3], w10
161 ; CHECK-NEXT: shl v1.4h, v1.4h, #8
162 ; CHECK-NEXT: shl v0.4h, v0.4h, #8
163 ; CHECK-NEXT: mvn v2.8b, v1.8b
164 ; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h
165 ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
166 ; CHECK-NEXT: ushr v0.4h, v0.4h, #8
167 ; CHECK-NEXT: xtn v0.8b, v0.8h
168 ; CHECK-NEXT: str s0, [x2]
170 %x = load <4 x i8>, <4 x i8>* %px
171 %y = load <4 x i8>, <4 x i8>* %py
172 %z = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
173 store <4 x i8> %z, <4 x i8>* %pz
177 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
180 ; CHECK-NEXT: ldrb w9, [x1]
181 ; CHECK-NEXT: ldrb w8, [x0]
182 ; CHECK-NEXT: ldrb w11, [x1, #1]
183 ; CHECK-NEXT: ldrb w10, [x0, #1]
184 ; CHECK-NEXT: fmov s1, w9
185 ; CHECK-NEXT: fmov s0, w8
186 ; CHECK-NEXT: mov v1.s[1], w11
187 ; CHECK-NEXT: mov v0.s[1], w10
188 ; CHECK-NEXT: shl v1.2s, v1.2s, #24
189 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
190 ; CHECK-NEXT: mvn v2.8b, v1.8b
191 ; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
192 ; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
193 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
194 ; CHECK-NEXT: mov w8, v0.s[1]
195 ; CHECK-NEXT: fmov w9, s0
196 ; CHECK-NEXT: strb w8, [x2, #1]
197 ; CHECK-NEXT: strb w9, [x2]
199 %x = load <2 x i8>, <2 x i8>* %px
200 %y = load <2 x i8>, <2 x i8>* %py
201 %z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
202 store <2 x i8> %z, <2 x i8>* %pz
206 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
207 ; CHECK-LABEL: v4i16:
209 ; CHECK-NEXT: ldr d0, [x1]
210 ; CHECK-NEXT: ldr d1, [x0]
211 ; CHECK-NEXT: mvn v2.8b, v0.8b
212 ; CHECK-NEXT: umin v1.4h, v1.4h, v2.4h
213 ; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
214 ; CHECK-NEXT: str d0, [x2]
216 %x = load <4 x i16>, <4 x i16>* %px
217 %y = load <4 x i16>, <4 x i16>* %py
218 %z = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
219 store <4 x i16> %z, <4 x i16>* %pz
223 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
224 ; CHECK-LABEL: v2i16:
226 ; CHECK-NEXT: ldrh w9, [x1]
227 ; CHECK-NEXT: ldrh w8, [x0]
228 ; CHECK-NEXT: ldrh w11, [x1, #2]
229 ; CHECK-NEXT: ldrh w10, [x0, #2]
230 ; CHECK-NEXT: fmov s1, w9
231 ; CHECK-NEXT: fmov s0, w8
232 ; CHECK-NEXT: mov v1.s[1], w11
233 ; CHECK-NEXT: mov v0.s[1], w10
234 ; CHECK-NEXT: shl v1.2s, v1.2s, #16
235 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
236 ; CHECK-NEXT: mvn v2.8b, v1.8b
237 ; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
238 ; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
239 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
240 ; CHECK-NEXT: mov w8, v0.s[1]
241 ; CHECK-NEXT: fmov w9, s0
242 ; CHECK-NEXT: strh w8, [x2, #2]
243 ; CHECK-NEXT: strh w9, [x2]
245 %x = load <2 x i16>, <2 x i16>* %px
246 %y = load <2 x i16>, <2 x i16>* %py
247 %z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
248 store <2 x i16> %z, <2 x i16>* %pz
252 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
253 ; CHECK-LABEL: v12i8:
255 ; CHECK-NEXT: mvn v2.16b, v1.16b
256 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
257 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
259 %z = call <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
263 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
264 ; CHECK-LABEL: v12i16:
266 ; CHECK-NEXT: ldp q1, q0, [x1]
267 ; CHECK-NEXT: ldp q3, q2, [x0]
268 ; CHECK-NEXT: mvn v4.16b, v0.16b
269 ; CHECK-NEXT: mvn v5.16b, v1.16b
270 ; CHECK-NEXT: umin v2.8h, v2.8h, v4.8h
271 ; CHECK-NEXT: umin v3.8h, v3.8h, v5.8h
272 ; CHECK-NEXT: add v0.8h, v2.8h, v0.8h
273 ; CHECK-NEXT: add v1.8h, v3.8h, v1.8h
274 ; CHECK-NEXT: str q1, [x2]
275 ; CHECK-NEXT: str d0, [x2, #16]
277 %x = load <12 x i16>, <12 x i16>* %px
278 %y = load <12 x i16>, <12 x i16>* %py
279 %z = call <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
280 store <12 x i16> %z, <12 x i16>* %pz
284 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
287 ; CHECK-NEXT: ldr b0, [x1]
288 ; CHECK-NEXT: ldr b1, [x0]
289 ; CHECK-NEXT: mvn v2.8b, v0.8b
290 ; CHECK-NEXT: umin v1.8b, v1.8b, v2.8b
291 ; CHECK-NEXT: add v0.8b, v1.8b, v0.8b
292 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
294 %x = load <1 x i8>, <1 x i8>* %px
295 %y = load <1 x i8>, <1 x i8>* %py
296 %z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
297 store <1 x i8> %z, <1 x i8>* %pz
301 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
302 ; CHECK-LABEL: v1i16:
304 ; CHECK-NEXT: ldr h0, [x1]
305 ; CHECK-NEXT: ldr h1, [x0]
306 ; CHECK-NEXT: mvn v2.8b, v0.8b
307 ; CHECK-NEXT: umin v1.4h, v1.4h, v2.4h
308 ; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
309 ; CHECK-NEXT: str h0, [x2]
311 %x = load <1 x i16>, <1 x i16>* %px
312 %y = load <1 x i16>, <1 x i16>* %py
313 %z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
314 store <1 x i16> %z, <1 x i16>* %pz
318 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
319 ; CHECK-LABEL: v16i4:
321 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
322 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
323 ; CHECK-NEXT: mvn v2.16b, v1.16b
324 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
325 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
326 ; CHECK-NEXT: ushr v0.16b, v0.16b, #4
328 %z = call <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
332 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
333 ; CHECK-LABEL: v16i1:
335 ; CHECK-NEXT: shl v1.16b, v1.16b, #7
336 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
337 ; CHECK-NEXT: mvn v2.16b, v1.16b
338 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
339 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
340 ; CHECK-NEXT: ushr v0.16b, v0.16b, #7
342 %z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
346 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
347 ; CHECK-LABEL: v2i32:
349 ; CHECK-NEXT: mvn v2.8b, v1.8b
350 ; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
351 ; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
353 %z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
357 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
358 ; CHECK-LABEL: v4i32:
360 ; CHECK-NEXT: mvn v2.16b, v1.16b
361 ; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
362 ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
364 %z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
368 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
369 ; CHECK-LABEL: v8i32:
371 ; CHECK-NEXT: mvn v4.16b, v2.16b
372 ; CHECK-NEXT: mvn v5.16b, v3.16b
373 ; CHECK-NEXT: umin v0.4s, v0.4s, v4.4s
374 ; CHECK-NEXT: umin v1.4s, v1.4s, v5.4s
375 ; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
376 ; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
378 %z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
382 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
383 ; CHECK-LABEL: v16i32:
385 ; CHECK-NEXT: mvn v16.16b, v4.16b
386 ; CHECK-NEXT: umin v0.4s, v0.4s, v16.4s
387 ; CHECK-NEXT: mvn v16.16b, v5.16b
388 ; CHECK-NEXT: umin v1.4s, v1.4s, v16.4s
389 ; CHECK-NEXT: mvn v16.16b, v6.16b
390 ; CHECK-NEXT: umin v2.4s, v2.4s, v16.4s
391 ; CHECK-NEXT: mvn v16.16b, v7.16b
392 ; CHECK-NEXT: umin v3.4s, v3.4s, v16.4s
393 ; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
394 ; CHECK-NEXT: add v1.4s, v1.4s, v5.4s
395 ; CHECK-NEXT: add v2.4s, v2.4s, v6.4s
396 ; CHECK-NEXT: add v3.4s, v3.4s, v7.4s
398 %z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
402 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
403 ; CHECK-LABEL: v2i64:
405 ; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
406 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
407 ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
409 %z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
413 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
414 ; CHECK-LABEL: v4i64:
416 ; CHECK-NEXT: add v2.2d, v0.2d, v2.2d
417 ; CHECK-NEXT: add v3.2d, v1.2d, v3.2d
418 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v2.2d
419 ; CHECK-NEXT: cmhi v1.2d, v1.2d, v3.2d
420 ; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b
421 ; CHECK-NEXT: orr v1.16b, v3.16b, v1.16b
423 %z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
427 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
428 ; CHECK-LABEL: v8i64:
430 ; CHECK-NEXT: add v4.2d, v0.2d, v4.2d
431 ; CHECK-NEXT: add v5.2d, v1.2d, v5.2d
432 ; CHECK-NEXT: add v6.2d, v2.2d, v6.2d
433 ; CHECK-NEXT: add v7.2d, v3.2d, v7.2d
434 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v4.2d
435 ; CHECK-NEXT: cmhi v1.2d, v1.2d, v5.2d
436 ; CHECK-NEXT: cmhi v2.2d, v2.2d, v6.2d
437 ; CHECK-NEXT: cmhi v3.2d, v3.2d, v7.2d
438 ; CHECK-NEXT: orr v0.16b, v4.16b, v0.16b
439 ; CHECK-NEXT: orr v1.16b, v5.16b, v1.16b
440 ; CHECK-NEXT: orr v2.16b, v6.16b, v2.16b
441 ; CHECK-NEXT: orr v3.16b, v7.16b, v3.16b
443 %z = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
447 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
448 ; CHECK-LABEL: v2i128:
450 ; CHECK-NEXT: adds x8, x2, x6
451 ; CHECK-NEXT: adcs x9, x3, x7
452 ; CHECK-NEXT: cmp x8, x2
453 ; CHECK-NEXT: cset w10, lo
454 ; CHECK-NEXT: cmp x9, x3
455 ; CHECK-NEXT: cset w11, lo
456 ; CHECK-NEXT: csel w10, w10, w11, eq
457 ; CHECK-NEXT: cmp w10, #0 // =0
458 ; CHECK-NEXT: csinv x3, x9, xzr, eq
459 ; CHECK-NEXT: csinv x2, x8, xzr, eq
460 ; CHECK-NEXT: adds x8, x0, x4
461 ; CHECK-NEXT: adcs x9, x1, x5
462 ; CHECK-NEXT: cmp x8, x0
463 ; CHECK-NEXT: cset w10, lo
464 ; CHECK-NEXT: cmp x9, x1
465 ; CHECK-NEXT: cset w11, lo
466 ; CHECK-NEXT: csel w10, w10, w11, eq
467 ; CHECK-NEXT: cmp w10, #0 // =0
468 ; CHECK-NEXT: csinv x8, x8, xzr, eq
469 ; CHECK-NEXT: csinv x1, x9, xzr, eq
470 ; CHECK-NEXT: fmov d0, x8
471 ; CHECK-NEXT: mov v0.d[1], x1
472 ; CHECK-NEXT: fmov x0, d0
474 %z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)