| blob | 99b6ebe2f1da19d8cd363e9ff540f56eb3c794bc |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
4 declare i1 @llvm.experimental.vector.reduce.umax.v1i1(<1 x i1> %a)
5 declare i8 @llvm.experimental.vector.reduce.umax.v1i8(<1 x i8> %a)
6 declare i16 @llvm.experimental.vector.reduce.umax.v1i16(<1 x i16> %a)
7 declare i24 @llvm.experimental.vector.reduce.umax.v1i24(<1 x i24> %a)
8 declare i32 @llvm.experimental.vector.reduce.umax.v1i32(<1 x i32> %a)
9 declare i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> %a)
10 declare i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
12 declare i8 @llvm.experimental.vector.reduce.umax.v3i8(<3 x i8> %a)
13 declare i8 @llvm.experimental.vector.reduce.umax.v9i8(<9 x i8> %a)
14 declare i32 @llvm.experimental.vector.reduce.umax.v3i32(<3 x i32> %a)
15 declare i1 @llvm.experimental.vector.reduce.umax.v4i1(<4 x i1> %a)
16 declare i24 @llvm.experimental.vector.reduce.umax.v4i24(<4 x i24> %a)
17 declare i128 @llvm.experimental.vector.reduce.umax.v2i128(<2 x i128> %a)
18 declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %a)
20 define i1 @test_v1i1(<1 x i1> %a) nounwind {
21 ; CHECK-LABEL: test_v1i1:
22 ; CHECK: // %bb.0:
23 ; CHECK-NEXT: and w0, w0, #0x1
24 ; CHECK-NEXT: ret
25 %b = call i1 @llvm.experimental.vector.reduce.umax.v1i1(<1 x i1> %a)
26 ret i1 %b
27 }
29 define i8 @test_v1i8(<1 x i8> %a) nounwind {
30 ; CHECK-LABEL: test_v1i8:
31 ; CHECK: // %bb.0:
32 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
33 ; CHECK-NEXT: umov w0, v0.b[0]
34 ; CHECK-NEXT: ret
35 %b = call i8 @llvm.experimental.vector.reduce.umax.v1i8(<1 x i8> %a)
36 ret i8 %b
37 }
39 define i16 @test_v1i16(<1 x i16> %a) nounwind {
40 ; CHECK-LABEL: test_v1i16:
41 ; CHECK: // %bb.0:
42 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
43 ; CHECK-NEXT: umov w0, v0.h[0]
44 ; CHECK-NEXT: ret
45 %b = call i16 @llvm.experimental.vector.reduce.umax.v1i16(<1 x i16> %a)
46 ret i16 %b
47 }
49 define i24 @test_v1i24(<1 x i24> %a) nounwind {
50 ; CHECK-LABEL: test_v1i24:
51 ; CHECK: // %bb.0:
52 ; CHECK-NEXT: ret
53 %b = call i24 @llvm.experimental.vector.reduce.umax.v1i24(<1 x i24> %a)
54 ret i24 %b
55 }
57 define i32 @test_v1i32(<1 x i32> %a) nounwind {
58 ; CHECK-LABEL: test_v1i32:
59 ; CHECK: // %bb.0:
60 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
61 ; CHECK-NEXT: fmov w0, s0
62 ; CHECK-NEXT: ret
63 %b = call i32 @llvm.experimental.vector.reduce.umax.v1i32(<1 x i32> %a)
64 ret i32 %b
65 }
67 define i64 @test_v1i64(<1 x i64> %a) nounwind {
68 ; CHECK-LABEL: test_v1i64:
69 ; CHECK: // %bb.0:
70 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
71 ; CHECK-NEXT: fmov x0, d0
72 ; CHECK-NEXT: ret
73 %b = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> %a)
74 ret i64 %b
75 }
77 define i128 @test_v1i128(<1 x i128> %a) nounwind {
78 ; CHECK-LABEL: test_v1i128:
79 ; CHECK: // %bb.0:
80 ; CHECK-NEXT: ret
81 %b = call i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
82 ret i128 %b
83 }
85 define i8 @test_v3i8(<3 x i8> %a) nounwind {
86 ; CHECK-LABEL: test_v3i8:
87 ; CHECK: // %bb.0:
88 ; CHECK-NEXT: movi d0, #0000000000000000
89 ; CHECK-NEXT: mov v0.h[0], w0
90 ; CHECK-NEXT: mov v0.h[1], w1
91 ; CHECK-NEXT: mov v0.h[2], w2
92 ; CHECK-NEXT: bic v0.4h, #255, lsl #8
93 ; CHECK-NEXT: umaxv h0, v0.4h
94 ; CHECK-NEXT: fmov w0, s0
95 ; CHECK-NEXT: ret
96 %b = call i8 @llvm.experimental.vector.reduce.umax.v3i8(<3 x i8> %a)
97 ret i8 %b
98 }
100 define i8 @test_v9i8(<9 x i8> %a) nounwind {
101 ; CHECK-LABEL: test_v9i8:
102 ; CHECK: // %bb.0:
103 ; CHECK-NEXT: mov v0.b[9], wzr
104 ; CHECK-NEXT: mov v0.b[10], wzr
105 ; CHECK-NEXT: mov v0.b[11], wzr
106 ; CHECK-NEXT: mov v0.b[12], wzr
107 ; CHECK-NEXT: mov v0.b[13], wzr
108 ; CHECK-NEXT: mov v0.b[14], wzr
109 ; CHECK-NEXT: mov v0.b[15], wzr
110 ; CHECK-NEXT: umaxv b0, v0.16b
111 ; CHECK-NEXT: fmov w0, s0
112 ; CHECK-NEXT: ret
113 %b = call i8 @llvm.experimental.vector.reduce.umax.v9i8(<9 x i8> %a)
114 ret i8 %b
115 }
117 define i32 @test_v3i32(<3 x i32> %a) nounwind {
118 ; CHECK-LABEL: test_v3i32:
119 ; CHECK: // %bb.0:
120 ; CHECK-NEXT: mov v0.s[3], wzr
121 ; CHECK-NEXT: umaxv s0, v0.4s
122 ; CHECK-NEXT: fmov w0, s0
123 ; CHECK-NEXT: ret
124 %b = call i32 @llvm.experimental.vector.reduce.umax.v3i32(<3 x i32> %a)
125 ret i32 %b
126 }
128 define i1 @test_v4i1(<4 x i1> %a) nounwind {
129 ; CHECK-LABEL: test_v4i1:
130 ; CHECK: // %bb.0:
131 ; CHECK-NEXT: movi v1.4h, #1
132 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
133 ; CHECK-NEXT: umaxv h0, v0.4h
134 ; CHECK-NEXT: fmov w8, s0
135 ; CHECK-NEXT: and w0, w8, #0x1
136 ; CHECK-NEXT: ret
137 %b = call i1 @llvm.experimental.vector.reduce.umax.v4i1(<4 x i1> %a)
138 ret i1 %b
139 }
141 define i24 @test_v4i24(<4 x i24> %a) nounwind {
142 ; CHECK-LABEL: test_v4i24:
143 ; CHECK: // %bb.0:
144 ; CHECK-NEXT: bic v0.4s, #255, lsl #24
145 ; CHECK-NEXT: umaxv s0, v0.4s
146 ; CHECK-NEXT: fmov w0, s0
147 ; CHECK-NEXT: ret
148 %b = call i24 @llvm.experimental.vector.reduce.umax.v4i24(<4 x i24> %a)
149 ret i24 %b
150 }
152 define i128 @test_v2i128(<2 x i128> %a) nounwind {
153 ; CHECK-LABEL: test_v2i128:
154 ; CHECK: // %bb.0:
155 ; CHECK-NEXT: cmp x0, x2
156 ; CHECK-NEXT: csel x8, x0, x2, hi
157 ; CHECK-NEXT: cmp x1, x3
158 ; CHECK-NEXT: csel x9, x0, x2, hi
159 ; CHECK-NEXT: csel x0, x8, x9, eq
160 ; CHECK-NEXT: csel x1, x1, x3, hi
161 ; CHECK-NEXT: ret
162 %b = call i128 @llvm.experimental.vector.reduce.umax.v2i128(<2 x i128> %a)
163 ret i128 %b
164 }
166 define i32 @test_v16i32(<16 x i32> %a) nounwind {
167 ; CHECK-LABEL: test_v16i32:
168 ; CHECK: // %bb.0:
169 ; CHECK-NEXT: umax v1.4s, v1.4s, v3.4s
170 ; CHECK-NEXT: umax v0.4s, v0.4s, v2.4s
171 ; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
172 ; CHECK-NEXT: umaxv s0, v0.4s
173 ; CHECK-NEXT: fmov w0, s0
174 ; CHECK-NEXT: ret
175 %b = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %a)
176 ret i32 %b
177 }