| blob | 5ecce5ed4d964bf7988f365ccf4a8c939b5a50c7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; Make sure that a negative value for the compare-and-swap is zero extended
3 ; from i8/i16 to i32 since it will be compared for equality.
4 ; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s
5 ; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P7
7 @str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00"
8 @str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00"
9 @str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00"
11 define signext i32 @main() {
12 ; CHECK-LABEL: main:
13 ; CHECK: # %bb.0: # %L.entry
14 ; CHECK-NEXT: mflr 0
15 ; CHECK-NEXT: std 0, 16(1)
16 ; CHECK-NEXT: stdu 1, -48(1)
17 ; CHECK-NEXT: .cfi_def_cfa_offset 48
18 ; CHECK-NEXT: .cfi_offset lr, 16
19 ; CHECK-NEXT: li 3, -32477
20 ; CHECK-NEXT: li 6, 234
21 ; CHECK-NEXT: addi 5, 1, 46
22 ; CHECK-NEXT: sth 3, 46(1)
23 ; CHECK-NEXT: lis 3, 0
24 ; CHECK-NEXT: ori 4, 3, 33059
25 ; CHECK-NEXT: sync
26 ; CHECK-NEXT: .LBB0_1: # %L.entry
27 ; CHECK-NEXT: #
28 ; CHECK-NEXT: lharx 3, 0, 5
29 ; CHECK-NEXT: cmpw 4, 3
30 ; CHECK-NEXT: bne 0, .LBB0_3
31 ; CHECK-NEXT: # %bb.2: # %L.entry
32 ; CHECK-NEXT: #
33 ; CHECK-NEXT: sthcx. 6, 0, 5
34 ; CHECK-NEXT: bne 0, .LBB0_1
35 ; CHECK-NEXT: b .LBB0_4
36 ; CHECK-NEXT: .LBB0_3: # %L.entry
37 ; CHECK-NEXT: sthcx. 3, 0, 5
38 ; CHECK-NEXT: .LBB0_4: # %L.entry
39 ; CHECK-NEXT: cmplwi 3, 33059
40 ; CHECK-NEXT: lwsync
41 ; CHECK-NEXT: bne 0, .LBB0_7
42 ; CHECK-NEXT: # %bb.5: # %L.B0000
43 ; CHECK-NEXT: lhz 3, 46(1)
44 ; CHECK-NEXT: cmplwi 3, 234
45 ; CHECK-NEXT: bne 0, .LBB0_8
46 ; CHECK-NEXT: # %bb.6: # %L.B0001
47 ; CHECK-NEXT: addis 3, 2, .Lstr.2@toc@ha
48 ; CHECK-NEXT: addi 3, 3, .Lstr.2@toc@l
49 ; CHECK-NEXT: bl puts
50 ; CHECK-NEXT: nop
51 ; CHECK-NEXT: li 3, 0
52 ; CHECK-NEXT: b .LBB0_10
53 ; CHECK-NEXT: .LBB0_7: # %L.B0003
54 ; CHECK-NEXT: addis 3, 2, .Lstr@toc@ha
55 ; CHECK-NEXT: addi 3, 3, .Lstr@toc@l
56 ; CHECK-NEXT: b .LBB0_9
57 ; CHECK-NEXT: .LBB0_8: # %L.B0005
58 ; CHECK-NEXT: addis 3, 2, .Lstr.1@toc@ha
59 ; CHECK-NEXT: addi 3, 3, .Lstr.1@toc@l
60 ; CHECK-NEXT: .LBB0_9: # %L.B0003
61 ; CHECK-NEXT: bl puts
62 ; CHECK-NEXT: nop
63 ; CHECK-NEXT: li 3, 1
64 ; CHECK-NEXT: .LBB0_10: # %L.B0003
65 ; CHECK-NEXT: addi 1, 1, 48
66 ; CHECK-NEXT: ld 0, 16(1)
67 ; CHECK-NEXT: mtlr 0
68 ; CHECK-NEXT: blr
69 ;
70 ; CHECK-P7-LABEL: main:
71 ; CHECK-P7: # %bb.0: # %L.entry
72 ; CHECK-P7-NEXT: mflr 0
73 ; CHECK-P7-NEXT: std 0, 16(1)
74 ; CHECK-P7-NEXT: stdu 1, -48(1)
75 ; CHECK-P7-NEXT: .cfi_def_cfa_offset 48
76 ; CHECK-P7-NEXT: .cfi_offset lr, 16
77 ; CHECK-P7-NEXT: li 3, -32477
78 ; CHECK-P7-NEXT: lis 5, 0
79 ; CHECK-P7-NEXT: addi 4, 1, 46
80 ; CHECK-P7-NEXT: li 7, 0
81 ; CHECK-P7-NEXT: sth 3, 46(1)
82 ; CHECK-P7-NEXT: li 6, 234
83 ; CHECK-P7-NEXT: ori 5, 5, 33059
84 ; CHECK-P7-NEXT: rlwinm 3, 4, 3, 27, 27
85 ; CHECK-P7-NEXT: ori 7, 7, 65535
86 ; CHECK-P7-NEXT: sync
87 ; CHECK-P7-NEXT: slw 6, 6, 3
88 ; CHECK-P7-NEXT: slw 8, 5, 3
89 ; CHECK-P7-NEXT: slw 5, 7, 3
90 ; CHECK-P7-NEXT: rldicr 4, 4, 0, 61
91 ; CHECK-P7-NEXT: and 7, 6, 5
92 ; CHECK-P7-NEXT: and 8, 8, 5
93 ; CHECK-P7-NEXT: .LBB0_1: # %L.entry
94 ; CHECK-P7-NEXT: #
95 ; CHECK-P7-NEXT: lwarx 9, 0, 4
96 ; CHECK-P7-NEXT: and 6, 9, 5
97 ; CHECK-P7-NEXT: cmpw 6, 8
98 ; CHECK-P7-NEXT: bne 0, .LBB0_3
99 ; CHECK-P7-NEXT: # %bb.2: # %L.entry
100 ; CHECK-P7-NEXT: #
101 ; CHECK-P7-NEXT: andc 9, 9, 5
102 ; CHECK-P7-NEXT: or 9, 9, 7
103 ; CHECK-P7-NEXT: stwcx. 9, 0, 4
104 ; CHECK-P7-NEXT: bne 0, .LBB0_1
105 ; CHECK-P7-NEXT: b .LBB0_4
106 ; CHECK-P7-NEXT: .LBB0_3: # %L.entry
107 ; CHECK-P7-NEXT: stwcx. 9, 0, 4
108 ; CHECK-P7-NEXT: .LBB0_4: # %L.entry
109 ; CHECK-P7-NEXT: srw 3, 6, 3
110 ; CHECK-P7-NEXT: lwsync
111 ; CHECK-P7-NEXT: cmplwi 3, 33059
112 ; CHECK-P7-NEXT: bne 0, .LBB0_7
113 ; CHECK-P7-NEXT: # %bb.5: # %L.B0000
114 ; CHECK-P7-NEXT: lhz 3, 46(1)
115 ; CHECK-P7-NEXT: cmplwi 3, 234
116 ; CHECK-P7-NEXT: bne 0, .LBB0_8
117 ; CHECK-P7-NEXT: # %bb.6: # %L.B0001
118 ; CHECK-P7-NEXT: addis 3, 2, .Lstr.2@toc@ha
119 ; CHECK-P7-NEXT: addi 3, 3, .Lstr.2@toc@l
120 ; CHECK-P7-NEXT: bl puts
121 ; CHECK-P7-NEXT: nop
122 ; CHECK-P7-NEXT: li 3, 0
123 ; CHECK-P7-NEXT: b .LBB0_10
124 ; CHECK-P7-NEXT: .LBB0_7: # %L.B0003
125 ; CHECK-P7-NEXT: addis 3, 2, .Lstr@toc@ha
126 ; CHECK-P7-NEXT: addi 3, 3, .Lstr@toc@l
127 ; CHECK-P7-NEXT: b .LBB0_9
128 ; CHECK-P7-NEXT: .LBB0_8: # %L.B0005
129 ; CHECK-P7-NEXT: addis 3, 2, .Lstr.1@toc@ha
130 ; CHECK-P7-NEXT: addi 3, 3, .Lstr.1@toc@l
131 ; CHECK-P7-NEXT: .LBB0_9: # %L.B0003
132 ; CHECK-P7-NEXT: bl puts
133 ; CHECK-P7-NEXT: nop
134 ; CHECK-P7-NEXT: li 3, 1
135 ; CHECK-P7-NEXT: .LBB0_10: # %L.B0003
136 ; CHECK-P7-NEXT: addi 1, 1, 48
137 ; CHECK-P7-NEXT: ld 0, 16(1)
138 ; CHECK-P7-NEXT: mtlr 0
139 ; CHECK-P7-NEXT: blr
140 L.entry:
141 %value.addr = alloca i16, align 2
142 store i16 -32477, i16* %value.addr, align 2
143 %0 = cmpxchg i16* %value.addr, i16 -32477, i16 234 seq_cst seq_cst
144 %1 = extractvalue { i16, i1 } %0, 1
145 br i1 %1, label %L.B0000, label %L.B0003
147 L.B0003: ; preds = %L.entry
148 %puts = call i32 @puts(i8* getelementptr inbounds ([46 x i8], [46 x i8]* @str, i64 0, i64 0))
149 ret i32 1
151 L.B0000: ; preds = %L.entry
152 %2 = load i16, i16* %value.addr, align 2
153 %3 = icmp eq i16 %2, 234
154 br i1 %3, label %L.B0001, label %L.B0005
156 L.B0005: ; preds = %L.B0000
157 %puts1 = call i32 @puts(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @str.1, i64 0, i64 0))
158 ret i32 1
160 L.B0001: ; preds = %L.B0000
161 %puts2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @str.2, i64 0, i64 0))
162 ret i32 0
163 }
165 ; Function Attrs: nounwind
166 declare i32 @puts(i8* nocapture readonly) #0