| blob | f3431f862b1450dc7546b14e7056d2b765927730 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: xxswapd vs0, v2
16 ; CHECK-P8-NEXT: xscvdpuxws f1, v2
17 ; CHECK-P8-NEXT: xscvdpuxws f0, f0
18 ; CHECK-P8-NEXT: mfvsrwz r3, f1
19 ; CHECK-P8-NEXT: mfvsrwz r4, f0
20 ; CHECK-P8-NEXT: mtvsrd f0, r3
21 ; CHECK-P8-NEXT: mtvsrd f1, r4
22 ; CHECK-P8-NEXT: xxswapd v2, vs0
23 ; CHECK-P8-NEXT: xxswapd v3, vs1
24 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
25 ; CHECK-P8-NEXT: xxswapd vs0, v2
26 ; CHECK-P8-NEXT: mfvsrd r3, f0
27 ; CHECK-P8-NEXT: blr
28 ;
29 ; CHECK-P9-LABEL: test2elt:
30 ; CHECK-P9: # %bb.0: # %entry
31 ; CHECK-P9-NEXT: xscvdpuxws f0, v2
32 ; CHECK-P9-NEXT: mfvsrwz r3, f0
33 ; CHECK-P9-NEXT: xxswapd vs0, v2
34 ; CHECK-P9-NEXT: mtvsrws v3, r3
35 ; CHECK-P9-NEXT: xscvdpuxws f0, f0
36 ; CHECK-P9-NEXT: mfvsrwz r3, f0
37 ; CHECK-P9-NEXT: mtvsrws v2, r3
38 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
39 ; CHECK-P9-NEXT: mfvsrld r3, v2
40 ; CHECK-P9-NEXT: blr
41 ;
42 ; CHECK-BE-LABEL: test2elt:
43 ; CHECK-BE: # %bb.0: # %entry
44 ; CHECK-BE-NEXT: xscvdpuxws f0, v2
45 ; CHECK-BE-NEXT: mfvsrwz r3, f0
46 ; CHECK-BE-NEXT: xxswapd vs0, v2
47 ; CHECK-BE-NEXT: mtvsrws v3, r3
48 ; CHECK-BE-NEXT: xscvdpuxws f0, f0
49 ; CHECK-BE-NEXT: mfvsrwz r3, f0
50 ; CHECK-BE-NEXT: mtvsrws v2, r3
51 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
52 ; CHECK-BE-NEXT: mfvsrd r3, v2
53 ; CHECK-BE-NEXT: blr
54 entry:
55 %0 = fptoui <2 x double> %a to <2 x i32>
56 %1 = bitcast <2 x i32> %0 to i64
57 ret i64 %1
58 }
60 define <4 x i32> @test4elt(<4 x double>* nocapture readonly) local_unnamed_addr #1 {
61 ; CHECK-P8-LABEL: test4elt:
62 ; CHECK-P8: # %bb.0: # %entry
63 ; CHECK-P8-NEXT: li r4, 16
64 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
65 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
66 ; CHECK-P8-NEXT: xxswapd vs1, vs1
67 ; CHECK-P8-NEXT: xxswapd vs0, vs0
68 ; CHECK-P8-NEXT: xxmrgld vs2, vs0, vs1
69 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs1
70 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs2
71 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs0
72 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
73 ; CHECK-P8-NEXT: blr
74 ;
75 ; CHECK-P9-LABEL: test4elt:
76 ; CHECK-P9: # %bb.0: # %entry
77 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
78 ; CHECK-P9-NEXT: lxv vs1, 16(r3)
79 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
80 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
81 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs2
82 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs0
83 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
84 ; CHECK-P9-NEXT: blr
85 ;
86 ; CHECK-BE-LABEL: test4elt:
87 ; CHECK-BE: # %bb.0: # %entry
88 ; CHECK-BE-NEXT: lxv vs0, 16(r3)
89 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
90 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
91 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
92 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs2
93 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs0
94 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
95 ; CHECK-BE-NEXT: blr
96 entry:
97 %a = load <4 x double>, <4 x double>* %0, align 32
98 %1 = fptoui <4 x double> %a to <4 x i32>
99 ret <4 x i32> %1
100 }
102 define void @test8elt(<8 x i32>* noalias nocapture sret %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #2 {
103 ; CHECK-P8-LABEL: test8elt:
104 ; CHECK-P8: # %bb.0: # %entry
105 ; CHECK-P8-NEXT: li r5, 32
106 ; CHECK-P8-NEXT: li r6, 48
107 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
108 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
109 ; CHECK-P8-NEXT: li r5, 16
110 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
111 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
112 ; CHECK-P8-NEXT: xxswapd vs3, vs3
113 ; CHECK-P8-NEXT: xxswapd vs0, vs0
114 ; CHECK-P8-NEXT: xxswapd vs1, vs1
115 ; CHECK-P8-NEXT: xxswapd vs2, vs2
116 ; CHECK-P8-NEXT: xxmrgld vs4, vs1, vs0
117 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
118 ; CHECK-P8-NEXT: xxmrgld vs1, vs2, vs3
119 ; CHECK-P8-NEXT: xxmrghd vs2, vs2, vs3
120 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs4
121 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs0
122 ; CHECK-P8-NEXT: xvcvdpuxws v4, vs1
123 ; CHECK-P8-NEXT: xvcvdpuxws v5, vs2
124 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
125 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
126 ; CHECK-P8-NEXT: stvx v2, r3, r5
127 ; CHECK-P8-NEXT: stvx v3, 0, r3
128 ; CHECK-P8-NEXT: blr
129 ;
130 ; CHECK-P9-LABEL: test8elt:
131 ; CHECK-P9: # %bb.0: # %entry
132 ; CHECK-P9-NEXT: lxv vs2, 0(r4)
133 ; CHECK-P9-NEXT: lxv vs3, 16(r4)
134 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
135 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
136 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
137 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
138 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs4
139 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
140 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
141 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
142 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs0
143 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
144 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
145 ; CHECK-P9-NEXT: stxv v2, 0(r3)
146 ; CHECK-P9-NEXT: vmrgew v3, v4, v3
147 ; CHECK-P9-NEXT: stxv v3, 16(r3)
148 ; CHECK-P9-NEXT: blr
149 ;
150 ; CHECK-BE-LABEL: test8elt:
151 ; CHECK-BE: # %bb.0: # %entry
152 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
153 ; CHECK-BE-NEXT: lxv vs3, 0(r4)
154 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
155 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
156 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
157 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
158 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs4
159 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
160 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
161 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
162 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs0
163 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
164 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
165 ; CHECK-BE-NEXT: stxv v2, 0(r3)
166 ; CHECK-BE-NEXT: vmrgew v3, v4, v3
167 ; CHECK-BE-NEXT: stxv v3, 16(r3)
168 ; CHECK-BE-NEXT: blr
169 entry:
170 %a = load <8 x double>, <8 x double>* %0, align 64
171 %1 = fptoui <8 x double> %a to <8 x i32>
172 store <8 x i32> %1, <8 x i32>* %agg.result, align 32
173 ret void
174 }
176 define void @test16elt(<16 x i32>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 {
177 ; CHECK-P8-LABEL: test16elt:
178 ; CHECK-P8: # %bb.0: # %entry
179 ; CHECK-P8-NEXT: li r5, 32
180 ; CHECK-P8-NEXT: li r6, 48
181 ; CHECK-P8-NEXT: li r8, 64
182 ; CHECK-P8-NEXT: li r7, 16
183 ; CHECK-P8-NEXT: li r9, 80
184 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
185 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
186 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
187 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
188 ; CHECK-P8-NEXT: li r8, 96
189 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
190 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r8
191 ; CHECK-P8-NEXT: li r8, 112
192 ; CHECK-P8-NEXT: lxvd2x vs4, r4, r9
193 ; CHECK-P8-NEXT: xxswapd vs0, vs0
194 ; CHECK-P8-NEXT: xxswapd vs1, vs1
195 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r8
196 ; CHECK-P8-NEXT: xxswapd vs2, vs2
197 ; CHECK-P8-NEXT: xxswapd vs3, vs3
198 ; CHECK-P8-NEXT: xxswapd vs4, vs4
199 ; CHECK-P8-NEXT: xxswapd vs5, vs5
200 ; CHECK-P8-NEXT: xxmrgld vs8, vs1, vs0
201 ; CHECK-P8-NEXT: xxswapd vs6, vs6
202 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
203 ; CHECK-P8-NEXT: xxswapd vs1, vs7
204 ; CHECK-P8-NEXT: xxmrgld vs7, vs4, vs3
205 ; CHECK-P8-NEXT: xxmrghd vs3, vs4, vs3
206 ; CHECK-P8-NEXT: xxmrgld vs4, vs6, vs5
207 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs8
208 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs0
209 ; CHECK-P8-NEXT: xxmrghd vs0, vs6, vs5
210 ; CHECK-P8-NEXT: xxmrgld vs5, vs2, vs1
211 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs1
212 ; CHECK-P8-NEXT: xvcvdpuxws v4, vs7
213 ; CHECK-P8-NEXT: xvcvdpuxws v5, vs3
214 ; CHECK-P8-NEXT: xvcvdpuxws v0, vs4
215 ; CHECK-P8-NEXT: xvcvdpuxws v1, vs0
216 ; CHECK-P8-NEXT: xvcvdpuxws v6, vs5
217 ; CHECK-P8-NEXT: xvcvdpuxws v7, vs1
218 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
219 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
220 ; CHECK-P8-NEXT: vmrgew v4, v1, v0
221 ; CHECK-P8-NEXT: vmrgew v5, v7, v6
222 ; CHECK-P8-NEXT: stvx v2, r3, r7
223 ; CHECK-P8-NEXT: stvx v3, r3, r5
224 ; CHECK-P8-NEXT: stvx v4, r3, r6
225 ; CHECK-P8-NEXT: stvx v5, 0, r3
226 ; CHECK-P8-NEXT: blr
227 ;
228 ; CHECK-P9-LABEL: test16elt:
229 ; CHECK-P9: # %bb.0: # %entry
230 ; CHECK-P9-NEXT: lxv vs6, 0(r4)
231 ; CHECK-P9-NEXT: lxv vs7, 16(r4)
232 ; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
233 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
234 ; CHECK-P9-NEXT: lxv vs4, 32(r4)
235 ; CHECK-P9-NEXT: lxv vs5, 48(r4)
236 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
237 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
238 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs8
239 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs6
240 ; CHECK-P9-NEXT: lxv vs2, 64(r4)
241 ; CHECK-P9-NEXT: lxv vs3, 80(r4)
242 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs7
243 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
244 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs4
245 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
246 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
247 ; CHECK-P9-NEXT: lxv vs0, 96(r4)
248 ; CHECK-P9-NEXT: lxv vs1, 112(r4)
249 ; CHECK-P9-NEXT: stxv v2, 0(r3)
250 ; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
251 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
252 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
253 ; CHECK-P9-NEXT: xvcvdpuxws v0, vs0
254 ; CHECK-P9-NEXT: vmrgew v3, v3, v4
255 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs4
256 ; CHECK-P9-NEXT: stxv v3, 16(r3)
257 ; CHECK-P9-NEXT: vmrgew v4, v5, v4
258 ; CHECK-P9-NEXT: stxv v4, 32(r3)
259 ; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
260 ; CHECK-P9-NEXT: vmrgew v5, v0, v5
261 ; CHECK-P9-NEXT: stxv v5, 48(r3)
262 ; CHECK-P9-NEXT: blr
263 ;
264 ; CHECK-BE-LABEL: test16elt:
265 ; CHECK-BE: # %bb.0: # %entry
266 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
267 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
268 ; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
269 ; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
270 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
271 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
272 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
273 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
274 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs8
275 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs6
276 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
277 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
278 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs7
279 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
280 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs4
281 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
282 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
283 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
284 ; CHECK-BE-NEXT: lxv vs1, 96(r4)
285 ; CHECK-BE-NEXT: stxv v2, 0(r3)
286 ; CHECK-BE-NEXT: xvcvdpuxws v5, vs2
287 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
288 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
289 ; CHECK-BE-NEXT: xvcvdpuxws v0, vs0
290 ; CHECK-BE-NEXT: vmrgew v3, v3, v4
291 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs4
292 ; CHECK-BE-NEXT: stxv v3, 16(r3)
293 ; CHECK-BE-NEXT: vmrgew v4, v5, v4
294 ; CHECK-BE-NEXT: stxv v4, 32(r3)
295 ; CHECK-BE-NEXT: xvcvdpuxws v5, vs2
296 ; CHECK-BE-NEXT: vmrgew v5, v0, v5
297 ; CHECK-BE-NEXT: stxv v5, 48(r3)
298 ; CHECK-BE-NEXT: blr
299 entry:
300 %a = load <16 x double>, <16 x double>* %0, align 128
301 %1 = fptoui <16 x double> %a to <16 x i32>
302 store <16 x i32> %1, <16 x i32>* %agg.result, align 64
303 ret void
304 }
306 define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
307 ; CHECK-P8-LABEL: test2elt_signed:
308 ; CHECK-P8: # %bb.0: # %entry
309 ; CHECK-P8-NEXT: xxswapd vs0, v2
310 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
311 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
312 ; CHECK-P8-NEXT: mfvsrwz r3, f1
313 ; CHECK-P8-NEXT: mfvsrwz r4, f0
314 ; CHECK-P8-NEXT: mtvsrd f0, r3
315 ; CHECK-P8-NEXT: mtvsrd f1, r4
316 ; CHECK-P8-NEXT: xxswapd v2, vs0
317 ; CHECK-P8-NEXT: xxswapd v3, vs1
318 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
319 ; CHECK-P8-NEXT: xxswapd vs0, v2
320 ; CHECK-P8-NEXT: mfvsrd r3, f0
321 ; CHECK-P8-NEXT: blr
322 ;
323 ; CHECK-P9-LABEL: test2elt_signed:
324 ; CHECK-P9: # %bb.0: # %entry
325 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
326 ; CHECK-P9-NEXT: mfvsrwz r3, f0
327 ; CHECK-P9-NEXT: xxswapd vs0, v2
328 ; CHECK-P9-NEXT: mtvsrws v3, r3
329 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
330 ; CHECK-P9-NEXT: mfvsrwz r3, f0
331 ; CHECK-P9-NEXT: mtvsrws v2, r3
332 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
333 ; CHECK-P9-NEXT: mfvsrld r3, v2
334 ; CHECK-P9-NEXT: blr
335 ;
336 ; CHECK-BE-LABEL: test2elt_signed:
337 ; CHECK-BE: # %bb.0: # %entry
338 ; CHECK-BE-NEXT: xscvdpsxws f0, v2
339 ; CHECK-BE-NEXT: mfvsrwz r3, f0
340 ; CHECK-BE-NEXT: xxswapd vs0, v2
341 ; CHECK-BE-NEXT: mtvsrws v3, r3
342 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
343 ; CHECK-BE-NEXT: mfvsrwz r3, f0
344 ; CHECK-BE-NEXT: mtvsrws v2, r3
345 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
346 ; CHECK-BE-NEXT: mfvsrd r3, v2
347 ; CHECK-BE-NEXT: blr
348 entry:
349 %0 = fptosi <2 x double> %a to <2 x i32>
350 %1 = bitcast <2 x i32> %0 to i64
351 ret i64 %1
352 }
354 define <4 x i32> @test4elt_signed(<4 x double>* nocapture readonly) local_unnamed_addr #1 {
355 ; CHECK-P8-LABEL: test4elt_signed:
356 ; CHECK-P8: # %bb.0: # %entry
357 ; CHECK-P8-NEXT: li r4, 16
358 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
359 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
360 ; CHECK-P8-NEXT: xxswapd vs1, vs1
361 ; CHECK-P8-NEXT: xxswapd vs0, vs0
362 ; CHECK-P8-NEXT: xxmrgld vs2, vs0, vs1
363 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs1
364 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs2
365 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs0
366 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
367 ; CHECK-P8-NEXT: blr
368 ;
369 ; CHECK-P9-LABEL: test4elt_signed:
370 ; CHECK-P9: # %bb.0: # %entry
371 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
372 ; CHECK-P9-NEXT: lxv vs1, 16(r3)
373 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
374 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
375 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs2
376 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs0
377 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
378 ; CHECK-P9-NEXT: blr
379 ;
380 ; CHECK-BE-LABEL: test4elt_signed:
381 ; CHECK-BE: # %bb.0: # %entry
382 ; CHECK-BE-NEXT: lxv vs0, 16(r3)
383 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
384 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
385 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
386 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs2
387 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs0
388 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
389 ; CHECK-BE-NEXT: blr
390 entry:
391 %a = load <4 x double>, <4 x double>* %0, align 32
392 %1 = fptosi <4 x double> %a to <4 x i32>
393 ret <4 x i32> %1
394 }
396 define void @test8elt_signed(<8 x i32>* noalias nocapture sret %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #2 {
397 ; CHECK-P8-LABEL: test8elt_signed:
398 ; CHECK-P8: # %bb.0: # %entry
399 ; CHECK-P8-NEXT: li r5, 32
400 ; CHECK-P8-NEXT: li r6, 48
401 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
402 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
403 ; CHECK-P8-NEXT: li r5, 16
404 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
405 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r5
406 ; CHECK-P8-NEXT: xxswapd vs3, vs3
407 ; CHECK-P8-NEXT: xxswapd vs0, vs0
408 ; CHECK-P8-NEXT: xxswapd vs1, vs1
409 ; CHECK-P8-NEXT: xxswapd vs2, vs2
410 ; CHECK-P8-NEXT: xxmrgld vs4, vs1, vs0
411 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
412 ; CHECK-P8-NEXT: xxmrgld vs1, vs2, vs3
413 ; CHECK-P8-NEXT: xxmrghd vs2, vs2, vs3
414 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs4
415 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs0
416 ; CHECK-P8-NEXT: xvcvdpsxws v4, vs1
417 ; CHECK-P8-NEXT: xvcvdpsxws v5, vs2
418 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
419 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
420 ; CHECK-P8-NEXT: stvx v2, r3, r5
421 ; CHECK-P8-NEXT: stvx v3, 0, r3
422 ; CHECK-P8-NEXT: blr
423 ;
424 ; CHECK-P9-LABEL: test8elt_signed:
425 ; CHECK-P9: # %bb.0: # %entry
426 ; CHECK-P9-NEXT: lxv vs2, 0(r4)
427 ; CHECK-P9-NEXT: lxv vs3, 16(r4)
428 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
429 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
430 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
431 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
432 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs4
433 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
434 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
435 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
436 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs0
437 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
438 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
439 ; CHECK-P9-NEXT: stxv v2, 0(r3)
440 ; CHECK-P9-NEXT: vmrgew v3, v4, v3
441 ; CHECK-P9-NEXT: stxv v3, 16(r3)
442 ; CHECK-P9-NEXT: blr
443 ;
444 ; CHECK-BE-LABEL: test8elt_signed:
445 ; CHECK-BE: # %bb.0: # %entry
446 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
447 ; CHECK-BE-NEXT: lxv vs3, 0(r4)
448 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
449 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
450 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
451 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
452 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs4
453 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
454 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
455 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
456 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs0
457 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
458 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
459 ; CHECK-BE-NEXT: stxv v2, 0(r3)
460 ; CHECK-BE-NEXT: vmrgew v3, v4, v3
461 ; CHECK-BE-NEXT: stxv v3, 16(r3)
462 ; CHECK-BE-NEXT: blr
463 entry:
464 %a = load <8 x double>, <8 x double>* %0, align 64
465 %1 = fptosi <8 x double> %a to <8 x i32>
466 store <8 x i32> %1, <8 x i32>* %agg.result, align 32
467 ret void
468 }
470 define void @test16elt_signed(<16 x i32>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 {
471 ; CHECK-P8-LABEL: test16elt_signed:
472 ; CHECK-P8: # %bb.0: # %entry
473 ; CHECK-P8-NEXT: li r5, 32
474 ; CHECK-P8-NEXT: li r6, 48
475 ; CHECK-P8-NEXT: li r8, 64
476 ; CHECK-P8-NEXT: li r7, 16
477 ; CHECK-P8-NEXT: li r9, 80
478 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
479 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
480 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
481 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r8
482 ; CHECK-P8-NEXT: li r8, 96
483 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r7
484 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r8
485 ; CHECK-P8-NEXT: li r8, 112
486 ; CHECK-P8-NEXT: lxvd2x vs4, r4, r9
487 ; CHECK-P8-NEXT: xxswapd vs0, vs0
488 ; CHECK-P8-NEXT: xxswapd vs1, vs1
489 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r8
490 ; CHECK-P8-NEXT: xxswapd vs2, vs2
491 ; CHECK-P8-NEXT: xxswapd vs3, vs3
492 ; CHECK-P8-NEXT: xxswapd vs4, vs4
493 ; CHECK-P8-NEXT: xxswapd vs5, vs5
494 ; CHECK-P8-NEXT: xxmrgld vs8, vs1, vs0
495 ; CHECK-P8-NEXT: xxswapd vs6, vs6
496 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
497 ; CHECK-P8-NEXT: xxswapd vs1, vs7
498 ; CHECK-P8-NEXT: xxmrgld vs7, vs4, vs3
499 ; CHECK-P8-NEXT: xxmrghd vs3, vs4, vs3
500 ; CHECK-P8-NEXT: xxmrgld vs4, vs6, vs5
501 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs8
502 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs0
503 ; CHECK-P8-NEXT: xxmrghd vs0, vs6, vs5
504 ; CHECK-P8-NEXT: xxmrgld vs5, vs2, vs1
505 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs1
506 ; CHECK-P8-NEXT: xvcvdpsxws v4, vs7
507 ; CHECK-P8-NEXT: xvcvdpsxws v5, vs3
508 ; CHECK-P8-NEXT: xvcvdpsxws v0, vs4
509 ; CHECK-P8-NEXT: xvcvdpsxws v1, vs0
510 ; CHECK-P8-NEXT: xvcvdpsxws v6, vs5
511 ; CHECK-P8-NEXT: xvcvdpsxws v7, vs1
512 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
513 ; CHECK-P8-NEXT: vmrgew v3, v5, v4
514 ; CHECK-P8-NEXT: vmrgew v4, v1, v0
515 ; CHECK-P8-NEXT: vmrgew v5, v7, v6
516 ; CHECK-P8-NEXT: stvx v2, r3, r7
517 ; CHECK-P8-NEXT: stvx v3, r3, r5
518 ; CHECK-P8-NEXT: stvx v4, r3, r6
519 ; CHECK-P8-NEXT: stvx v5, 0, r3
520 ; CHECK-P8-NEXT: blr
521 ;
522 ; CHECK-P9-LABEL: test16elt_signed:
523 ; CHECK-P9: # %bb.0: # %entry
524 ; CHECK-P9-NEXT: lxv vs6, 0(r4)
525 ; CHECK-P9-NEXT: lxv vs7, 16(r4)
526 ; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
527 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
528 ; CHECK-P9-NEXT: lxv vs4, 32(r4)
529 ; CHECK-P9-NEXT: lxv vs5, 48(r4)
530 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
531 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
532 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs8
533 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs6
534 ; CHECK-P9-NEXT: lxv vs2, 64(r4)
535 ; CHECK-P9-NEXT: lxv vs3, 80(r4)
536 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs7
537 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
538 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs4
539 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
540 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
541 ; CHECK-P9-NEXT: lxv vs0, 96(r4)
542 ; CHECK-P9-NEXT: lxv vs1, 112(r4)
543 ; CHECK-P9-NEXT: stxv v2, 0(r3)
544 ; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
545 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
546 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
547 ; CHECK-P9-NEXT: xvcvdpsxws v0, vs0
548 ; CHECK-P9-NEXT: vmrgew v3, v3, v4
549 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs4
550 ; CHECK-P9-NEXT: stxv v3, 16(r3)
551 ; CHECK-P9-NEXT: vmrgew v4, v5, v4
552 ; CHECK-P9-NEXT: stxv v4, 32(r3)
553 ; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
554 ; CHECK-P9-NEXT: vmrgew v5, v0, v5
555 ; CHECK-P9-NEXT: stxv v5, 48(r3)
556 ; CHECK-P9-NEXT: blr
557 ;
558 ; CHECK-BE-LABEL: test16elt_signed:
559 ; CHECK-BE: # %bb.0: # %entry
560 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
561 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
562 ; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
563 ; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
564 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
565 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
566 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
567 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
568 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs8
569 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs6
570 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
571 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
572 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs7
573 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
574 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs4
575 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
576 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
577 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
578 ; CHECK-BE-NEXT: lxv vs1, 96(r4)
579 ; CHECK-BE-NEXT: stxv v2, 0(r3)
580 ; CHECK-BE-NEXT: xvcvdpsxws v5, vs2
581 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
582 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
583 ; CHECK-BE-NEXT: xvcvdpsxws v0, vs0
584 ; CHECK-BE-NEXT: vmrgew v3, v3, v4
585 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs4
586 ; CHECK-BE-NEXT: stxv v3, 16(r3)
587 ; CHECK-BE-NEXT: vmrgew v4, v5, v4
588 ; CHECK-BE-NEXT: stxv v4, 32(r3)
589 ; CHECK-BE-NEXT: xvcvdpsxws v5, vs2
590 ; CHECK-BE-NEXT: vmrgew v5, v0, v5
591 ; CHECK-BE-NEXT: stxv v5, 48(r3)
592 ; CHECK-BE-NEXT: blr
593 entry:
594 %a = load <16 x double>, <16 x double>* %0, align 128
595 %1 = fptosi <16 x double> %a to <16 x i32>
596 store <16 x i32> %1, <16 x i32>* %agg.result, align 64
597 ret void
598 }