1 ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
2 ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
3 ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
4 ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
5 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
8 @d = common global double 0.000000e+00, align 8
9 @f = common global float 0.000000e+00, align 4
10 @i = common global i32 0, align 4
11 @ui = common global i32 0, align 4
13 ; Function Attrs: nounwind
14 define void @dblToInt() #0 {
16 %ii = alloca i32, align 4
17 %0 = load double, double* @d, align 8
18 %conv = fptosi double %0 to i32
19 store volatile i32 %conv, i32* %ii, align 4
21 ; CHECK-LABEL: @dblToInt
22 ; CHECK: xscvdpsxws [[REGCONV1:[0-9]+]],
23 ; CHECK: stfiwx [[REGCONV1]],
26 ; Function Attrs: nounwind
27 define void @fltToInt() #0 {
29 %ii = alloca i32, align 4
30 %0 = load float, float* @f, align 4
31 %conv = fptosi float %0 to i32
32 store volatile i32 %conv, i32* %ii, align 4
34 ; CHECK-LABEL: @fltToInt
35 ; CHECK: xscvdpsxws [[REGCONV2:[0-9]+]],
36 ; CHECK: stfiwx [[REGCONV2]],
39 ; Function Attrs: nounwind
40 define void @intToDbl() #0 {
42 %dd = alloca double, align 8
43 %0 = load i32, i32* @i, align 4
44 %conv = sitofp i32 %0 to double
45 store volatile double %conv, double* %dd, align 8
47 ; CHECK-LABEL: @intToDbl
48 ; CHECK: lfiwax [[REGLD1:[0-9]+]],
49 ; CHECK: xscvsxddp {{[0-9]+}}, [[REGLD1]]
52 ; Function Attrs: nounwind
53 define void @intToFlt() #0 {
55 %ff = alloca float, align 4
56 %0 = load i32, i32* @i, align 4
57 %conv = sitofp i32 %0 to float
58 store volatile float %conv, float* %ff, align 4
60 ; CHECK-LABEL: @intToFlt
61 ; CHECK: lfiwax [[REGLD2:[0-9]+]],
62 ; CHECK: xscvsxdsp {{[0-9]}}, [[REGLD2]]
65 ; Function Attrs: nounwind
66 define void @dblToUInt() #0 {
68 %uiui = alloca i32, align 4
69 %0 = load double, double* @d, align 8
70 %conv = fptoui double %0 to i32
71 store volatile i32 %conv, i32* %uiui, align 4
73 ; CHECK-LABEL: @dblToUInt
74 ; CHECK: xscvdpuxws [[REGCONV3:[0-9]+]],
75 ; CHECK: stfiwx [[REGCONV3]],
78 ; Function Attrs: nounwind
79 define void @fltToUInt() #0 {
81 %uiui = alloca i32, align 4
82 %0 = load float, float* @f, align 4
83 %conv = fptoui float %0 to i32
84 store volatile i32 %conv, i32* %uiui, align 4
86 ; CHECK-LABEL: @fltToUInt
87 ; CHECK: xscvdpuxws [[REGCONV4:[0-9]+]],
88 ; CHECK: stfiwx [[REGCONV4]],
91 ; Function Attrs: nounwind
92 define void @uIntToDbl() #0 {
94 %dd = alloca double, align 8
95 %0 = load i32, i32* @ui, align 4
96 %conv = uitofp i32 %0 to double
97 store volatile double %conv, double* %dd, align 8
99 ; CHECK-LABEL: @uIntToDbl
100 ; CHECK: lfiwzx [[REGLD3:[0-9]+]],
101 ; CHECK: xscvuxddp {{[0-9]+}}, [[REGLD3]]
104 ; Function Attrs: nounwind
105 define void @uIntToFlt() #0 {
107 %ff = alloca float, align 4
108 %0 = load i32, i32* @ui, align 4
109 %conv = uitofp i32 %0 to float
110 store volatile float %conv, float* %ff, align 4
112 ; CHECK-LABEL: @uIntToFlt
113 ; CHECK: lfiwzx [[REGLD4:[0-9]+]],
114 ; CHECK: xscvuxdsp {{[0-9]+}}, [[REGLD4]]
117 ; Function Attrs: nounwind
118 define void @dblToFloat() #0 {
120 %ff = alloca float, align 4
121 %0 = load double, double* @d, align 8
122 %conv = fptrunc double %0 to float
123 store volatile float %conv, float* %ff, align 4
125 ; CHECK-LABEL: @dblToFloat
126 ; CHECK: lfdx [[REGLD5:[0-9]+]],
127 ; CHECK: stfs [[REGLD5]],
128 ; CHECK-P9-LABEL: @dblToFloat
129 ; CHECK-P9: lfd [[REGLD5:[0-9]+]],
130 ; CHECK-P9: stfs [[REGLD5]],
133 ; Function Attrs: nounwind
134 define void @floatToDbl() #0 {
136 %dd = alloca double, align 8
137 %0 = load float, float* @f, align 4
138 %conv = fpext float %0 to double
139 store volatile double %conv, double* %dd, align 8
141 ; CHECK-LABEL: @floatToDbl
142 ; CHECK: lfsx [[REGLD5:[0-9]+]],
143 ; CHECK: stfd [[REGLD5]],
144 ; CHECK-P9-LABEL: @floatToDbl
145 ; CHECK-P9: lfs [[REGLD5:[0-9]+]],
146 ; CHECK-P9: stfd [[REGLD5]],