| blob | 9bf95bece61f1de49e839667bb31c346ec947291 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV32I %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefix=RV32IM %s
6 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7 ; RUN: | FileCheck -check-prefix=RV64I %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefix=RV64IM %s
11 define signext i32 @square(i32 %a) nounwind {
12 ; RV32I-LABEL: square:
13 ; RV32I: # %bb.0:
14 ; RV32I-NEXT: addi sp, sp, -16
15 ; RV32I-NEXT: sw ra, 12(sp)
16 ; RV32I-NEXT: mv a1, a0
17 ; RV32I-NEXT: call __mulsi3
18 ; RV32I-NEXT: lw ra, 12(sp)
19 ; RV32I-NEXT: addi sp, sp, 16
20 ; RV32I-NEXT: ret
21 ;
22 ; RV32IM-LABEL: square:
23 ; RV32IM: # %bb.0:
24 ; RV32IM-NEXT: mul a0, a0, a0
25 ; RV32IM-NEXT: ret
26 ;
27 ; RV64I-LABEL: square:
28 ; RV64I: # %bb.0:
29 ; RV64I-NEXT: addi sp, sp, -16
30 ; RV64I-NEXT: sd ra, 8(sp)
31 ; RV64I-NEXT: mv a1, a0
32 ; RV64I-NEXT: call __muldi3
33 ; RV64I-NEXT: sext.w a0, a0
34 ; RV64I-NEXT: ld ra, 8(sp)
35 ; RV64I-NEXT: addi sp, sp, 16
36 ; RV64I-NEXT: ret
37 ;
38 ; RV64IM-LABEL: square:
39 ; RV64IM: # %bb.0:
40 ; RV64IM-NEXT: mulw a0, a0, a0
41 ; RV64IM-NEXT: ret
42 %1 = mul i32 %a, %a
43 ret i32 %1
44 }
46 define signext i32 @mul(i32 %a, i32 %b) nounwind {
47 ; RV32I-LABEL: mul:
48 ; RV32I: # %bb.0:
49 ; RV32I-NEXT: addi sp, sp, -16
50 ; RV32I-NEXT: sw ra, 12(sp)
51 ; RV32I-NEXT: call __mulsi3
52 ; RV32I-NEXT: lw ra, 12(sp)
53 ; RV32I-NEXT: addi sp, sp, 16
54 ; RV32I-NEXT: ret
55 ;
56 ; RV32IM-LABEL: mul:
57 ; RV32IM: # %bb.0:
58 ; RV32IM-NEXT: mul a0, a0, a1
59 ; RV32IM-NEXT: ret
60 ;
61 ; RV64I-LABEL: mul:
62 ; RV64I: # %bb.0:
63 ; RV64I-NEXT: addi sp, sp, -16
64 ; RV64I-NEXT: sd ra, 8(sp)
65 ; RV64I-NEXT: call __muldi3
66 ; RV64I-NEXT: sext.w a0, a0
67 ; RV64I-NEXT: ld ra, 8(sp)
68 ; RV64I-NEXT: addi sp, sp, 16
69 ; RV64I-NEXT: ret
70 ;
71 ; RV64IM-LABEL: mul:
72 ; RV64IM: # %bb.0:
73 ; RV64IM-NEXT: mulw a0, a0, a1
74 ; RV64IM-NEXT: ret
75 %1 = mul i32 %a, %b
76 ret i32 %1
77 }
79 define signext i32 @mul_constant(i32 %a) nounwind {
80 ; RV32I-LABEL: mul_constant:
81 ; RV32I: # %bb.0:
82 ; RV32I-NEXT: addi sp, sp, -16
83 ; RV32I-NEXT: sw ra, 12(sp)
84 ; RV32I-NEXT: addi a1, zero, 5
85 ; RV32I-NEXT: call __mulsi3
86 ; RV32I-NEXT: lw ra, 12(sp)
87 ; RV32I-NEXT: addi sp, sp, 16
88 ; RV32I-NEXT: ret
89 ;
90 ; RV32IM-LABEL: mul_constant:
91 ; RV32IM: # %bb.0:
92 ; RV32IM-NEXT: addi a1, zero, 5
93 ; RV32IM-NEXT: mul a0, a0, a1
94 ; RV32IM-NEXT: ret
95 ;
96 ; RV64I-LABEL: mul_constant:
97 ; RV64I: # %bb.0:
98 ; RV64I-NEXT: addi sp, sp, -16
99 ; RV64I-NEXT: sd ra, 8(sp)
100 ; RV64I-NEXT: addi a1, zero, 5
101 ; RV64I-NEXT: call __muldi3
102 ; RV64I-NEXT: sext.w a0, a0
103 ; RV64I-NEXT: ld ra, 8(sp)
104 ; RV64I-NEXT: addi sp, sp, 16
105 ; RV64I-NEXT: ret
106 ;
107 ; RV64IM-LABEL: mul_constant:
108 ; RV64IM: # %bb.0:
109 ; RV64IM-NEXT: addi a1, zero, 5
110 ; RV64IM-NEXT: mulw a0, a0, a1
111 ; RV64IM-NEXT: ret
112 %1 = mul i32 %a, 5
113 ret i32 %1
114 }
116 define i32 @mul_pow2(i32 %a) nounwind {
117 ; RV32I-LABEL: mul_pow2:
118 ; RV32I: # %bb.0:
119 ; RV32I-NEXT: slli a0, a0, 3
120 ; RV32I-NEXT: ret
121 ;
122 ; RV32IM-LABEL: mul_pow2:
123 ; RV32IM: # %bb.0:
124 ; RV32IM-NEXT: slli a0, a0, 3
125 ; RV32IM-NEXT: ret
126 ;
127 ; RV64I-LABEL: mul_pow2:
128 ; RV64I: # %bb.0:
129 ; RV64I-NEXT: slli a0, a0, 3
130 ; RV64I-NEXT: ret
131 ;
132 ; RV64IM-LABEL: mul_pow2:
133 ; RV64IM: # %bb.0:
134 ; RV64IM-NEXT: slli a0, a0, 3
135 ; RV64IM-NEXT: ret
136 %1 = mul i32 %a, 8
137 ret i32 %1
138 }
140 define i64 @mul64(i64 %a, i64 %b) nounwind {
141 ; RV32I-LABEL: mul64:
142 ; RV32I: # %bb.0:
143 ; RV32I-NEXT: addi sp, sp, -16
144 ; RV32I-NEXT: sw ra, 12(sp)
145 ; RV32I-NEXT: call __muldi3
146 ; RV32I-NEXT: lw ra, 12(sp)
147 ; RV32I-NEXT: addi sp, sp, 16
148 ; RV32I-NEXT: ret
149 ;
150 ; RV32IM-LABEL: mul64:
151 ; RV32IM: # %bb.0:
152 ; RV32IM-NEXT: mul a3, a0, a3
153 ; RV32IM-NEXT: mulhu a4, a0, a2
154 ; RV32IM-NEXT: add a3, a4, a3
155 ; RV32IM-NEXT: mul a1, a1, a2
156 ; RV32IM-NEXT: add a1, a3, a1
157 ; RV32IM-NEXT: mul a0, a0, a2
158 ; RV32IM-NEXT: ret
159 ;
160 ; RV64I-LABEL: mul64:
161 ; RV64I: # %bb.0:
162 ; RV64I-NEXT: addi sp, sp, -16
163 ; RV64I-NEXT: sd ra, 8(sp)
164 ; RV64I-NEXT: call __muldi3
165 ; RV64I-NEXT: ld ra, 8(sp)
166 ; RV64I-NEXT: addi sp, sp, 16
167 ; RV64I-NEXT: ret
168 ;
169 ; RV64IM-LABEL: mul64:
170 ; RV64IM: # %bb.0:
171 ; RV64IM-NEXT: mul a0, a0, a1
172 ; RV64IM-NEXT: ret
173 %1 = mul i64 %a, %b
174 ret i64 %1
175 }
177 define i64 @mul64_constant(i64 %a) nounwind {
178 ; RV32I-LABEL: mul64_constant:
179 ; RV32I: # %bb.0:
180 ; RV32I-NEXT: addi sp, sp, -16
181 ; RV32I-NEXT: sw ra, 12(sp)
182 ; RV32I-NEXT: addi a2, zero, 5
183 ; RV32I-NEXT: mv a3, zero
184 ; RV32I-NEXT: call __muldi3
185 ; RV32I-NEXT: lw ra, 12(sp)
186 ; RV32I-NEXT: addi sp, sp, 16
187 ; RV32I-NEXT: ret
188 ;
189 ; RV32IM-LABEL: mul64_constant:
190 ; RV32IM: # %bb.0:
191 ; RV32IM-NEXT: addi a2, zero, 5
192 ; RV32IM-NEXT: mul a1, a1, a2
193 ; RV32IM-NEXT: mulhu a3, a0, a2
194 ; RV32IM-NEXT: add a1, a3, a1
195 ; RV32IM-NEXT: mul a0, a0, a2
196 ; RV32IM-NEXT: ret
197 ;
198 ; RV64I-LABEL: mul64_constant:
199 ; RV64I: # %bb.0:
200 ; RV64I-NEXT: addi sp, sp, -16
201 ; RV64I-NEXT: sd ra, 8(sp)
202 ; RV64I-NEXT: addi a1, zero, 5
203 ; RV64I-NEXT: call __muldi3
204 ; RV64I-NEXT: ld ra, 8(sp)
205 ; RV64I-NEXT: addi sp, sp, 16
206 ; RV64I-NEXT: ret
207 ;
208 ; RV64IM-LABEL: mul64_constant:
209 ; RV64IM: # %bb.0:
210 ; RV64IM-NEXT: addi a1, zero, 5
211 ; RV64IM-NEXT: mul a0, a0, a1
212 ; RV64IM-NEXT: ret
213 %1 = mul i64 %a, 5
214 ret i64 %1
215 }
217 define i32 @mulhs(i32 %a, i32 %b) nounwind {
218 ; RV32I-LABEL: mulhs:
219 ; RV32I: # %bb.0:
220 ; RV32I-NEXT: addi sp, sp, -16
221 ; RV32I-NEXT: sw ra, 12(sp)
222 ; RV32I-NEXT: mv a2, a1
223 ; RV32I-NEXT: srai a1, a0, 31
224 ; RV32I-NEXT: srai a3, a2, 31
225 ; RV32I-NEXT: call __muldi3
226 ; RV32I-NEXT: mv a0, a1
227 ; RV32I-NEXT: lw ra, 12(sp)
228 ; RV32I-NEXT: addi sp, sp, 16
229 ; RV32I-NEXT: ret
230 ;
231 ; RV32IM-LABEL: mulhs:
232 ; RV32IM: # %bb.0:
233 ; RV32IM-NEXT: mulh a0, a0, a1
234 ; RV32IM-NEXT: ret
235 ;
236 ; RV64I-LABEL: mulhs:
237 ; RV64I: # %bb.0:
238 ; RV64I-NEXT: addi sp, sp, -16
239 ; RV64I-NEXT: sd ra, 8(sp)
240 ; RV64I-NEXT: sext.w a0, a0
241 ; RV64I-NEXT: sext.w a1, a1
242 ; RV64I-NEXT: call __muldi3
243 ; RV64I-NEXT: srli a0, a0, 32
244 ; RV64I-NEXT: ld ra, 8(sp)
245 ; RV64I-NEXT: addi sp, sp, 16
246 ; RV64I-NEXT: ret
247 ;
248 ; RV64IM-LABEL: mulhs:
249 ; RV64IM: # %bb.0:
250 ; RV64IM-NEXT: sext.w a1, a1
251 ; RV64IM-NEXT: sext.w a0, a0
252 ; RV64IM-NEXT: mul a0, a0, a1
253 ; RV64IM-NEXT: srli a0, a0, 32
254 ; RV64IM-NEXT: ret
255 %1 = sext i32 %a to i64
256 %2 = sext i32 %b to i64
257 %3 = mul i64 %1, %2
258 %4 = lshr i64 %3, 32
259 %5 = trunc i64 %4 to i32
260 ret i32 %5
261 }
263 define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {
264 ; RV32I-LABEL: mulhu:
265 ; RV32I: # %bb.0:
266 ; RV32I-NEXT: addi sp, sp, -16
267 ; RV32I-NEXT: sw ra, 12(sp)
268 ; RV32I-NEXT: mv a2, a1
269 ; RV32I-NEXT: mv a1, zero
270 ; RV32I-NEXT: mv a3, zero
271 ; RV32I-NEXT: call __muldi3
272 ; RV32I-NEXT: mv a0, a1
273 ; RV32I-NEXT: lw ra, 12(sp)
274 ; RV32I-NEXT: addi sp, sp, 16
275 ; RV32I-NEXT: ret
276 ;
277 ; RV32IM-LABEL: mulhu:
278 ; RV32IM: # %bb.0:
279 ; RV32IM-NEXT: mulhu a0, a0, a1
280 ; RV32IM-NEXT: ret
281 ;
282 ; RV64I-LABEL: mulhu:
283 ; RV64I: # %bb.0:
284 ; RV64I-NEXT: addi sp, sp, -16
285 ; RV64I-NEXT: sd ra, 8(sp)
286 ; RV64I-NEXT: call __muldi3
287 ; RV64I-NEXT: srli a0, a0, 32
288 ; RV64I-NEXT: ld ra, 8(sp)
289 ; RV64I-NEXT: addi sp, sp, 16
290 ; RV64I-NEXT: ret
291 ;
292 ; RV64IM-LABEL: mulhu:
293 ; RV64IM: # %bb.0:
294 ; RV64IM-NEXT: mul a0, a0, a1
295 ; RV64IM-NEXT: srli a0, a0, 32
296 ; RV64IM-NEXT: ret
297 %1 = zext i32 %a to i64
298 %2 = zext i32 %b to i64
299 %3 = mul i64 %1, %2
300 %4 = lshr i64 %3, 32
301 %5 = trunc i64 %4 to i32
302 ret i32 %5
303 }