1 ; Test 32-bit addition in which the second operand is constant and in which
2 ; three-operand forms are available.
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
9 define zeroext i1 @f1(i32 %dummy, i32 %a, i32 *%res) {
11 ; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
12 ; CHECK-DAG: st [[REG1]], 0(%r4)
13 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
14 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
16 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
17 %val = extractvalue {i32, i1} %t, 0
18 %obit = extractvalue {i32, i1} %t, 1
19 store i32 %val, i32 *%res
23 ; Check the high end of the ALHSIK range.
24 define zeroext i1 @f2(i32 %dummy, i32 %a, i32 *%res) {
26 ; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 32767
27 ; CHECK-DAG: st [[REG1]], 0(%r4)
28 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
29 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
31 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 32767)
32 %val = extractvalue {i32, i1} %t, 0
33 %obit = extractvalue {i32, i1} %t, 1
34 store i32 %val, i32 *%res
38 ; Check the next value up, which must use ALFI instead.
39 define zeroext i1 @f3(i32 %dummy, i32 %a, i32 *%res) {
41 ; CHECK: alfi %r3, 32768
42 ; CHECK-DAG: st %r3, 0(%r4)
43 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
44 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
46 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 32768)
47 %val = extractvalue {i32, i1} %t, 0
48 %obit = extractvalue {i32, i1} %t, 1
49 store i32 %val, i32 *%res
53 ; Check the high end of the negative ALHSIK range.
54 define zeroext i1 @f4(i32 %dummy, i32 %a, i32 *%res) {
56 ; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -1
57 ; CHECK-DAG: st [[REG1]], 0(%r4)
58 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
59 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
61 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 -1)
62 %val = extractvalue {i32, i1} %t, 0
63 %obit = extractvalue {i32, i1} %t, 1
64 store i32 %val, i32 *%res
68 ; Check the low end of the ALHSIK range.
69 define zeroext i1 @f5(i32 %dummy, i32 %a, i32 *%res) {
71 ; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -32768
72 ; CHECK-DAG: st [[REG1]], 0(%r4)
73 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
74 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
76 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 -32768)
77 %val = extractvalue {i32, i1} %t, 0
78 %obit = extractvalue {i32, i1} %t, 1
79 store i32 %val, i32 *%res
83 ; Check the next value down, which must use ALFI instead.
84 define zeroext i1 @f6(i32 %dummy, i32 %a, i32 *%res) {
86 ; CHECK: alfi %r3, 4294934527
87 ; CHECK-DAG: st %r3, 0(%r4)
88 ; CHECK-DAG: ipm [[REG2:%r[0-5]]]
89 ; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
91 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 -32769)
92 %val = extractvalue {i32, i1} %t, 0
93 %obit = extractvalue {i32, i1} %t, 1
94 store i32 %val, i32 *%res
98 ; Check using the overflow result for a branch.
99 define void @f7(i32 %dummy, i32 %a, i32 *%res) {
101 ; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
102 ; CHECK-DAG: st [[REG1]], 0(%r4)
103 ; CHECK: jgnle foo@PLT
105 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
106 %val = extractvalue {i32, i1} %t, 0
107 %obit = extractvalue {i32, i1} %t, 1
108 store i32 %val, i32 *%res
109 br i1 %obit, label %call, label %exit
119 ; ... and the same with the inverted direction.
120 define void @f8(i32 %dummy, i32 %a, i32 *%res) {
122 ; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
123 ; CHECK-DAG: st [[REG1]], 0(%r4)
124 ; CHECK: jgle foo@PLT
126 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
127 %val = extractvalue {i32, i1} %t, 0
128 %obit = extractvalue {i32, i1} %t, 1
129 store i32 %val, i32 *%res
130 br i1 %obit, label %exit, label %call
141 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone