| blob | c8a937edf95c60921c687a9a6189649932702af5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=ENABLE
3 ; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=DISABLE
4 ; We cannot merge this test with the main test for shrink-wrapping, because
5 ; the code path we want to exerce is not taken with ios lowering.
6 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"
7 target triple = "armv7--linux-gnueabi"
9 @skip = internal unnamed_addr constant [2 x i8] c"\01\01", align 1
11 ; Check that we do not restore the before having used the saved CSRs.
12 ; This happened because of a bad use of the post-dominance property.
13 ; The exit block of the loop happens to also lead to defs/uses of CSRs.
14 ; It also post-dominates the loop body and we use to generate invalid
15 ; restore sequence. I.e., we restored too early.
17 define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnone %lim) {
18 ; ENABLE-LABEL: wrongUseOfPostDominate:
19 ; ENABLE: @ %bb.0: @ %entry
20 ; ENABLE-NEXT: .save {r11, lr}
21 ; ENABLE-NEXT: push {r11, lr}
22 ; ENABLE-NEXT: cmn r1, #1
23 ; ENABLE-NEXT: ble .LBB0_6
24 ; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader
25 ; ENABLE-NEXT: cmp r1, #0
26 ; ENABLE-NEXT: beq .LBB0_5
27 ; ENABLE-NEXT: @ %bb.2: @ %while.cond.preheader
28 ; ENABLE-NEXT: cmp r0, r2
29 ; ENABLE-NEXT: pophs {r11, pc}
30 ; ENABLE-NEXT: movw r12, :lower16:skip
31 ; ENABLE-NEXT: sub r1, r1, #1
32 ; ENABLE-NEXT: movt r12, :upper16:skip
33 ; ENABLE-NEXT: .LBB0_3: @ %while.body
34 ; ENABLE-NEXT: @ =>This Inner Loop Header: Depth=1
35 ; ENABLE-NEXT: ldrb r3, [r0]
36 ; ENABLE-NEXT: ldrb r3, [r12, r3]
37 ; ENABLE-NEXT: add r0, r0, r3
38 ; ENABLE-NEXT: sub r3, r1, #1
39 ; ENABLE-NEXT: cmp r3, r1
40 ; ENABLE-NEXT: bhs .LBB0_5
41 ; ENABLE-NEXT: @ %bb.4: @ %while.body
42 ; ENABLE-NEXT: @ in Loop: Header=BB0_3 Depth=1
43 ; ENABLE-NEXT: cmp r0, r2
44 ; ENABLE-NEXT: mov r1, r3
45 ; ENABLE-NEXT: blo .LBB0_3
46 ; ENABLE-NEXT: .LBB0_5: @ %if.end29
47 ; ENABLE-NEXT: pop {r11, pc}
48 ; ENABLE-NEXT: .LBB0_6: @ %while.cond2.outer
49 ; ENABLE-NEXT: @ =>This Loop Header: Depth=1
50 ; ENABLE-NEXT: @ Child Loop BB0_7 Depth 2
51 ; ENABLE-NEXT: @ Child Loop BB0_14 Depth 2
52 ; ENABLE-NEXT: mov r3, r0
53 ; ENABLE-NEXT: .LBB0_7: @ %while.cond2
54 ; ENABLE-NEXT: @ Parent Loop BB0_6 Depth=1
55 ; ENABLE-NEXT: @ => This Inner Loop Header: Depth=2
56 ; ENABLE-NEXT: add r1, r1, #1
57 ; ENABLE-NEXT: cmp r1, #1
58 ; ENABLE-NEXT: beq .LBB0_17
59 ; ENABLE-NEXT: @ %bb.8: @ %while.body4
60 ; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=2
61 ; ENABLE-NEXT: cmp r3, r2
62 ; ENABLE-NEXT: bls .LBB0_7
63 ; ENABLE-NEXT: @ %bb.9: @ %if.then7
64 ; ENABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
65 ; ENABLE-NEXT: mov r0, r3
66 ; ENABLE-NEXT: ldrb r12, [r0, #-1]!
67 ; ENABLE-NEXT: sxtb lr, r12
68 ; ENABLE-NEXT: cmn lr, #1
69 ; ENABLE-NEXT: bgt .LBB0_6
70 ; ENABLE-NEXT: @ %bb.10: @ %if.then7
71 ; ENABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
72 ; ENABLE-NEXT: cmp r0, r2
73 ; ENABLE-NEXT: bls .LBB0_6
74 ; ENABLE-NEXT: @ %bb.11: @ %land.rhs14.preheader
75 ; ENABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
76 ; ENABLE-NEXT: cmn lr, #1
77 ; ENABLE-NEXT: bgt .LBB0_6
78 ; ENABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
79 ; ENABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
80 ; ENABLE-NEXT: cmp r12, #191
81 ; ENABLE-NEXT: bhi .LBB0_6
82 ; ENABLE-NEXT: @ %bb.13: @ %while.body24.preheader
83 ; ENABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
84 ; ENABLE-NEXT: sub r3, r3, #2
85 ; ENABLE-NEXT: .LBB0_14: @ %while.body24
86 ; ENABLE-NEXT: @ Parent Loop BB0_6 Depth=1
87 ; ENABLE-NEXT: @ => This Inner Loop Header: Depth=2
88 ; ENABLE-NEXT: mov r0, r3
89 ; ENABLE-NEXT: cmp r3, r2
90 ; ENABLE-NEXT: bls .LBB0_6
91 ; ENABLE-NEXT: @ %bb.15: @ %while.body24.land.rhs14_crit_edge
92 ; ENABLE-NEXT: @ in Loop: Header=BB0_14 Depth=2
93 ; ENABLE-NEXT: mov r3, r0
94 ; ENABLE-NEXT: ldrsb lr, [r3], #-1
95 ; ENABLE-NEXT: cmn lr, #1
96 ; ENABLE-NEXT: uxtb r12, lr
97 ; ENABLE-NEXT: bgt .LBB0_6
98 ; ENABLE-NEXT: @ %bb.16: @ %while.body24.land.rhs14_crit_edge
99 ; ENABLE-NEXT: @ in Loop: Header=BB0_14 Depth=2
100 ; ENABLE-NEXT: cmp r12, #192
101 ; ENABLE-NEXT: blo .LBB0_14
102 ; ENABLE-NEXT: b .LBB0_6
103 ; ENABLE-NEXT: .LBB0_17:
104 ; ENABLE-NEXT: mov r0, r3
105 ; ENABLE-NEXT: pop {r11, pc}
106 ;
107 ; DISABLE-LABEL: wrongUseOfPostDominate:
108 ; DISABLE: @ %bb.0: @ %entry
109 ; DISABLE-NEXT: .save {r11, lr}
110 ; DISABLE-NEXT: push {r11, lr}
111 ; DISABLE-NEXT: cmn r1, #1
112 ; DISABLE-NEXT: ble .LBB0_6
113 ; DISABLE-NEXT: @ %bb.1: @ %while.cond.preheader
114 ; DISABLE-NEXT: cmp r1, #0
115 ; DISABLE-NEXT: beq .LBB0_5
116 ; DISABLE-NEXT: @ %bb.2: @ %while.cond.preheader
117 ; DISABLE-NEXT: cmp r0, r2
118 ; DISABLE-NEXT: pophs {r11, pc}
119 ; DISABLE-NEXT: movw r12, :lower16:skip
120 ; DISABLE-NEXT: sub r1, r1, #1
121 ; DISABLE-NEXT: movt r12, :upper16:skip
122 ; DISABLE-NEXT: .LBB0_3: @ %while.body
123 ; DISABLE-NEXT: @ =>This Inner Loop Header: Depth=1
124 ; DISABLE-NEXT: ldrb r3, [r0]
125 ; DISABLE-NEXT: ldrb r3, [r12, r3]
126 ; DISABLE-NEXT: add r0, r0, r3
127 ; DISABLE-NEXT: sub r3, r1, #1
128 ; DISABLE-NEXT: cmp r3, r1
129 ; DISABLE-NEXT: bhs .LBB0_5
130 ; DISABLE-NEXT: @ %bb.4: @ %while.body
131 ; DISABLE-NEXT: @ in Loop: Header=BB0_3 Depth=1
132 ; DISABLE-NEXT: cmp r0, r2
133 ; DISABLE-NEXT: mov r1, r3
134 ; DISABLE-NEXT: blo .LBB0_3
135 ; DISABLE-NEXT: .LBB0_5: @ %if.end29
136 ; DISABLE-NEXT: pop {r11, pc}
137 ; DISABLE-NEXT: .LBB0_6: @ %while.cond2.outer
138 ; DISABLE-NEXT: @ =>This Loop Header: Depth=1
139 ; DISABLE-NEXT: @ Child Loop BB0_7 Depth 2
140 ; DISABLE-NEXT: @ Child Loop BB0_14 Depth 2
141 ; DISABLE-NEXT: mov r3, r0
142 ; DISABLE-NEXT: .LBB0_7: @ %while.cond2
143 ; DISABLE-NEXT: @ Parent Loop BB0_6 Depth=1
144 ; DISABLE-NEXT: @ => This Inner Loop Header: Depth=2
145 ; DISABLE-NEXT: add r1, r1, #1
146 ; DISABLE-NEXT: cmp r1, #1
147 ; DISABLE-NEXT: beq .LBB0_17
148 ; DISABLE-NEXT: @ %bb.8: @ %while.body4
149 ; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=2
150 ; DISABLE-NEXT: cmp r3, r2
151 ; DISABLE-NEXT: bls .LBB0_7
152 ; DISABLE-NEXT: @ %bb.9: @ %if.then7
153 ; DISABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
154 ; DISABLE-NEXT: mov r0, r3
155 ; DISABLE-NEXT: ldrb r12, [r0, #-1]!
156 ; DISABLE-NEXT: sxtb lr, r12
157 ; DISABLE-NEXT: cmn lr, #1
158 ; DISABLE-NEXT: bgt .LBB0_6
159 ; DISABLE-NEXT: @ %bb.10: @ %if.then7
160 ; DISABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
161 ; DISABLE-NEXT: cmp r0, r2
162 ; DISABLE-NEXT: bls .LBB0_6
163 ; DISABLE-NEXT: @ %bb.11: @ %land.rhs14.preheader
164 ; DISABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
165 ; DISABLE-NEXT: cmn lr, #1
166 ; DISABLE-NEXT: bgt .LBB0_6
167 ; DISABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
168 ; DISABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
169 ; DISABLE-NEXT: cmp r12, #191
170 ; DISABLE-NEXT: bhi .LBB0_6
171 ; DISABLE-NEXT: @ %bb.13: @ %while.body24.preheader
172 ; DISABLE-NEXT: @ in Loop: Header=BB0_6 Depth=1
173 ; DISABLE-NEXT: sub r3, r3, #2
174 ; DISABLE-NEXT: .LBB0_14: @ %while.body24
175 ; DISABLE-NEXT: @ Parent Loop BB0_6 Depth=1
176 ; DISABLE-NEXT: @ => This Inner Loop Header: Depth=2
177 ; DISABLE-NEXT: mov r0, r3
178 ; DISABLE-NEXT: cmp r3, r2
179 ; DISABLE-NEXT: bls .LBB0_6
180 ; DISABLE-NEXT: @ %bb.15: @ %while.body24.land.rhs14_crit_edge
181 ; DISABLE-NEXT: @ in Loop: Header=BB0_14 Depth=2
182 ; DISABLE-NEXT: mov r3, r0
183 ; DISABLE-NEXT: ldrsb lr, [r3], #-1
184 ; DISABLE-NEXT: cmn lr, #1
185 ; DISABLE-NEXT: uxtb r12, lr
186 ; DISABLE-NEXT: bgt .LBB0_6
187 ; DISABLE-NEXT: @ %bb.16: @ %while.body24.land.rhs14_crit_edge
188 ; DISABLE-NEXT: @ in Loop: Header=BB0_14 Depth=2
189 ; DISABLE-NEXT: cmp r12, #192
190 ; DISABLE-NEXT: blo .LBB0_14
191 ; DISABLE-NEXT: b .LBB0_6
192 ; DISABLE-NEXT: .LBB0_17:
193 ; DISABLE-NEXT: mov r0, r3
194 ; DISABLE-NEXT: pop {r11, pc}
195 entry:
196 %cmp = icmp sgt i32 %off, -1
197 br i1 %cmp, label %while.cond.preheader, label %while.cond2.outer
199 while.cond.preheader: ; preds = %entry
200 %tobool4 = icmp ne i32 %off, 0
201 %cmp15 = icmp ult i8* %s, %lim
202 %sel66 = and i1 %tobool4, %cmp15
203 br i1 %sel66, label %while.body, label %if.end29
205 while.body: ; preds = %while.body, %while.cond.preheader
206 %s.addr.08 = phi i8* [ %add.ptr, %while.body ], [ %s, %while.cond.preheader ]
207 %off.addr.07 = phi i32 [ %dec, %while.body ], [ %off, %while.cond.preheader ]
208 %dec = add nsw i32 %off.addr.07, -1
209 %tmp = load i8, i8* %s.addr.08, align 1, !tbaa !2
210 %idxprom = zext i8 %tmp to i32
211 %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* @skip, i32 0, i32 %idxprom
212 %tmp1 = load i8, i8* %arrayidx, align 1, !tbaa !2
213 %conv = zext i8 %tmp1 to i32
214 %add.ptr = getelementptr inbounds i8, i8* %s.addr.08, i32 %conv
215 %tobool = icmp ne i32 %off.addr.07, 1
216 %cmp1 = icmp ult i8* %add.ptr, %lim
217 %sel6 = and i1 %tobool, %cmp1
218 br i1 %sel6, label %while.body, label %if.end29
220 while.cond2.outer: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24, %land.rhs14.preheader, %if.then7, %entry
221 %off.addr.1.ph = phi i32 [ %off, %entry ], [ %inc, %land.rhs14.preheader ], [ %inc, %if.then7 ], [ %inc, %while.body24.land.rhs14_crit_edge ], [ %inc, %while.body24 ]
222 %s.addr.1.ph = phi i8* [ %s, %entry ], [ %incdec.ptr, %land.rhs14.preheader ], [ %incdec.ptr, %if.then7 ], [ %lsr.iv, %while.body24.land.rhs14_crit_edge ], [ %lsr.iv, %while.body24 ]
223 br label %while.cond2
225 while.cond2: ; preds = %while.body4, %while.cond2.outer
226 %off.addr.1 = phi i32 [ %inc, %while.body4 ], [ %off.addr.1.ph, %while.cond2.outer ]
227 %inc = add nsw i32 %off.addr.1, 1
228 %tobool3 = icmp eq i32 %off.addr.1, 0
229 br i1 %tobool3, label %if.end29, label %while.body4
231 while.body4: ; preds = %while.cond2
232 %tmp2 = icmp ugt i8* %s.addr.1.ph, %lim
233 br i1 %tmp2, label %if.then7, label %while.cond2
235 if.then7: ; preds = %while.body4
236 %incdec.ptr = getelementptr inbounds i8, i8* %s.addr.1.ph, i32 -1
237 %tmp3 = load i8, i8* %incdec.ptr, align 1, !tbaa !2
238 %conv1525 = zext i8 %tmp3 to i32
239 %tobool9 = icmp slt i8 %tmp3, 0
240 %cmp129 = icmp ugt i8* %incdec.ptr, %lim
241 %or.cond13 = and i1 %tobool9, %cmp129
242 br i1 %or.cond13, label %land.rhs14.preheader, label %while.cond2.outer
244 land.rhs14.preheader: ; preds = %if.then7
245 %cmp1624 = icmp slt i8 %tmp3, 0
246 %cmp2026 = icmp ult i32 %conv1525, 192
247 %or.cond27 = and i1 %cmp1624, %cmp2026
248 br i1 %or.cond27, label %while.body24.preheader, label %while.cond2.outer
250 while.body24.preheader: ; preds = %land.rhs14.preheader
251 %scevgep = getelementptr i8, i8* %s.addr.1.ph, i32 -2
252 br label %while.body24
254 while.body24: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24.preheader
255 %lsr.iv = phi i8* [ %scevgep, %while.body24.preheader ], [ %scevgep34, %while.body24.land.rhs14_crit_edge ]
256 %cmp12 = icmp ugt i8* %lsr.iv, %lim
257 br i1 %cmp12, label %while.body24.land.rhs14_crit_edge, label %while.cond2.outer
259 while.body24.land.rhs14_crit_edge: ; preds = %while.body24
260 %.pre = load i8, i8* %lsr.iv, align 1, !tbaa !2
261 %cmp16 = icmp slt i8 %.pre, 0
262 %conv15 = zext i8 %.pre to i32
263 %cmp20 = icmp ult i32 %conv15, 192
264 %or.cond = and i1 %cmp16, %cmp20
265 %scevgep34 = getelementptr i8, i8* %lsr.iv, i32 -1
266 br i1 %or.cond, label %while.body24, label %while.cond2.outer
268 if.end29: ; preds = %while.cond2, %while.body, %while.cond.preheader
269 %s.addr.3 = phi i8* [ %s, %while.cond.preheader ], [ %add.ptr, %while.body ], [ %s.addr.1.ph, %while.cond2 ]
270 ret i8* %s.addr.3
271 }
273 !llvm.module.flags = !{!0, !1}
275 !0 = !{i32 1, !"wchar_size", i32 4}
276 !1 = !{i32 1, !"min_enum_size", i32 4}
277 !2 = !{!3, !3, i64 0}
278 !3 = !{!"omnipotent char", !4, i64 0}
279 !4 = !{!"Simple C/C++ TBAA"}