[ARM] Cortex-M4 schedule additions

[llvm-complete.git] / test / CodeGen / MIR / X86 / expected-power-of-2-after-align.mir

# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s

---
name: align_0
body: |
  bb.0:

    %0:_(p0) = IMPLICIT_DEF
    ; CHECK: [[@LINE+1]]:50: expected a power-of-2 literal after 'align'
    %1:_(s64) = G_LOAD %0(p0) :: (load 8, align 0)
...