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HEAD
[ARM] Cortex-M4 schedule additions
[llvm-complete.git]
/
test
/
CodeGen
/
MIR
/
X86
/
named-registers.mir
blob
1bb67225d38b7fb1a35ec4d8601bda9fade3ac86
1
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses X86 registers correctly.
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--- |
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define i32 @foo() {
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entry:
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ret i32 0
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}
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...
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---
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# CHECK: name: foo
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name: foo
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body: |
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bb.0.entry:
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; CHECK: $eax = MOV32r0
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; CHECK-NEXT: RETQ $eax
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$eax = MOV32r0 implicit-def $eflags
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RETQ $eax
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...