1 tblgen - Target Description To C++ Code Generator
2 =================================================
9 :program:`tblgen` [*options*] [*filename*]
14 :program:`tblgen` translates from target description (``.td``) files into C++
15 code that can be included in the definition of an LLVM target library. Most
16 users of LLVM will not need to use this program. It is only for assisting with
17 writing an LLVM target backend.
19 The input and output of :program:`tblgen` is beyond the scope of this short
20 introduction; please see the :doc:`introduction to TableGen
23 The *filename* argument specifies the name of a Target Description (``.td``)
24 file to read as input.
33 Print a summary of command line options.
35 .. option:: -o filename
37 Specify the output file name. If ``filename`` is ``-``, then
38 :program:`tblgen` sends its output to standard output.
40 .. option:: -I directory
42 Specify where to find other target description files for inclusion. The
43 ``directory`` value should be a full or partial path to a directory that
44 contains target description files.
46 .. option:: -asmparsernum N
48 Make -gen-asm-parser emit assembly writer number ``N``.
50 .. option:: -asmwriternum N
52 Make -gen-asm-writer emit assembly writer number ``N``.
54 .. option:: -class className
56 Print the enumeration list for this class.
58 .. option:: -print-records
60 Print all records to standard output (default).
62 .. option:: -dump-json
64 Print a JSON representation of all records, suitable for further
67 .. option:: -print-enums
69 Print enumeration values for a class.
71 .. option:: -print-sets
73 Print expanded sets for testing DAG exprs.
75 .. option:: -gen-emitter
77 Generate machine code emitter.
79 .. option:: -gen-register-info
81 Generate registers and register classes info.
83 .. option:: -gen-instr-info
85 Generate instruction descriptions.
87 .. option:: -gen-asm-writer
89 Generate the assembly writer.
91 .. option:: -gen-disassembler
93 Generate disassembler.
95 .. option:: -gen-pseudo-lowering
97 Generate pseudo instruction lowering.
99 .. option:: -gen-dag-isel
101 Generate a DAG (Directed Acycle Graph) instruction selector.
103 .. option:: -gen-asm-matcher
105 Generate assembly instruction matcher.
107 .. option:: -gen-dfa-packetizer
109 Generate DFA Packetizer for VLIW targets.
111 .. option:: -gen-fast-isel
113 Generate a "fast" instruction selector.
115 .. option:: -gen-subtarget
117 Generate subtarget enumerations.
119 .. option:: -gen-intrinsic-enums
121 Generate intrinsic enums.
123 .. option:: -gen-intrinsic-impl
125 Generate intrinsic implementation.
127 .. option:: -gen-tgt-intrinsic
129 Generate target intrinsic information.
131 .. option:: -gen-enhanced-disassembly-info
133 Generate enhanced disassembly info.
135 .. option:: -gen-exegesis
137 Generate llvm-exegesis tables.
141 Show the version number of this program.
146 If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
147 occurs, it will exit with a non-zero value.