1 //===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the BPFMCCodeEmitter class.
11 //===----------------------------------------------------------------------===//
13 #include "MCTargetDesc/BPFMCTargetDesc.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/MC/MCCodeEmitter.h"
16 #include "llvm/MC/MCFixup.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/Endian.h"
22 #include "llvm/Support/EndianStream.h"
28 #define DEBUG_TYPE "mccodeemitter"
32 class BPFMCCodeEmitter
: public MCCodeEmitter
{
33 const MCInstrInfo
&MCII
;
34 const MCRegisterInfo
&MRI
;
38 BPFMCCodeEmitter(const MCInstrInfo
&mcii
, const MCRegisterInfo
&mri
,
40 : MCII(mcii
), MRI(mri
), IsLittleEndian(IsLittleEndian
) {}
41 BPFMCCodeEmitter(const BPFMCCodeEmitter
&) = delete;
42 void operator=(const BPFMCCodeEmitter
&) = delete;
43 ~BPFMCCodeEmitter() override
= default;
45 // getBinaryCodeForInstr - TableGen'erated function for getting the
46 // binary encoding for an instruction.
47 uint64_t getBinaryCodeForInstr(const MCInst
&MI
,
48 SmallVectorImpl
<MCFixup
> &Fixups
,
49 const MCSubtargetInfo
&STI
) const;
51 // getMachineOpValue - Return binary encoding of operand. If the machin
52 // operand requires relocation, record the relocation and return zero.
53 unsigned getMachineOpValue(const MCInst
&MI
, const MCOperand
&MO
,
54 SmallVectorImpl
<MCFixup
> &Fixups
,
55 const MCSubtargetInfo
&STI
) const;
57 uint64_t getMemoryOpValue(const MCInst
&MI
, unsigned Op
,
58 SmallVectorImpl
<MCFixup
> &Fixups
,
59 const MCSubtargetInfo
&STI
) const;
61 void encodeInstruction(const MCInst
&MI
, raw_ostream
&OS
,
62 SmallVectorImpl
<MCFixup
> &Fixups
,
63 const MCSubtargetInfo
&STI
) const override
;
66 FeatureBitset
computeAvailableFeatures(const FeatureBitset
&FB
) const;
68 verifyInstructionPredicates(const MCInst
&MI
,
69 const FeatureBitset
&AvailableFeatures
) const;
72 } // end anonymous namespace
74 MCCodeEmitter
*llvm::createBPFMCCodeEmitter(const MCInstrInfo
&MCII
,
75 const MCRegisterInfo
&MRI
,
77 return new BPFMCCodeEmitter(MCII
, MRI
, true);
80 MCCodeEmitter
*llvm::createBPFbeMCCodeEmitter(const MCInstrInfo
&MCII
,
81 const MCRegisterInfo
&MRI
,
83 return new BPFMCCodeEmitter(MCII
, MRI
, false);
86 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst
&MI
,
88 SmallVectorImpl
<MCFixup
> &Fixups
,
89 const MCSubtargetInfo
&STI
) const {
91 return MRI
.getEncodingValue(MO
.getReg());
93 return static_cast<unsigned>(MO
.getImm());
97 const MCExpr
*Expr
= MO
.getExpr();
99 assert(Expr
->getKind() == MCExpr::SymbolRef
);
101 if (MI
.getOpcode() == BPF::JAL
)
103 Fixups
.push_back(MCFixup::create(0, Expr
, FK_PCRel_4
));
104 else if (MI
.getOpcode() == BPF::LD_imm64
)
105 Fixups
.push_back(MCFixup::create(0, Expr
, FK_SecRel_8
));
108 Fixups
.push_back(MCFixup::create(0, Expr
, FK_PCRel_2
));
113 static uint8_t SwapBits(uint8_t Val
)
115 return (Val
& 0x0F) << 4 | (Val
& 0xF0) >> 4;
118 void BPFMCCodeEmitter::encodeInstruction(const MCInst
&MI
, raw_ostream
&OS
,
119 SmallVectorImpl
<MCFixup
> &Fixups
,
120 const MCSubtargetInfo
&STI
) const {
121 verifyInstructionPredicates(MI
,
122 computeAvailableFeatures(STI
.getFeatureBits()));
124 unsigned Opcode
= MI
.getOpcode();
125 support::endian::Writer
OSE(OS
,
126 IsLittleEndian
? support::little
: support::big
);
128 if (Opcode
== BPF::LD_imm64
|| Opcode
== BPF::LD_pseudo
) {
129 uint64_t Value
= getBinaryCodeForInstr(MI
, Fixups
, STI
);
130 OS
<< char(Value
>> 56);
132 OS
<< char((Value
>> 48) & 0xff);
134 OS
<< char(SwapBits((Value
>> 48) & 0xff));
135 OSE
.write
<uint16_t>(0);
136 OSE
.write
<uint32_t>(Value
& 0xffffFFFF);
138 const MCOperand
&MO
= MI
.getOperand(1);
139 uint64_t Imm
= MO
.isImm() ? MO
.getImm() : 0;
140 OSE
.write
<uint8_t>(0);
141 OSE
.write
<uint8_t>(0);
142 OSE
.write
<uint16_t>(0);
143 OSE
.write
<uint32_t>(Imm
>> 32);
145 // Get instruction encoding and emit it
146 uint64_t Value
= getBinaryCodeForInstr(MI
, Fixups
, STI
);
147 OS
<< char(Value
>> 56);
149 OS
<< char((Value
>> 48) & 0xff);
151 OS
<< char(SwapBits((Value
>> 48) & 0xff));
152 OSE
.write
<uint16_t>((Value
>> 32) & 0xffff);
153 OSE
.write
<uint32_t>(Value
& 0xffffFFFF);
157 // Encode BPF Memory Operand
158 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst
&MI
, unsigned Op
,
159 SmallVectorImpl
<MCFixup
> &Fixups
,
160 const MCSubtargetInfo
&STI
) const {
162 const MCOperand Op1
= MI
.getOperand(1);
163 assert(Op1
.isReg() && "First operand is not register.");
164 Encoding
= MRI
.getEncodingValue(Op1
.getReg());
166 MCOperand Op2
= MI
.getOperand(2);
167 assert(Op2
.isImm() && "Second operand is not immediate.");
168 Encoding
|= Op2
.getImm() & 0xffff;
172 #define ENABLE_INSTR_PREDICATE_VERIFIER
173 #include "BPFGenMCCodeEmitter.inc"