lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp

   1 //===-- X86DisassemblerDecoder.cpp - Disassembler decoder -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file is part of the X86 Disassembler.
  10 // It contains the implementation of the instruction decoder.
  11 // Documentation for the disassembler can be found in X86Disassembler.h.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "X86DisassemblerDecoder.h"
  16 #include "llvm/ADT/StringRef.h"
  17
  18 #include <cstdarg> /* for va_*()       */
  19 #include <cstdio>  /* for vsnprintf()  */
  20 #include <cstdlib> /* for exit()       */
  21 #include <cstring> /* for memset()     */
  22
  23 using namespace llvm::X86Disassembler;
  24
  25 /// Specifies whether a ModR/M byte is needed and (if so) which
  26 /// instruction each possible value of the ModR/M byte corresponds to.  Once
  27 /// this information is known, we have narrowed down to a single instruction.
  28 struct ModRMDecision {
  29   uint8_t modrm_type;
  30   uint16_t instructionIDs;
  31 };
  32
  33 /// Specifies which set of ModR/M->instruction tables to look at
  34 /// given a particular opcode.
  35 struct OpcodeDecision {
  36   ModRMDecision modRMDecisions[256];
  37 };
  38
  39 /// Specifies which opcode->instruction tables to look at given
  40 /// a particular context (set of attributes).  Since there are many possible
  41 /// contexts, the decoder first uses CONTEXTS_SYM to determine which context
  42 /// applies given a specific set of attributes.  Hence there are only IC_max
  43 /// entries in this table, rather than 2^(ATTR_max).
  44 struct ContextDecision {
  45   OpcodeDecision opcodeDecisions[IC_max];
  46 };
  47
  48 #include "X86GenDisassemblerTables.inc"
  49
  50 #ifndef NDEBUG
  51 #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
  52 #else
  53 #define debug(s) do { } while (0)
  54 #endif
  55
  56 /*
  57  * contextForAttrs - Client for the instruction context table.  Takes a set of
  58  *   attributes and returns the appropriate decode context.
  59  *
  60  * @param attrMask  - Attributes, from the enumeration attributeBits.
  61  * @return          - The InstructionContext to use when looking up an
  62  *                    an instruction with these attributes.
  63  */
  64 static InstructionContext contextForAttrs(uint16_t attrMask) {
  65   return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
  66 }
  67
  68 /*
  69  * modRMRequired - Reads the appropriate instruction table to determine whether
  70  *   the ModR/M byte is required to decode a particular instruction.
  71  *
  72  * @param type        - The opcode type (i.e., how many bytes it has).
  73  * @param insnContext - The context for the instruction, as returned by
  74  *                      contextForAttrs.
  75  * @param opcode      - The last byte of the instruction's opcode, not counting
  76  *                      ModR/M extensions and escapes.
  77  * @return            - true if the ModR/M byte is required, false otherwise.
  78  */
  79 static int modRMRequired(OpcodeType type,
  80                          InstructionContext insnContext,
  81                          uint16_t opcode) {
  82   const struct ContextDecision* decision = nullptr;
  83
  84   switch (type) {
  85   case ONEBYTE:
  86     decision = &ONEBYTE_SYM;
  87     break;
  88   case TWOBYTE:
  89     decision = &TWOBYTE_SYM;
  90     break;
  91   case THREEBYTE_38:
  92     decision = &THREEBYTE38_SYM;
  93     break;
  94   case THREEBYTE_3A:
  95     decision = &THREEBYTE3A_SYM;
  96     break;
  97   case XOP8_MAP:
  98     decision = &XOP8_MAP_SYM;
  99     break;
 100   case XOP9_MAP:
 101     decision = &XOP9_MAP_SYM;
 102     break;
 103   case XOPA_MAP:
 104     decision = &XOPA_MAP_SYM;
 105     break;
 106   case THREEDNOW_MAP:
 107     decision = &THREEDNOW_MAP_SYM;
 108     break;
 109   }
 110
 111   return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
 112     modrm_type != MODRM_ONEENTRY;
 113 }
 114
 115 /*
 116  * decode - Reads the appropriate instruction table to obtain the unique ID of
 117  *   an instruction.
 118  *
 119  * @param type        - See modRMRequired().
 120  * @param insnContext - See modRMRequired().
 121  * @param opcode      - See modRMRequired().
 122  * @param modRM       - The ModR/M byte if required, or any value if not.
 123  * @return            - The UID of the instruction, or 0 on failure.
 124  */
 125 static InstrUID decode(OpcodeType type,
 126                        InstructionContext insnContext,
 127                        uint8_t opcode,
 128                        uint8_t modRM) {
 129   const struct ModRMDecision* dec = nullptr;
 130
 131   switch (type) {
 132   case ONEBYTE:
 133     dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 134     break;
 135   case TWOBYTE:
 136     dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 137     break;
 138   case THREEBYTE_38:
 139     dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 140     break;
 141   case THREEBYTE_3A:
 142     dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 143     break;
 144   case XOP8_MAP:
 145     dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 146     break;
 147   case XOP9_MAP:
 148     dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 149     break;
 150   case XOPA_MAP:
 151     dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 152     break;
 153   case THREEDNOW_MAP:
 154     dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
 155     break;
 156   }
 157
 158   switch (dec->modrm_type) {
 159   default:
 160     debug("Corrupt table!  Unknown modrm_type");
 161     return 0;
 162   case MODRM_ONEENTRY:
 163     return modRMTable[dec->instructionIDs];
 164   case MODRM_SPLITRM:
 165     if (modFromModRM(modRM) == 0x3)
 166       return modRMTable[dec->instructionIDs+1];
 167     return modRMTable[dec->instructionIDs];
 168   case MODRM_SPLITREG:
 169     if (modFromModRM(modRM) == 0x3)
 170       return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
 171     return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
 172   case MODRM_SPLITMISC:
 173     if (modFromModRM(modRM) == 0x3)
 174       return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
 175     return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
 176   case MODRM_FULL:
 177     return modRMTable[dec->instructionIDs+modRM];
 178   }
 179 }
 180
 181 /*
 182  * specifierForUID - Given a UID, returns the name and operand specification for
 183  *   that instruction.
 184  *
 185  * @param uid - The unique ID for the instruction.  This should be returned by
 186  *              decode(); specifierForUID will not check bounds.
 187  * @return    - A pointer to the specification for that instruction.
 188  */
 189 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
 190   return &INSTRUCTIONS_SYM[uid];
 191 }
 192
 193 /*
 194  * consumeByte - Uses the reader function provided by the user to consume one
 195  *   byte from the instruction's memory and advance the cursor.
 196  *
 197  * @param insn  - The instruction with the reader function to use.  The cursor
 198  *                for this instruction is advanced.
 199  * @param byte  - A pointer to a pre-allocated memory buffer to be populated
 200  *                with the data read.
 201  * @return      - 0 if the read was successful; nonzero otherwise.
 202  */
 203 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
 204   int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
 205
 206   if (!ret)
 207     ++(insn->readerCursor);
 208
 209   return ret;
 210 }
 211
 212 /*
 213  * lookAtByte - Like consumeByte, but does not advance the cursor.
 214  *
 215  * @param insn  - See consumeByte().
 216  * @param byte  - See consumeByte().
 217  * @return      - See consumeByte().
 218  */
 219 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
 220   return insn->reader(insn->readerArg, byte, insn->readerCursor);
 221 }
 222
 223 static void unconsumeByte(struct InternalInstruction* insn) {
 224   insn->readerCursor--;
 225 }
 226
 227 #define CONSUME_FUNC(name, type)                                  \
 228   static int name(struct InternalInstruction* insn, type* ptr) {  \
 229     type combined = 0;                                            \
 230     unsigned offset;                                              \
 231     for (offset = 0; offset < sizeof(type); ++offset) {           \
 232       uint8_t byte;                                               \
 233       int ret = insn->reader(insn->readerArg,                     \
 234                              &byte,                               \
 235                              insn->readerCursor + offset);        \
 236       if (ret)                                                    \
 237         return ret;                                               \
 238       combined = combined | ((uint64_t)byte << (offset * 8));     \
 239     }                                                             \
 240     *ptr = combined;                                              \
 241     insn->readerCursor += sizeof(type);                           \
 242     return 0;                                                     \
 243   }
 244
 245 /*
 246  * consume* - Use the reader function provided by the user to consume data
 247  *   values of various sizes from the instruction's memory and advance the
 248  *   cursor appropriately.  These readers perform endian conversion.
 249  *
 250  * @param insn    - See consumeByte().
 251  * @param ptr     - A pointer to a pre-allocated memory of appropriate size to
 252  *                  be populated with the data read.
 253  * @return        - See consumeByte().
 254  */
 255 CONSUME_FUNC(consumeInt8, int8_t)
 256 CONSUME_FUNC(consumeInt16, int16_t)
 257 CONSUME_FUNC(consumeInt32, int32_t)
 258 CONSUME_FUNC(consumeUInt16, uint16_t)
 259 CONSUME_FUNC(consumeUInt32, uint32_t)
 260 CONSUME_FUNC(consumeUInt64, uint64_t)
 261
 262 /*
 263  * dbgprintf - Uses the logging function provided by the user to log a single
 264  *   message, typically without a carriage-return.
 265  *
 266  * @param insn    - The instruction containing the logging function.
 267  * @param format  - See printf().
 268  * @param ...     - See printf().
 269  */
 270 static void dbgprintf(struct InternalInstruction* insn,
 271                       const char* format,
 272                       ...) {
 273   char buffer[256];
 274   va_list ap;
 275
 276   if (!insn->dlog)
 277     return;
 278
 279   va_start(ap, format);
 280   (void)vsnprintf(buffer, sizeof(buffer), format, ap);
 281   va_end(ap);
 282
 283   insn->dlog(insn->dlogArg, buffer);
 284 }
 285
 286 static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
 287   if (insn->mode == MODE_64BIT)
 288     return prefix >= 0x40 && prefix <= 0x4f;
 289   return false;
 290 }
 291
 292 /*
 293  * setPrefixPresent - Marks that a particular prefix is present as mandatory
 294  *
 295  * @param insn      - The instruction to be marked as having the prefix.
 296  * @param prefix    - The prefix that is present.
 297  */
 298 static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix) {
 299   uint8_t nextByte;
 300   switch (prefix) {
 301   case 0xf0:
 302     insn->hasLockPrefix = true;
 303     break;
 304   case 0xf2:
 305   case 0xf3:
 306     if (lookAtByte(insn, &nextByte))
 307       break;
 308     // TODO:
 309     //  1. There could be several 0x66
 310     //  2. if (nextByte == 0x66) and nextNextByte != 0x0f then
 311     //      it's not mandatory prefix
 312     //  3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
 313     //     0x0f exactly after it to be mandatory prefix
 314     if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66)
 315       // The last of 0xf2 /0xf3 is mandatory prefix
 316       insn->mandatoryPrefix = prefix;
 317     insn->repeatPrefix = prefix;
 318     break;
 319   case 0x66:
 320     if (lookAtByte(insn, &nextByte))
 321       break;
 322     // 0x66 can't overwrite existing mandatory prefix and should be ignored
 323     if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte)))
 324       insn->mandatoryPrefix = prefix;
 325     break;
 326   }
 327 }
 328
 329 /*
 330  * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
 331  *   instruction as having them.  Also sets the instruction's default operand,
 332  *   address, and other relevant data sizes to report operands correctly.
 333  *
 334  * @param insn  - The instruction whose prefixes are to be read.
 335  * @return      - 0 if the instruction could be read until the end of the prefix
 336  *                bytes, and no prefixes conflicted; nonzero otherwise.
 337  */
 338 static int readPrefixes(struct InternalInstruction* insn) {
 339   bool isPrefix = true;
 340   uint8_t byte = 0;
 341   uint8_t nextByte;
 342
 343   dbgprintf(insn, "readPrefixes()");
 344
 345   while (isPrefix) {
 346     /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
 347     if (consumeByte(insn, &byte))
 348       break;
 349
 350     /*
 351      * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
 352      * break and let it be disassembled as a normal "instruction".
 353      */
 354     if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK
 355       break;
 356
 357     if ((byte == 0xf2 || byte == 0xf3) && !lookAtByte(insn, &nextByte)) {
 358       /*
 359        * If the byte is 0xf2 or 0xf3, and any of the following conditions are
 360        * met:
 361        * - it is followed by a LOCK (0xf0) prefix
 362        * - it is followed by an xchg instruction
 363        * then it should be disassembled as a xacquire/xrelease not repne/rep.
 364        */
 365       if (((nextByte == 0xf0) ||
 366            ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
 367         insn->xAcquireRelease = true;
 368         if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support
 369           break;
 370       }
 371       /*
 372        * Also if the byte is 0xf3, and the following condition is met:
 373        * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
 374        *                       "mov mem, imm" (opcode 0xc6/0xc7) instructions.
 375        * then it should be disassembled as an xrelease not rep.
 376        */
 377       if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 ||
 378                            nextByte == 0xc6 || nextByte == 0xc7)) {
 379         insn->xAcquireRelease = true;
 380         break;
 381       }
 382       if (isREX(insn, nextByte)) {
 383         uint8_t nnextByte;
 384         // Go to REX prefix after the current one
 385         if (consumeByte(insn, &nnextByte))
 386           return -1;
 387         // We should be able to read next byte after REX prefix
 388         if (lookAtByte(insn, &nnextByte))
 389           return -1;
 390         unconsumeByte(insn);
 391       }
 392     }
 393
 394     switch (byte) {
 395     case 0xf0:  /* LOCK */
 396     case 0xf2:  /* REPNE/REPNZ */
 397     case 0xf3:  /* REP or REPE/REPZ */
 398       setPrefixPresent(insn, byte);
 399       break;
 400     case 0x2e:  /* CS segment override -OR- Branch not taken */
 401     case 0x36:  /* SS segment override -OR- Branch taken */
 402     case 0x3e:  /* DS segment override */
 403     case 0x26:  /* ES segment override */
 404     case 0x64:  /* FS segment override */
 405     case 0x65:  /* GS segment override */
 406       switch (byte) {
 407       case 0x2e:
 408         insn->segmentOverride = SEG_OVERRIDE_CS;
 409         break;
 410       case 0x36:
 411         insn->segmentOverride = SEG_OVERRIDE_SS;
 412         break;
 413       case 0x3e:
 414         insn->segmentOverride = SEG_OVERRIDE_DS;
 415         break;
 416       case 0x26:
 417         insn->segmentOverride = SEG_OVERRIDE_ES;
 418         break;
 419       case 0x64:
 420         insn->segmentOverride = SEG_OVERRIDE_FS;
 421         break;
 422       case 0x65:
 423         insn->segmentOverride = SEG_OVERRIDE_GS;
 424         break;
 425       default:
 426         debug("Unhandled override");
 427         return -1;
 428       }
 429       setPrefixPresent(insn, byte);
 430       break;
 431     case 0x66:  /* Operand-size override */
 432       insn->hasOpSize = true;
 433       setPrefixPresent(insn, byte);
 434       break;
 435     case 0x67:  /* Address-size override */
 436       insn->hasAdSize = true;
 437       setPrefixPresent(insn, byte);
 438       break;
 439     default:    /* Not a prefix byte */
 440       isPrefix = false;
 441       break;
 442     }
 443
 444     if (isPrefix)
 445       dbgprintf(insn, "Found prefix 0x%hhx", byte);
 446   }
 447
 448   insn->vectorExtensionType = TYPE_NO_VEX_XOP;
 449
 450   if (byte == 0x62) {
 451     uint8_t byte1, byte2;
 452
 453     if (consumeByte(insn, &byte1)) {
 454       dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
 455       return -1;
 456     }
 457
 458     if (lookAtByte(insn, &byte2)) {
 459       dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
 460       return -1;
 461     }
 462
 463     if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
 464        ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
 465       insn->vectorExtensionType = TYPE_EVEX;
 466     } else {
 467       unconsumeByte(insn); /* unconsume byte1 */
 468       unconsumeByte(insn); /* unconsume byte  */
 469     }
 470
 471     if (insn->vectorExtensionType == TYPE_EVEX) {
 472       insn->vectorExtensionPrefix[0] = byte;
 473       insn->vectorExtensionPrefix[1] = byte1;
 474       if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
 475         dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
 476         return -1;
 477       }
 478       if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
 479         dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
 480         return -1;
 481       }
 482
 483       /* We simulate the REX prefix for simplicity's sake */
 484       if (insn->mode == MODE_64BIT) {
 485         insn->rexPrefix = 0x40
 486                         | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
 487                         | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
 488                         | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
 489                         | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
 490       }
 491
 492       dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
 493               insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
 494               insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
 495     }
 496   } else if (byte == 0xc4) {
 497     uint8_t byte1;
 498
 499     if (lookAtByte(insn, &byte1)) {
 500       dbgprintf(insn, "Couldn't read second byte of VEX");
 501       return -1;
 502     }
 503
 504     if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
 505       insn->vectorExtensionType = TYPE_VEX_3B;
 506     else
 507       unconsumeByte(insn);
 508
 509     if (insn->vectorExtensionType == TYPE_VEX_3B) {
 510       insn->vectorExtensionPrefix[0] = byte;
 511       consumeByte(insn, &insn->vectorExtensionPrefix[1]);
 512       consumeByte(insn, &insn->vectorExtensionPrefix[2]);
 513
 514       /* We simulate the REX prefix for simplicity's sake */
 515
 516       if (insn->mode == MODE_64BIT)
 517         insn->rexPrefix = 0x40
 518                         | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
 519                         | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
 520                         | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
 521                         | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
 522
 523       dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
 524                 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
 525                 insn->vectorExtensionPrefix[2]);
 526     }
 527   } else if (byte == 0xc5) {
 528     uint8_t byte1;
 529
 530     if (lookAtByte(insn, &byte1)) {
 531       dbgprintf(insn, "Couldn't read second byte of VEX");
 532       return -1;
 533     }
 534
 535     if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
 536       insn->vectorExtensionType = TYPE_VEX_2B;
 537     else
 538       unconsumeByte(insn);
 539
 540     if (insn->vectorExtensionType == TYPE_VEX_2B) {
 541       insn->vectorExtensionPrefix[0] = byte;
 542       consumeByte(insn, &insn->vectorExtensionPrefix[1]);
 543
 544       if (insn->mode == MODE_64BIT)
 545         insn->rexPrefix = 0x40
 546                         | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
 547
 548       switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
 549       default:
 550         break;
 551       case VEX_PREFIX_66:
 552         insn->hasOpSize = true;
 553         break;
 554       }
 555
 556       dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
 557                 insn->vectorExtensionPrefix[0],
 558                 insn->vectorExtensionPrefix[1]);
 559     }
 560   } else if (byte == 0x8f) {
 561     uint8_t byte1;
 562
 563     if (lookAtByte(insn, &byte1)) {
 564       dbgprintf(insn, "Couldn't read second byte of XOP");
 565       return -1;
 566     }
 567
 568     if ((byte1 & 0x38) != 0x0) /* 0 in these 3 bits is a POP instruction. */
 569       insn->vectorExtensionType = TYPE_XOP;
 570     else
 571       unconsumeByte(insn);
 572
 573     if (insn->vectorExtensionType == TYPE_XOP) {
 574       insn->vectorExtensionPrefix[0] = byte;
 575       consumeByte(insn, &insn->vectorExtensionPrefix[1]);
 576       consumeByte(insn, &insn->vectorExtensionPrefix[2]);
 577
 578       /* We simulate the REX prefix for simplicity's sake */
 579
 580       if (insn->mode == MODE_64BIT)
 581         insn->rexPrefix = 0x40
 582                         | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
 583                         | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
 584                         | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
 585                         | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
 586
 587       switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
 588       default:
 589         break;
 590       case VEX_PREFIX_66:
 591         insn->hasOpSize = true;
 592         break;
 593       }
 594
 595       dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
 596                 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
 597                 insn->vectorExtensionPrefix[2]);
 598     }
 599   } else if (isREX(insn, byte)) {
 600     if (lookAtByte(insn, &nextByte))
 601       return -1;
 602     insn->rexPrefix = byte;
 603     dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
 604   } else
 605     unconsumeByte(insn);
 606
 607   if (insn->mode == MODE_16BIT) {
 608     insn->registerSize = (insn->hasOpSize ? 4 : 2);
 609     insn->addressSize = (insn->hasAdSize ? 4 : 2);
 610     insn->displacementSize = (insn->hasAdSize ? 4 : 2);
 611     insn->immediateSize = (insn->hasOpSize ? 4 : 2);
 612   } else if (insn->mode == MODE_32BIT) {
 613     insn->registerSize = (insn->hasOpSize ? 2 : 4);
 614     insn->addressSize = (insn->hasAdSize ? 2 : 4);
 615     insn->displacementSize = (insn->hasAdSize ? 2 : 4);
 616     insn->immediateSize = (insn->hasOpSize ? 2 : 4);
 617   } else if (insn->mode == MODE_64BIT) {
 618     if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
 619       insn->registerSize       = 8;
 620       insn->addressSize = (insn->hasAdSize ? 4 : 8);
 621       insn->displacementSize   = 4;
 622       insn->immediateSize      = 4;
 623     } else {
 624       insn->registerSize = (insn->hasOpSize ? 2 : 4);
 625       insn->addressSize = (insn->hasAdSize ? 4 : 8);
 626       insn->displacementSize = (insn->hasOpSize ? 2 : 4);
 627       insn->immediateSize = (insn->hasOpSize ? 2 : 4);
 628     }
 629   }
 630
 631   return 0;
 632 }
 633
 634 static int readModRM(struct InternalInstruction* insn);
 635
 636 /*
 637  * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
 638  *   extended or escape opcodes).
 639  *
 640  * @param insn  - The instruction whose opcode is to be read.
 641  * @return      - 0 if the opcode could be read successfully; nonzero otherwise.
 642  */
 643 static int readOpcode(struct InternalInstruction* insn) {
 644   /* Determine the length of the primary opcode */
 645
 646   uint8_t current;
 647
 648   dbgprintf(insn, "readOpcode()");
 649
 650   insn->opcodeType = ONEBYTE;
 651
 652   if (insn->vectorExtensionType == TYPE_EVEX) {
 653     switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
 654     default:
 655       dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
 656                 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
 657       return -1;
 658     case VEX_LOB_0F:
 659       insn->opcodeType = TWOBYTE;
 660       return consumeByte(insn, &insn->opcode);
 661     case VEX_LOB_0F38:
 662       insn->opcodeType = THREEBYTE_38;
 663       return consumeByte(insn, &insn->opcode);
 664     case VEX_LOB_0F3A:
 665       insn->opcodeType = THREEBYTE_3A;
 666       return consumeByte(insn, &insn->opcode);
 667     }
 668   } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
 669     switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
 670     default:
 671       dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
 672                 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
 673       return -1;
 674     case VEX_LOB_0F:
 675       insn->opcodeType = TWOBYTE;
 676       return consumeByte(insn, &insn->opcode);
 677     case VEX_LOB_0F38:
 678       insn->opcodeType = THREEBYTE_38;
 679       return consumeByte(insn, &insn->opcode);
 680     case VEX_LOB_0F3A:
 681       insn->opcodeType = THREEBYTE_3A;
 682       return consumeByte(insn, &insn->opcode);
 683     }
 684   } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
 685     insn->opcodeType = TWOBYTE;
 686     return consumeByte(insn, &insn->opcode);
 687   } else if (insn->vectorExtensionType == TYPE_XOP) {
 688     switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
 689     default:
 690       dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
 691                 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
 692       return -1;
 693     case XOP_MAP_SELECT_8:
 694       insn->opcodeType = XOP8_MAP;
 695       return consumeByte(insn, &insn->opcode);
 696     case XOP_MAP_SELECT_9:
 697       insn->opcodeType = XOP9_MAP;
 698       return consumeByte(insn, &insn->opcode);
 699     case XOP_MAP_SELECT_A:
 700       insn->opcodeType = XOPA_MAP;
 701       return consumeByte(insn, &insn->opcode);
 702     }
 703   }
 704
 705   if (consumeByte(insn, &current))
 706     return -1;
 707
 708   if (current == 0x0f) {
 709     dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
 710
 711     if (consumeByte(insn, &current))
 712       return -1;
 713
 714     if (current == 0x38) {
 715       dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
 716
 717       if (consumeByte(insn, &current))
 718         return -1;
 719
 720       insn->opcodeType = THREEBYTE_38;
 721     } else if (current == 0x3a) {
 722       dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
 723
 724       if (consumeByte(insn, &current))
 725         return -1;
 726
 727       insn->opcodeType = THREEBYTE_3A;
 728     } else if (current == 0x0f) {
 729       dbgprintf(insn, "Found a 3dnow escape prefix (0x%hhx)", current);
 730
 731       // Consume operands before the opcode to comply with the 3DNow encoding
 732       if (readModRM(insn))
 733         return -1;
 734
 735       if (consumeByte(insn, &current))
 736         return -1;
 737
 738       insn->opcodeType = THREEDNOW_MAP;
 739     } else {
 740       dbgprintf(insn, "Didn't find a three-byte escape prefix");
 741
 742       insn->opcodeType = TWOBYTE;
 743     }
 744   } else if (insn->mandatoryPrefix)
 745     // The opcode with mandatory prefix must start with opcode escape.
 746     // If not it's legacy repeat prefix
 747     insn->mandatoryPrefix = 0;
 748
 749   /*
 750    * At this point we have consumed the full opcode.
 751    * Anything we consume from here on must be unconsumed.
 752    */
 753
 754   insn->opcode = current;
 755
 756   return 0;
 757 }
 758
 759 /*
 760  * getIDWithAttrMask - Determines the ID of an instruction, consuming
 761  *   the ModR/M byte as appropriate for extended and escape opcodes,
 762  *   and using a supplied attribute mask.
 763  *
 764  * @param instructionID - A pointer whose target is filled in with the ID of the
 765  *                        instruction.
 766  * @param insn          - The instruction whose ID is to be determined.
 767  * @param attrMask      - The attribute mask to search.
 768  * @return              - 0 if the ModR/M could be read when needed or was not
 769  *                        needed; nonzero otherwise.
 770  */
 771 static int getIDWithAttrMask(uint16_t* instructionID,
 772                              struct InternalInstruction* insn,
 773                              uint16_t attrMask) {
 774   bool hasModRMExtension;
 775
 776   InstructionContext instructionClass = contextForAttrs(attrMask);
 777
 778   hasModRMExtension = modRMRequired(insn->opcodeType,
 779                                     instructionClass,
 780                                     insn->opcode);
 781
 782   if (hasModRMExtension) {
 783     if (readModRM(insn))
 784       return -1;
 785
 786     *instructionID = decode(insn->opcodeType,
 787                             instructionClass,
 788                             insn->opcode,
 789                             insn->modRM);
 790   } else {
 791     *instructionID = decode(insn->opcodeType,
 792                             instructionClass,
 793                             insn->opcode,
 794                             0);
 795   }
 796
 797   return 0;
 798 }
 799
 800 /*
 801  * is16BitEquivalent - Determines whether two instruction names refer to
 802  * equivalent instructions but one is 16-bit whereas the other is not.
 803  *
 804  * @param orig  - The instruction that is not 16-bit
 805  * @param equiv - The instruction that is 16-bit
 806  */
 807 static bool is16BitEquivalent(const char *orig, const char *equiv) {
 808   off_t i;
 809
 810   for (i = 0;; i++) {
 811     if (orig[i] == '\0' && equiv[i] == '\0')
 812       return true;
 813     if (orig[i] == '\0' || equiv[i] == '\0')
 814       return false;
 815     if (orig[i] != equiv[i]) {
 816       if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
 817         continue;
 818       if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
 819         continue;
 820       if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
 821         continue;
 822       return false;
 823     }
 824   }
 825 }
 826
 827 /*
 828  * is64Bit - Determines whether this instruction is a 64-bit instruction.
 829  *
 830  * @param name - The instruction that is not 16-bit
 831  */
 832 static bool is64Bit(const char *name) {
 833   off_t i;
 834
 835   for (i = 0;; ++i) {
 836     if (name[i] == '\0')
 837       return false;
 838     if (name[i] == '6' && name[i+1] == '4')
 839       return true;
 840   }
 841 }
 842
 843 /*
 844  * getID - Determines the ID of an instruction, consuming the ModR/M byte as
 845  *   appropriate for extended and escape opcodes.  Determines the attributes and
 846  *   context for the instruction before doing so.
 847  *
 848  * @param insn  - The instruction whose ID is to be determined.
 849  * @return      - 0 if the ModR/M could be read when needed or was not needed;
 850  *                nonzero otherwise.
 851  */
 852 static int getID(struct InternalInstruction* insn, const void *miiArg) {
 853   uint16_t attrMask;
 854   uint16_t instructionID;
 855
 856   dbgprintf(insn, "getID()");
 857
 858   attrMask = ATTR_NONE;
 859
 860   if (insn->mode == MODE_64BIT)
 861     attrMask |= ATTR_64BIT;
 862
 863   if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
 864     attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
 865
 866     if (insn->vectorExtensionType == TYPE_EVEX) {
 867       switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
 868       case VEX_PREFIX_66:
 869         attrMask |= ATTR_OPSIZE;
 870         break;
 871       case VEX_PREFIX_F3:
 872         attrMask |= ATTR_XS;
 873         break;
 874       case VEX_PREFIX_F2:
 875         attrMask |= ATTR_XD;
 876         break;
 877       }
 878
 879       if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
 880         attrMask |= ATTR_EVEXKZ;
 881       if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
 882         attrMask |= ATTR_EVEXB;
 883       if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
 884         attrMask |= ATTR_EVEXK;
 885       if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
 886         attrMask |= ATTR_VEXL;
 887       if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
 888         attrMask |= ATTR_EVEXL2;
 889     } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
 890       switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
 891       case VEX_PREFIX_66:
 892         attrMask |= ATTR_OPSIZE;
 893         break;
 894       case VEX_PREFIX_F3:
 895         attrMask |= ATTR_XS;
 896         break;
 897       case VEX_PREFIX_F2:
 898         attrMask |= ATTR_XD;
 899         break;
 900       }
 901
 902       if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
 903         attrMask |= ATTR_VEXL;
 904     } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
 905       switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
 906       case VEX_PREFIX_66:
 907         attrMask |= ATTR_OPSIZE;
 908         break;
 909       case VEX_PREFIX_F3:
 910         attrMask |= ATTR_XS;
 911         break;
 912       case VEX_PREFIX_F2:
 913         attrMask |= ATTR_XD;
 914         break;
 915       }
 916
 917       if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
 918         attrMask |= ATTR_VEXL;
 919     } else if (insn->vectorExtensionType == TYPE_XOP) {
 920       switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
 921       case VEX_PREFIX_66:
 922         attrMask |= ATTR_OPSIZE;
 923         break;
 924       case VEX_PREFIX_F3:
 925         attrMask |= ATTR_XS;
 926         break;
 927       case VEX_PREFIX_F2:
 928         attrMask |= ATTR_XD;
 929         break;
 930       }
 931
 932       if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
 933         attrMask |= ATTR_VEXL;
 934     } else {
 935       return -1;
 936     }
 937   } else if (!insn->mandatoryPrefix) {
 938     // If we don't have mandatory prefix we should use legacy prefixes here
 939     if (insn->hasOpSize && (insn->mode != MODE_16BIT))
 940       attrMask |= ATTR_OPSIZE;
 941     if (insn->hasAdSize)
 942       attrMask |= ATTR_ADSIZE;
 943     if (insn->opcodeType == ONEBYTE) {
 944       if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90))
 945         // Special support for PAUSE
 946         attrMask |= ATTR_XS;
 947     } else {
 948       if (insn->repeatPrefix == 0xf2)
 949         attrMask |= ATTR_XD;
 950       else if (insn->repeatPrefix == 0xf3)
 951         attrMask |= ATTR_XS;
 952     }
 953   } else {
 954     switch (insn->mandatoryPrefix) {
 955     case 0xf2:
 956       attrMask |= ATTR_XD;
 957       break;
 958     case 0xf3:
 959       attrMask |= ATTR_XS;
 960       break;
 961     case 0x66:
 962       if (insn->mode != MODE_16BIT)
 963         attrMask |= ATTR_OPSIZE;
 964       break;
 965     case 0x67:
 966       attrMask |= ATTR_ADSIZE;
 967       break;
 968     }
 969
 970   }
 971
 972   if (insn->rexPrefix & 0x08) {
 973     attrMask |= ATTR_REXW;
 974     attrMask &= ~ATTR_ADSIZE;
 975   }
 976
 977   /*
 978    * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
 979    * of the AdSize prefix is inverted w.r.t. 32-bit mode.
 980    */
 981   if (insn->mode == MODE_16BIT && insn->opcodeType == ONEBYTE &&
 982       insn->opcode == 0xE3)
 983     attrMask ^= ATTR_ADSIZE;
 984
 985   // If we're in 16-bit mode and this is one of the relative jumps and opsize
 986   // prefix isn't present, we need to force the opsize attribute since the
 987   // prefix is inverted relative to 32-bit mode.
 988   if (insn->mode == MODE_16BIT && !insn->hasOpSize &&
 989       insn->opcodeType == ONEBYTE &&
 990       (insn->opcode == 0xE8 || insn->opcode == 0xE9))
 991     attrMask |= ATTR_OPSIZE;
 992
 993   if (insn->mode == MODE_16BIT && !insn->hasOpSize &&
 994       insn->opcodeType == TWOBYTE &&
 995       insn->opcode >= 0x80 && insn->opcode <= 0x8F)
 996     attrMask |= ATTR_OPSIZE;
 997
 998   if (getIDWithAttrMask(&instructionID, insn, attrMask))
 999     return -1;
1000
1001   /* The following clauses compensate for limitations of the tables. */
1002
1003   if (insn->mode != MODE_64BIT &&
1004       insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
1005     /*
1006      * The tables can't distinquish between cases where the W-bit is used to
1007      * select register size and cases where its a required part of the opcode.
1008      */
1009     if ((insn->vectorExtensionType == TYPE_EVEX &&
1010          wFromEVEX3of4(insn->vectorExtensionPrefix[2])) ||
1011         (insn->vectorExtensionType == TYPE_VEX_3B &&
1012          wFromVEX3of3(insn->vectorExtensionPrefix[2])) ||
1013         (insn->vectorExtensionType == TYPE_XOP &&
1014          wFromXOP3of3(insn->vectorExtensionPrefix[2]))) {
1015
1016       uint16_t instructionIDWithREXW;
1017       if (getIDWithAttrMask(&instructionIDWithREXW,
1018                             insn, attrMask | ATTR_REXW)) {
1019         insn->instructionID = instructionID;
1020         insn->spec = specifierForUID(instructionID);
1021         return 0;
1022       }
1023
1024       auto SpecName = GetInstrName(instructionIDWithREXW, miiArg);
1025       // If not a 64-bit instruction. Switch the opcode.
1026       if (!is64Bit(SpecName.data())) {
1027         insn->instructionID = instructionIDWithREXW;
1028         insn->spec = specifierForUID(instructionIDWithREXW);
1029         return 0;
1030       }
1031     }
1032   }
1033
1034   /*
1035    * Absolute moves, umonitor, and movdir64b need special handling.
1036    * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
1037    *  inverted w.r.t.
1038    * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
1039    *  any position.
1040    */
1041   if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
1042       (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
1043       (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) {
1044     /* Make sure we observed the prefixes in any position. */
1045     if (insn->hasAdSize)
1046       attrMask |= ATTR_ADSIZE;
1047     if (insn->hasOpSize)
1048       attrMask |= ATTR_OPSIZE;
1049
1050     /* In 16-bit, invert the attributes. */
1051     if (insn->mode == MODE_16BIT) {
1052       attrMask ^= ATTR_ADSIZE;
1053
1054       /* The OpSize attribute is only valid with the absolute moves. */
1055       if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
1056         attrMask ^= ATTR_OPSIZE;
1057     }
1058
1059     if (getIDWithAttrMask(&instructionID, insn, attrMask))
1060       return -1;
1061
1062     insn->instructionID = instructionID;
1063     insn->spec = specifierForUID(instructionID);
1064     return 0;
1065   }
1066
1067   if ((insn->mode == MODE_16BIT || insn->hasOpSize) &&
1068       !(attrMask & ATTR_OPSIZE)) {
1069     /*
1070      * The instruction tables make no distinction between instructions that
1071      * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1072      * particular spot (i.e., many MMX operations).  In general we're
1073      * conservative, but in the specific case where OpSize is present but not
1074      * in the right place we check if there's a 16-bit operation.
1075      */
1076
1077     const struct InstructionSpecifier *spec;
1078     uint16_t instructionIDWithOpsize;
1079     llvm::StringRef specName, specWithOpSizeName;
1080
1081     spec = specifierForUID(instructionID);
1082
1083     if (getIDWithAttrMask(&instructionIDWithOpsize,
1084                           insn,
1085                           attrMask | ATTR_OPSIZE)) {
1086       /*
1087        * ModRM required with OpSize but not present; give up and return version
1088        * without OpSize set
1089        */
1090
1091       insn->instructionID = instructionID;
1092       insn->spec = spec;
1093       return 0;
1094     }
1095
1096     specName = GetInstrName(instructionID, miiArg);
1097     specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
1098
1099     if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
1100         (insn->mode == MODE_16BIT) ^ insn->hasOpSize) {
1101       insn->instructionID = instructionIDWithOpsize;
1102       insn->spec = specifierForUID(instructionIDWithOpsize);
1103     } else {
1104       insn->instructionID = instructionID;
1105       insn->spec = spec;
1106     }
1107     return 0;
1108   }
1109
1110   if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1111       insn->rexPrefix & 0x01) {
1112     /*
1113      * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1114      * it should decode as XCHG %r8, %eax.
1115      */
1116
1117     const struct InstructionSpecifier *spec;
1118     uint16_t instructionIDWithNewOpcode;
1119     const struct InstructionSpecifier *specWithNewOpcode;
1120
1121     spec = specifierForUID(instructionID);
1122
1123     /* Borrow opcode from one of the other XCHGar opcodes */
1124     insn->opcode = 0x91;
1125
1126     if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1127                           insn,
1128                           attrMask)) {
1129       insn->opcode = 0x90;
1130
1131       insn->instructionID = instructionID;
1132       insn->spec = spec;
1133       return 0;
1134     }
1135
1136     specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1137
1138     /* Change back */
1139     insn->opcode = 0x90;
1140
1141     insn->instructionID = instructionIDWithNewOpcode;
1142     insn->spec = specWithNewOpcode;
1143
1144     return 0;
1145   }
1146
1147   insn->instructionID = instructionID;
1148   insn->spec = specifierForUID(insn->instructionID);
1149
1150   return 0;
1151 }
1152
1153 /*
1154  * readSIB - Consumes the SIB byte to determine addressing information for an
1155  *   instruction.
1156  *
1157  * @param insn  - The instruction whose SIB byte is to be read.
1158  * @return      - 0 if the SIB byte was successfully read; nonzero otherwise.
1159  */
1160 static int readSIB(struct InternalInstruction* insn) {
1161   SIBBase sibBaseBase = SIB_BASE_NONE;
1162   uint8_t index, base;
1163
1164   dbgprintf(insn, "readSIB()");
1165
1166   if (insn->consumedSIB)
1167     return 0;
1168
1169   insn->consumedSIB = true;
1170
1171   switch (insn->addressSize) {
1172   case 2:
1173     dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1174     return -1;
1175   case 4:
1176     insn->sibIndexBase = SIB_INDEX_EAX;
1177     sibBaseBase = SIB_BASE_EAX;
1178     break;
1179   case 8:
1180     insn->sibIndexBase = SIB_INDEX_RAX;
1181     sibBaseBase = SIB_BASE_RAX;
1182     break;
1183   }
1184
1185   if (consumeByte(insn, &insn->sib))
1186     return -1;
1187
1188   index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1189
1190   if (index == 0x4) {
1191     insn->sibIndex = SIB_INDEX_NONE;
1192   } else {
1193     insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index);
1194   }
1195
1196   insn->sibScale = 1 << scaleFromSIB(insn->sib);
1197
1198   base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1199
1200   switch (base) {
1201   case 0x5:
1202   case 0xd:
1203     switch (modFromModRM(insn->modRM)) {
1204     case 0x0:
1205       insn->eaDisplacement = EA_DISP_32;
1206       insn->sibBase = SIB_BASE_NONE;
1207       break;
1208     case 0x1:
1209       insn->eaDisplacement = EA_DISP_8;
1210       insn->sibBase = (SIBBase)(sibBaseBase + base);
1211       break;
1212     case 0x2:
1213       insn->eaDisplacement = EA_DISP_32;
1214       insn->sibBase = (SIBBase)(sibBaseBase + base);
1215       break;
1216     case 0x3:
1217       debug("Cannot have Mod = 0b11 and a SIB byte");
1218       return -1;
1219     }
1220     break;
1221   default:
1222     insn->sibBase = (SIBBase)(sibBaseBase + base);
1223     break;
1224   }
1225
1226   return 0;
1227 }
1228
1229 /*
1230  * readDisplacement - Consumes the displacement of an instruction.
1231  *
1232  * @param insn  - The instruction whose displacement is to be read.
1233  * @return      - 0 if the displacement byte was successfully read; nonzero
1234  *                otherwise.
1235  */
1236 static int readDisplacement(struct InternalInstruction* insn) {
1237   int8_t d8;
1238   int16_t d16;
1239   int32_t d32;
1240
1241   dbgprintf(insn, "readDisplacement()");
1242
1243   if (insn->consumedDisplacement)
1244     return 0;
1245
1246   insn->consumedDisplacement = true;
1247   insn->displacementOffset = insn->readerCursor - insn->startLocation;
1248
1249   switch (insn->eaDisplacement) {
1250   case EA_DISP_NONE:
1251     insn->consumedDisplacement = false;
1252     break;
1253   case EA_DISP_8:
1254     if (consumeInt8(insn, &d8))
1255       return -1;
1256     insn->displacement = d8;
1257     break;
1258   case EA_DISP_16:
1259     if (consumeInt16(insn, &d16))
1260       return -1;
1261     insn->displacement = d16;
1262     break;
1263   case EA_DISP_32:
1264     if (consumeInt32(insn, &d32))
1265       return -1;
1266     insn->displacement = d32;
1267     break;
1268   }
1269
1270   insn->consumedDisplacement = true;
1271   return 0;
1272 }
1273
1274 /*
1275  * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1276  *   displacement) for an instruction and interprets it.
1277  *
1278  * @param insn  - The instruction whose addressing information is to be read.
1279  * @return      - 0 if the information was successfully read; nonzero otherwise.
1280  */
1281 static int readModRM(struct InternalInstruction* insn) {
1282   uint8_t mod, rm, reg, evexrm;
1283
1284   dbgprintf(insn, "readModRM()");
1285
1286   if (insn->consumedModRM)
1287     return 0;
1288
1289   if (consumeByte(insn, &insn->modRM))
1290     return -1;
1291   insn->consumedModRM = true;
1292
1293   mod     = modFromModRM(insn->modRM);
1294   rm      = rmFromModRM(insn->modRM);
1295   reg     = regFromModRM(insn->modRM);
1296
1297   /*
1298    * This goes by insn->registerSize to pick the correct register, which messes
1299    * up if we're using (say) XMM or 8-bit register operands.  That gets fixed in
1300    * fixupReg().
1301    */
1302   switch (insn->registerSize) {
1303   case 2:
1304     insn->regBase = MODRM_REG_AX;
1305     insn->eaRegBase = EA_REG_AX;
1306     break;
1307   case 4:
1308     insn->regBase = MODRM_REG_EAX;
1309     insn->eaRegBase = EA_REG_EAX;
1310     break;
1311   case 8:
1312     insn->regBase = MODRM_REG_RAX;
1313     insn->eaRegBase = EA_REG_RAX;
1314     break;
1315   }
1316
1317   reg |= rFromREX(insn->rexPrefix) << 3;
1318   rm  |= bFromREX(insn->rexPrefix) << 3;
1319
1320   evexrm = 0;
1321   if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) {
1322     reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1323     evexrm = xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1324   }
1325
1326   insn->reg = (Reg)(insn->regBase + reg);
1327
1328   switch (insn->addressSize) {
1329   case 2: {
1330     EABase eaBaseBase = EA_BASE_BX_SI;
1331
1332     switch (mod) {
1333     case 0x0:
1334       if (rm == 0x6) {
1335         insn->eaBase = EA_BASE_NONE;
1336         insn->eaDisplacement = EA_DISP_16;
1337         if (readDisplacement(insn))
1338           return -1;
1339       } else {
1340         insn->eaBase = (EABase)(eaBaseBase + rm);
1341         insn->eaDisplacement = EA_DISP_NONE;
1342       }
1343       break;
1344     case 0x1:
1345       insn->eaBase = (EABase)(eaBaseBase + rm);
1346       insn->eaDisplacement = EA_DISP_8;
1347       insn->displacementSize = 1;
1348       if (readDisplacement(insn))
1349         return -1;
1350       break;
1351     case 0x2:
1352       insn->eaBase = (EABase)(eaBaseBase + rm);
1353       insn->eaDisplacement = EA_DISP_16;
1354       if (readDisplacement(insn))
1355         return -1;
1356       break;
1357     case 0x3:
1358       insn->eaBase = (EABase)(insn->eaRegBase + rm);
1359       if (readDisplacement(insn))
1360         return -1;
1361       break;
1362     }
1363     break;
1364   }
1365   case 4:
1366   case 8: {
1367     EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1368
1369     switch (mod) {
1370     case 0x0:
1371       insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1372       // In determining whether RIP-relative mode is used (rm=5),
1373       // or whether a SIB byte is present (rm=4),
1374       // the extension bits (REX.b and EVEX.x) are ignored.
1375       switch (rm & 7) {
1376       case 0x4: // SIB byte is present
1377         insn->eaBase = (insn->addressSize == 4 ?
1378                         EA_BASE_sib : EA_BASE_sib64);
1379         if (readSIB(insn) || readDisplacement(insn))
1380           return -1;
1381         break;
1382       case 0x5: // RIP-relative
1383         insn->eaBase = EA_BASE_NONE;
1384         insn->eaDisplacement = EA_DISP_32;
1385         if (readDisplacement(insn))
1386           return -1;
1387         break;
1388       default:
1389         insn->eaBase = (EABase)(eaBaseBase + rm);
1390         break;
1391       }
1392       break;
1393     case 0x1:
1394       insn->displacementSize = 1;
1395       LLVM_FALLTHROUGH;
1396     case 0x2:
1397       insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1398       switch (rm & 7) {
1399       case 0x4: // SIB byte is present
1400         insn->eaBase = EA_BASE_sib;
1401         if (readSIB(insn) || readDisplacement(insn))
1402           return -1;
1403         break;
1404       default:
1405         insn->eaBase = (EABase)(eaBaseBase + rm);
1406         if (readDisplacement(insn))
1407           return -1;
1408         break;
1409       }
1410       break;
1411     case 0x3:
1412       insn->eaDisplacement = EA_DISP_NONE;
1413       insn->eaBase = (EABase)(insn->eaRegBase + rm + evexrm);
1414       break;
1415     }
1416     break;
1417   }
1418   } /* switch (insn->addressSize) */
1419
1420   return 0;
1421 }
1422
1423 #define GENERIC_FIXUP_FUNC(name, base, prefix, mask)      \
1424   static uint16_t name(struct InternalInstruction *insn,  \
1425                        OperandType type,                  \
1426                        uint8_t index,                     \
1427                        uint8_t *valid) {                  \
1428     *valid = 1;                                           \
1429     switch (type) {                                       \
1430     default:                                              \
1431       debug("Unhandled register type");                   \
1432       *valid = 0;                                         \
1433       return 0;                                           \
1434     case TYPE_Rv:                                         \
1435       return base + index;                                \
1436     case TYPE_R8:                                         \
1437       index &= mask;                                      \
1438       if (index > 0xf)                                    \
1439         *valid = 0;                                       \
1440       if (insn->rexPrefix &&                              \
1441          index >= 4 && index <= 7) {                      \
1442         return prefix##_SPL + (index - 4);                \
1443       } else {                                            \
1444         return prefix##_AL + index;                       \
1445       }                                                   \
1446     case TYPE_R16:                                        \
1447       index &= mask;                                      \
1448       if (index > 0xf)                                    \
1449         *valid = 0;                                       \
1450       return prefix##_AX + index;                         \
1451     case TYPE_R32:                                        \
1452       index &= mask;                                      \
1453       if (index > 0xf)                                    \
1454         *valid = 0;                                       \
1455       return prefix##_EAX + index;                        \
1456     case TYPE_R64:                                        \
1457       index &= mask;                                      \
1458       if (index > 0xf)                                    \
1459         *valid = 0;                                       \
1460       return prefix##_RAX + index;                        \
1461     case TYPE_ZMM:                                        \
1462       return prefix##_ZMM0 + index;                       \
1463     case TYPE_YMM:                                        \
1464       return prefix##_YMM0 + index;                       \
1465     case TYPE_XMM:                                        \
1466       return prefix##_XMM0 + index;                       \
1467     case TYPE_VK:                                         \
1468       index &= 0xf;                                       \
1469       if (index > 7)                                      \
1470         *valid = 0;                                       \
1471       return prefix##_K0 + index;                         \
1472     case TYPE_VK_PAIR:                                    \
1473       if (index > 7)                                      \
1474         *valid = 0;                                       \
1475       return prefix##_K0_K1 + (index / 2);                \
1476     case TYPE_MM64:                                       \
1477       return prefix##_MM0 + (index & 0x7);                \
1478     case TYPE_SEGMENTREG:                                 \
1479       if ((index & 7) > 5)                                \
1480         *valid = 0;                                       \
1481       return prefix##_ES + (index & 7);                   \
1482     case TYPE_DEBUGREG:                                   \
1483       return prefix##_DR0 + index;                        \
1484     case TYPE_CONTROLREG:                                 \
1485       return prefix##_CR0 + index;                        \
1486     case TYPE_BNDR:                                       \
1487       if (index > 3)                                      \
1488         *valid = 0;                                       \
1489       return prefix##_BND0 + index;                       \
1490     case TYPE_MVSIBX:                                     \
1491       return prefix##_XMM0 + index;                       \
1492     case TYPE_MVSIBY:                                     \
1493       return prefix##_YMM0 + index;                       \
1494     case TYPE_MVSIBZ:                                     \
1495       return prefix##_ZMM0 + index;                       \
1496     }                                                     \
1497   }
1498
1499 /*
1500  * fixup*Value - Consults an operand type to determine the meaning of the
1501  *   reg or R/M field.  If the operand is an XMM operand, for example, an
1502  *   operand would be XMM0 instead of AX, which readModRM() would otherwise
1503  *   misinterpret it as.
1504  *
1505  * @param insn  - The instruction containing the operand.
1506  * @param type  - The operand type.
1507  * @param index - The existing value of the field as reported by readModRM().
1508  * @param valid - The address of a uint8_t.  The target is set to 1 if the
1509  *                field is valid for the register class; 0 if not.
1510  * @return      - The proper value.
1511  */
1512 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase,    MODRM_REG, 0x1f)
1513 GENERIC_FIXUP_FUNC(fixupRMValue,  insn->eaRegBase,  EA_REG,    0xf)
1514
1515 /*
1516  * fixupReg - Consults an operand specifier to determine which of the
1517  *   fixup*Value functions to use in correcting readModRM()'ss interpretation.
1518  *
1519  * @param insn  - See fixup*Value().
1520  * @param op    - The operand specifier.
1521  * @return      - 0 if fixup was successful; -1 if the register returned was
1522  *                invalid for its class.
1523  */
1524 static int fixupReg(struct InternalInstruction *insn,
1525                     const struct OperandSpecifier *op) {
1526   uint8_t valid;
1527
1528   dbgprintf(insn, "fixupReg()");
1529
1530   switch ((OperandEncoding)op->encoding) {
1531   default:
1532     debug("Expected a REG or R/M encoding in fixupReg");
1533     return -1;
1534   case ENCODING_VVVV:
1535     insn->vvvv = (Reg)fixupRegValue(insn,
1536                                     (OperandType)op->type,
1537                                     insn->vvvv,
1538                                     &valid);
1539     if (!valid)
1540       return -1;
1541     break;
1542   case ENCODING_REG:
1543     insn->reg = (Reg)fixupRegValue(insn,
1544                                    (OperandType)op->type,
1545                                    insn->reg - insn->regBase,
1546                                    &valid);
1547     if (!valid)
1548       return -1;
1549     break;
1550   CASE_ENCODING_RM:
1551     if (insn->eaBase >= insn->eaRegBase) {
1552       insn->eaBase = (EABase)fixupRMValue(insn,
1553                                           (OperandType)op->type,
1554                                           insn->eaBase - insn->eaRegBase,
1555                                           &valid);
1556       if (!valid)
1557         return -1;
1558     }
1559     break;
1560   }
1561
1562   return 0;
1563 }
1564
1565 /*
1566  * readOpcodeRegister - Reads an operand from the opcode field of an
1567  *   instruction and interprets it appropriately given the operand width.
1568  *   Handles AddRegFrm instructions.
1569  *
1570  * @param insn  - the instruction whose opcode field is to be read.
1571  * @param size  - The width (in bytes) of the register being specified.
1572  *                1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1573  *                RAX.
1574  * @return      - 0 on success; nonzero otherwise.
1575  */
1576 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1577   dbgprintf(insn, "readOpcodeRegister()");
1578
1579   if (size == 0)
1580     size = insn->registerSize;
1581
1582   switch (size) {
1583   case 1:
1584     insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1585                                                   | (insn->opcode & 7)));
1586     if (insn->rexPrefix &&
1587         insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1588         insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1589       insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1590                                    + (insn->opcodeRegister - MODRM_REG_AL - 4));
1591     }
1592
1593     break;
1594   case 2:
1595     insn->opcodeRegister = (Reg)(MODRM_REG_AX
1596                                  + ((bFromREX(insn->rexPrefix) << 3)
1597                                     | (insn->opcode & 7)));
1598     break;
1599   case 4:
1600     insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1601                                  + ((bFromREX(insn->rexPrefix) << 3)
1602                                     | (insn->opcode & 7)));
1603     break;
1604   case 8:
1605     insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1606                                  + ((bFromREX(insn->rexPrefix) << 3)
1607                                     | (insn->opcode & 7)));
1608     break;
1609   }
1610
1611   return 0;
1612 }
1613
1614 /*
1615  * readImmediate - Consumes an immediate operand from an instruction, given the
1616  *   desired operand size.
1617  *
1618  * @param insn  - The instruction whose operand is to be read.
1619  * @param size  - The width (in bytes) of the operand.
1620  * @return      - 0 if the immediate was successfully consumed; nonzero
1621  *                otherwise.
1622  */
1623 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1624   uint8_t imm8;
1625   uint16_t imm16;
1626   uint32_t imm32;
1627   uint64_t imm64;
1628
1629   dbgprintf(insn, "readImmediate()");
1630
1631   if (insn->numImmediatesConsumed == 2) {
1632     debug("Already consumed two immediates");
1633     return -1;
1634   }
1635
1636   if (size == 0)
1637     size = insn->immediateSize;
1638   else
1639     insn->immediateSize = size;
1640   insn->immediateOffset = insn->readerCursor - insn->startLocation;
1641
1642   switch (size) {
1643   case 1:
1644     if (consumeByte(insn, &imm8))
1645       return -1;
1646     insn->immediates[insn->numImmediatesConsumed] = imm8;
1647     break;
1648   case 2:
1649     if (consumeUInt16(insn, &imm16))
1650       return -1;
1651     insn->immediates[insn->numImmediatesConsumed] = imm16;
1652     break;
1653   case 4:
1654     if (consumeUInt32(insn, &imm32))
1655       return -1;
1656     insn->immediates[insn->numImmediatesConsumed] = imm32;
1657     break;
1658   case 8:
1659     if (consumeUInt64(insn, &imm64))
1660       return -1;
1661     insn->immediates[insn->numImmediatesConsumed] = imm64;
1662     break;
1663   }
1664
1665   insn->numImmediatesConsumed++;
1666
1667   return 0;
1668 }
1669
1670 /*
1671  * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1672  *
1673  * @param insn  - The instruction whose operand is to be read.
1674  * @return      - 0 if the vvvv was successfully consumed; nonzero
1675  *                otherwise.
1676  */
1677 static int readVVVV(struct InternalInstruction* insn) {
1678   dbgprintf(insn, "readVVVV()");
1679
1680   int vvvv;
1681   if (insn->vectorExtensionType == TYPE_EVEX)
1682     vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1683             vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]));
1684   else if (insn->vectorExtensionType == TYPE_VEX_3B)
1685     vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1686   else if (insn->vectorExtensionType == TYPE_VEX_2B)
1687     vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1688   else if (insn->vectorExtensionType == TYPE_XOP)
1689     vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1690   else
1691     return -1;
1692
1693   if (insn->mode != MODE_64BIT)
1694     vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
1695
1696   insn->vvvv = static_cast<Reg>(vvvv);
1697   return 0;
1698 }
1699
1700 /*
1701  * readMaskRegister - Reads an mask register from the opcode field of an
1702  *   instruction.
1703  *
1704  * @param insn    - The instruction whose opcode field is to be read.
1705  * @return        - 0 on success; nonzero otherwise.
1706  */
1707 static int readMaskRegister(struct InternalInstruction* insn) {
1708   dbgprintf(insn, "readMaskRegister()");
1709
1710   if (insn->vectorExtensionType != TYPE_EVEX)
1711     return -1;
1712
1713   insn->writemask =
1714       static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1715   return 0;
1716 }
1717
1718 /*
1719  * readOperands - Consults the specifier for an instruction and consumes all
1720  *   operands for that instruction, interpreting them as it goes.
1721  *
1722  * @param insn  - The instruction whose operands are to be read and interpreted.
1723  * @return      - 0 if all operands could be read; nonzero otherwise.
1724  */
1725 static int readOperands(struct InternalInstruction* insn) {
1726   int hasVVVV, needVVVV;
1727   int sawRegImm = 0;
1728
1729   dbgprintf(insn, "readOperands()");
1730
1731   /* If non-zero vvvv specified, need to make sure one of the operands
1732      uses it. */
1733   hasVVVV = !readVVVV(insn);
1734   needVVVV = hasVVVV && (insn->vvvv != 0);
1735
1736   for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1737     switch (Op.encoding) {
1738     case ENCODING_NONE:
1739     case ENCODING_SI:
1740     case ENCODING_DI:
1741       break;
1742     CASE_ENCODING_VSIB:
1743       // VSIB can use the V2 bit so check only the other bits.
1744       if (needVVVV)
1745         needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1746       if (readModRM(insn))
1747         return -1;
1748
1749       // Reject if SIB wasn't used.
1750       if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1751         return -1;
1752
1753       // If sibIndex was set to SIB_INDEX_NONE, index offset is 4.
1754       if (insn->sibIndex == SIB_INDEX_NONE)
1755         insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4);
1756
1757       // If EVEX.v2 is set this is one of the 16-31 registers.
1758       if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
1759           v2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
1760         insn->sibIndex = (SIBIndex)(insn->sibIndex + 16);
1761
1762       // Adjust the index register to the correct size.
1763       switch ((OperandType)Op.type) {
1764       default:
1765         debug("Unhandled VSIB index type");
1766         return -1;
1767       case TYPE_MVSIBX:
1768         insn->sibIndex = (SIBIndex)(SIB_INDEX_XMM0 +
1769                                     (insn->sibIndex - insn->sibIndexBase));
1770         break;
1771       case TYPE_MVSIBY:
1772         insn->sibIndex = (SIBIndex)(SIB_INDEX_YMM0 +
1773                                     (insn->sibIndex - insn->sibIndexBase));
1774         break;
1775       case TYPE_MVSIBZ:
1776         insn->sibIndex = (SIBIndex)(SIB_INDEX_ZMM0 +
1777                                     (insn->sibIndex - insn->sibIndexBase));
1778         break;
1779       }
1780
1781       // Apply the AVX512 compressed displacement scaling factor.
1782       if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1783         insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
1784       break;
1785     case ENCODING_REG:
1786     CASE_ENCODING_RM:
1787       if (readModRM(insn))
1788         return -1;
1789       if (fixupReg(insn, &Op))
1790         return -1;
1791       // Apply the AVX512 compressed displacement scaling factor.
1792       if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1793         insn->displacement *= 1 << (Op.encoding - ENCODING_RM);
1794       break;
1795     case ENCODING_IB:
1796       if (sawRegImm) {
1797         /* Saw a register immediate so don't read again and instead split the
1798            previous immediate.  FIXME: This is a hack. */
1799         insn->immediates[insn->numImmediatesConsumed] =
1800           insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1801         ++insn->numImmediatesConsumed;
1802         break;
1803       }
1804       if (readImmediate(insn, 1))
1805         return -1;
1806       if (Op.type == TYPE_XMM || Op.type == TYPE_YMM)
1807         sawRegImm = 1;
1808       break;
1809     case ENCODING_IW:
1810       if (readImmediate(insn, 2))
1811         return -1;
1812       break;
1813     case ENCODING_ID:
1814       if (readImmediate(insn, 4))
1815         return -1;
1816       break;
1817     case ENCODING_IO:
1818       if (readImmediate(insn, 8))
1819         return -1;
1820       break;
1821     case ENCODING_Iv:
1822       if (readImmediate(insn, insn->immediateSize))
1823         return -1;
1824       break;
1825     case ENCODING_Ia:
1826       if (readImmediate(insn, insn->addressSize))
1827         return -1;
1828       break;
1829     case ENCODING_IRC:
1830       insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) |
1831                  lFromEVEX4of4(insn->vectorExtensionPrefix[3]);
1832       break;
1833     case ENCODING_RB:
1834       if (readOpcodeRegister(insn, 1))
1835         return -1;
1836       break;
1837     case ENCODING_RW:
1838       if (readOpcodeRegister(insn, 2))
1839         return -1;
1840       break;
1841     case ENCODING_RD:
1842       if (readOpcodeRegister(insn, 4))
1843         return -1;
1844       break;
1845     case ENCODING_RO:
1846       if (readOpcodeRegister(insn, 8))
1847         return -1;
1848       break;
1849     case ENCODING_Rv:
1850       if (readOpcodeRegister(insn, 0))
1851         return -1;
1852       break;
1853     case ENCODING_CC:
1854       insn->immediates[1] = insn->opcode & 0xf;
1855       break;
1856     case ENCODING_FP:
1857       break;
1858     case ENCODING_VVVV:
1859       needVVVV = 0; /* Mark that we have found a VVVV operand. */
1860       if (!hasVVVV)
1861         return -1;
1862       if (insn->mode != MODE_64BIT)
1863         insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
1864       if (fixupReg(insn, &Op))
1865         return -1;
1866       break;
1867     case ENCODING_WRITEMASK:
1868       if (readMaskRegister(insn))
1869         return -1;
1870       break;
1871     case ENCODING_DUP:
1872       break;
1873     default:
1874       dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1875       return -1;
1876     }
1877   }
1878
1879   /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1880   if (needVVVV) return -1;
1881
1882   return 0;
1883 }
1884
1885 /*
1886  * decodeInstruction - Reads and interprets a full instruction provided by the
1887  *   user.
1888  *
1889  * @param insn      - A pointer to the instruction to be populated.  Must be
1890  *                    pre-allocated.
1891  * @param reader    - The function to be used to read the instruction's bytes.
1892  * @param readerArg - A generic argument to be passed to the reader to store
1893  *                    any internal state.
1894  * @param logger    - If non-NULL, the function to be used to write log messages
1895  *                    and warnings.
1896  * @param loggerArg - A generic argument to be passed to the logger to store
1897  *                    any internal state.
1898  * @param startLoc  - The address (in the reader's address space) of the first
1899  *                    byte in the instruction.
1900  * @param mode      - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1901  *                    decode the instruction in.
1902  * @return          - 0 if the instruction's memory could be read; nonzero if
1903  *                    not.
1904  */
1905 int llvm::X86Disassembler::decodeInstruction(
1906     struct InternalInstruction *insn, byteReader_t reader,
1907     const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
1908     uint64_t startLoc, DisassemblerMode mode) {
1909   memset(insn, 0, sizeof(struct InternalInstruction));
1910
1911   insn->reader = reader;
1912   insn->readerArg = readerArg;
1913   insn->dlog = logger;
1914   insn->dlogArg = loggerArg;
1915   insn->startLocation = startLoc;
1916   insn->readerCursor = startLoc;
1917   insn->mode = mode;
1918   insn->numImmediatesConsumed = 0;
1919
1920   if (readPrefixes(insn)       ||
1921       readOpcode(insn)         ||
1922       getID(insn, miiArg)      ||
1923       insn->instructionID == 0 ||
1924       readOperands(insn))
1925     return -1;
1926
1927   insn->operands = x86OperandSets[insn->spec->operands];
1928
1929   insn->length = insn->readerCursor - insn->startLocation;
1930
1931   dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1932             startLoc, insn->readerCursor, insn->length);
1933
1934   if (insn->length > 15)
1935     dbgprintf(insn, "Instruction exceeds 15-byte limit");
1936
1937   return 0;
1938 }