[InstCombine] Signed saturation patterns
[llvm-complete.git] / lib / Target / X86 / Disassembler / X86DisassemblerDecoder.h
blob7c0a42c019e3506e56304666a5d8a3972b62944b
1 //===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the X86 Disassembler.
10 // It contains the public interface of the instruction decoder.
11 // Documentation for the disassembler can be found in X86Disassembler.h.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
16 #define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/Support/X86DisassemblerDecoderCommon.h"
21 namespace llvm {
22 namespace X86Disassembler {
24 // Accessor functions for various fields of an Intel instruction
25 #define modFromModRM(modRM) (((modRM) & 0xc0) >> 6)
26 #define regFromModRM(modRM) (((modRM) & 0x38) >> 3)
27 #define rmFromModRM(modRM) ((modRM) & 0x7)
28 #define scaleFromSIB(sib) (((sib) & 0xc0) >> 6)
29 #define indexFromSIB(sib) (((sib) & 0x38) >> 3)
30 #define baseFromSIB(sib) ((sib) & 0x7)
31 #define wFromREX(rex) (((rex) & 0x8) >> 3)
32 #define rFromREX(rex) (((rex) & 0x4) >> 2)
33 #define xFromREX(rex) (((rex) & 0x2) >> 1)
34 #define bFromREX(rex) ((rex) & 0x1)
36 #define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7)
37 #define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6)
38 #define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5)
39 #define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4)
40 #define mmFromEVEX2of4(evex) ((evex) & 0x3)
41 #define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7)
42 #define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3)
43 #define ppFromEVEX3of4(evex) ((evex) & 0x3)
44 #define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7)
45 #define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6)
46 #define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5)
47 #define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4)
48 #define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3)
49 #define aaaFromEVEX4of4(evex) ((evex) & 0x7)
51 #define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
52 #define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
53 #define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
54 #define mmmmmFromVEX2of3(vex) ((vex) & 0x1f)
55 #define wFromVEX3of3(vex) (((vex) & 0x80) >> 7)
56 #define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3)
57 #define lFromVEX3of3(vex) (((vex) & 0x4) >> 2)
58 #define ppFromVEX3of3(vex) ((vex) & 0x3)
60 #define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7)
61 #define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3)
62 #define lFromVEX2of2(vex) (((vex) & 0x4) >> 2)
63 #define ppFromVEX2of2(vex) ((vex) & 0x3)
65 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7)
66 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6)
67 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5)
68 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f)
69 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7)
70 #define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3)
71 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2)
72 #define ppFromXOP3of3(xop) ((xop) & 0x3)
74 // These enums represent Intel registers for use by the decoder.
75 #define REGS_8BIT \
76 ENTRY(AL) \
77 ENTRY(CL) \
78 ENTRY(DL) \
79 ENTRY(BL) \
80 ENTRY(AH) \
81 ENTRY(CH) \
82 ENTRY(DH) \
83 ENTRY(BH) \
84 ENTRY(R8B) \
85 ENTRY(R9B) \
86 ENTRY(R10B) \
87 ENTRY(R11B) \
88 ENTRY(R12B) \
89 ENTRY(R13B) \
90 ENTRY(R14B) \
91 ENTRY(R15B) \
92 ENTRY(SPL) \
93 ENTRY(BPL) \
94 ENTRY(SIL) \
95 ENTRY(DIL)
97 #define EA_BASES_16BIT \
98 ENTRY(BX_SI) \
99 ENTRY(BX_DI) \
100 ENTRY(BP_SI) \
101 ENTRY(BP_DI) \
102 ENTRY(SI) \
103 ENTRY(DI) \
104 ENTRY(BP) \
105 ENTRY(BX) \
106 ENTRY(R8W) \
107 ENTRY(R9W) \
108 ENTRY(R10W) \
109 ENTRY(R11W) \
110 ENTRY(R12W) \
111 ENTRY(R13W) \
112 ENTRY(R14W) \
113 ENTRY(R15W)
115 #define REGS_16BIT \
116 ENTRY(AX) \
117 ENTRY(CX) \
118 ENTRY(DX) \
119 ENTRY(BX) \
120 ENTRY(SP) \
121 ENTRY(BP) \
122 ENTRY(SI) \
123 ENTRY(DI) \
124 ENTRY(R8W) \
125 ENTRY(R9W) \
126 ENTRY(R10W) \
127 ENTRY(R11W) \
128 ENTRY(R12W) \
129 ENTRY(R13W) \
130 ENTRY(R14W) \
131 ENTRY(R15W)
133 #define EA_BASES_32BIT \
134 ENTRY(EAX) \
135 ENTRY(ECX) \
136 ENTRY(EDX) \
137 ENTRY(EBX) \
138 ENTRY(sib) \
139 ENTRY(EBP) \
140 ENTRY(ESI) \
141 ENTRY(EDI) \
142 ENTRY(R8D) \
143 ENTRY(R9D) \
144 ENTRY(R10D) \
145 ENTRY(R11D) \
146 ENTRY(R12D) \
147 ENTRY(R13D) \
148 ENTRY(R14D) \
149 ENTRY(R15D)
151 #define REGS_32BIT \
152 ENTRY(EAX) \
153 ENTRY(ECX) \
154 ENTRY(EDX) \
155 ENTRY(EBX) \
156 ENTRY(ESP) \
157 ENTRY(EBP) \
158 ENTRY(ESI) \
159 ENTRY(EDI) \
160 ENTRY(R8D) \
161 ENTRY(R9D) \
162 ENTRY(R10D) \
163 ENTRY(R11D) \
164 ENTRY(R12D) \
165 ENTRY(R13D) \
166 ENTRY(R14D) \
167 ENTRY(R15D)
169 #define EA_BASES_64BIT \
170 ENTRY(RAX) \
171 ENTRY(RCX) \
172 ENTRY(RDX) \
173 ENTRY(RBX) \
174 ENTRY(sib64) \
175 ENTRY(RBP) \
176 ENTRY(RSI) \
177 ENTRY(RDI) \
178 ENTRY(R8) \
179 ENTRY(R9) \
180 ENTRY(R10) \
181 ENTRY(R11) \
182 ENTRY(R12) \
183 ENTRY(R13) \
184 ENTRY(R14) \
185 ENTRY(R15)
187 #define REGS_64BIT \
188 ENTRY(RAX) \
189 ENTRY(RCX) \
190 ENTRY(RDX) \
191 ENTRY(RBX) \
192 ENTRY(RSP) \
193 ENTRY(RBP) \
194 ENTRY(RSI) \
195 ENTRY(RDI) \
196 ENTRY(R8) \
197 ENTRY(R9) \
198 ENTRY(R10) \
199 ENTRY(R11) \
200 ENTRY(R12) \
201 ENTRY(R13) \
202 ENTRY(R14) \
203 ENTRY(R15)
205 #define REGS_MMX \
206 ENTRY(MM0) \
207 ENTRY(MM1) \
208 ENTRY(MM2) \
209 ENTRY(MM3) \
210 ENTRY(MM4) \
211 ENTRY(MM5) \
212 ENTRY(MM6) \
213 ENTRY(MM7)
215 #define REGS_XMM \
216 ENTRY(XMM0) \
217 ENTRY(XMM1) \
218 ENTRY(XMM2) \
219 ENTRY(XMM3) \
220 ENTRY(XMM4) \
221 ENTRY(XMM5) \
222 ENTRY(XMM6) \
223 ENTRY(XMM7) \
224 ENTRY(XMM8) \
225 ENTRY(XMM9) \
226 ENTRY(XMM10) \
227 ENTRY(XMM11) \
228 ENTRY(XMM12) \
229 ENTRY(XMM13) \
230 ENTRY(XMM14) \
231 ENTRY(XMM15) \
232 ENTRY(XMM16) \
233 ENTRY(XMM17) \
234 ENTRY(XMM18) \
235 ENTRY(XMM19) \
236 ENTRY(XMM20) \
237 ENTRY(XMM21) \
238 ENTRY(XMM22) \
239 ENTRY(XMM23) \
240 ENTRY(XMM24) \
241 ENTRY(XMM25) \
242 ENTRY(XMM26) \
243 ENTRY(XMM27) \
244 ENTRY(XMM28) \
245 ENTRY(XMM29) \
246 ENTRY(XMM30) \
247 ENTRY(XMM31)
249 #define REGS_YMM \
250 ENTRY(YMM0) \
251 ENTRY(YMM1) \
252 ENTRY(YMM2) \
253 ENTRY(YMM3) \
254 ENTRY(YMM4) \
255 ENTRY(YMM5) \
256 ENTRY(YMM6) \
257 ENTRY(YMM7) \
258 ENTRY(YMM8) \
259 ENTRY(YMM9) \
260 ENTRY(YMM10) \
261 ENTRY(YMM11) \
262 ENTRY(YMM12) \
263 ENTRY(YMM13) \
264 ENTRY(YMM14) \
265 ENTRY(YMM15) \
266 ENTRY(YMM16) \
267 ENTRY(YMM17) \
268 ENTRY(YMM18) \
269 ENTRY(YMM19) \
270 ENTRY(YMM20) \
271 ENTRY(YMM21) \
272 ENTRY(YMM22) \
273 ENTRY(YMM23) \
274 ENTRY(YMM24) \
275 ENTRY(YMM25) \
276 ENTRY(YMM26) \
277 ENTRY(YMM27) \
278 ENTRY(YMM28) \
279 ENTRY(YMM29) \
280 ENTRY(YMM30) \
281 ENTRY(YMM31)
283 #define REGS_ZMM \
284 ENTRY(ZMM0) \
285 ENTRY(ZMM1) \
286 ENTRY(ZMM2) \
287 ENTRY(ZMM3) \
288 ENTRY(ZMM4) \
289 ENTRY(ZMM5) \
290 ENTRY(ZMM6) \
291 ENTRY(ZMM7) \
292 ENTRY(ZMM8) \
293 ENTRY(ZMM9) \
294 ENTRY(ZMM10) \
295 ENTRY(ZMM11) \
296 ENTRY(ZMM12) \
297 ENTRY(ZMM13) \
298 ENTRY(ZMM14) \
299 ENTRY(ZMM15) \
300 ENTRY(ZMM16) \
301 ENTRY(ZMM17) \
302 ENTRY(ZMM18) \
303 ENTRY(ZMM19) \
304 ENTRY(ZMM20) \
305 ENTRY(ZMM21) \
306 ENTRY(ZMM22) \
307 ENTRY(ZMM23) \
308 ENTRY(ZMM24) \
309 ENTRY(ZMM25) \
310 ENTRY(ZMM26) \
311 ENTRY(ZMM27) \
312 ENTRY(ZMM28) \
313 ENTRY(ZMM29) \
314 ENTRY(ZMM30) \
315 ENTRY(ZMM31)
317 #define REGS_MASKS \
318 ENTRY(K0) \
319 ENTRY(K1) \
320 ENTRY(K2) \
321 ENTRY(K3) \
322 ENTRY(K4) \
323 ENTRY(K5) \
324 ENTRY(K6) \
325 ENTRY(K7)
327 #define REGS_MASK_PAIRS \
328 ENTRY(K0_K1) \
329 ENTRY(K2_K3) \
330 ENTRY(K4_K5) \
331 ENTRY(K6_K7)
333 #define REGS_SEGMENT \
334 ENTRY(ES) \
335 ENTRY(CS) \
336 ENTRY(SS) \
337 ENTRY(DS) \
338 ENTRY(FS) \
339 ENTRY(GS)
341 #define REGS_DEBUG \
342 ENTRY(DR0) \
343 ENTRY(DR1) \
344 ENTRY(DR2) \
345 ENTRY(DR3) \
346 ENTRY(DR4) \
347 ENTRY(DR5) \
348 ENTRY(DR6) \
349 ENTRY(DR7) \
350 ENTRY(DR8) \
351 ENTRY(DR9) \
352 ENTRY(DR10) \
353 ENTRY(DR11) \
354 ENTRY(DR12) \
355 ENTRY(DR13) \
356 ENTRY(DR14) \
357 ENTRY(DR15)
359 #define REGS_CONTROL \
360 ENTRY(CR0) \
361 ENTRY(CR1) \
362 ENTRY(CR2) \
363 ENTRY(CR3) \
364 ENTRY(CR4) \
365 ENTRY(CR5) \
366 ENTRY(CR6) \
367 ENTRY(CR7) \
368 ENTRY(CR8) \
369 ENTRY(CR9) \
370 ENTRY(CR10) \
371 ENTRY(CR11) \
372 ENTRY(CR12) \
373 ENTRY(CR13) \
374 ENTRY(CR14) \
375 ENTRY(CR15)
377 #define REGS_BOUND \
378 ENTRY(BND0) \
379 ENTRY(BND1) \
380 ENTRY(BND2) \
381 ENTRY(BND3)
383 #define ALL_EA_BASES \
384 EA_BASES_16BIT \
385 EA_BASES_32BIT \
386 EA_BASES_64BIT
388 #define ALL_SIB_BASES \
389 REGS_32BIT \
390 REGS_64BIT
392 #define ALL_REGS \
393 REGS_8BIT \
394 REGS_16BIT \
395 REGS_32BIT \
396 REGS_64BIT \
397 REGS_MMX \
398 REGS_XMM \
399 REGS_YMM \
400 REGS_ZMM \
401 REGS_MASKS \
402 REGS_MASK_PAIRS \
403 REGS_SEGMENT \
404 REGS_DEBUG \
405 REGS_CONTROL \
406 REGS_BOUND \
407 ENTRY(RIP)
409 /// All possible values of the base field for effective-address
410 /// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
411 /// We distinguish between bases (EA_BASE_*) and registers that just happen
412 /// to be referred to when Mod == 0b11 (EA_REG_*).
413 enum EABase {
414 EA_BASE_NONE,
415 #define ENTRY(x) EA_BASE_##x,
416 ALL_EA_BASES
417 #undef ENTRY
418 #define ENTRY(x) EA_REG_##x,
419 ALL_REGS
420 #undef ENTRY
421 EA_max
424 /// All possible values of the SIB index field.
425 /// borrows entries from ALL_EA_BASES with the special case that
426 /// sib is synonymous with NONE.
427 /// Vector SIB: index can be XMM or YMM.
428 enum SIBIndex {
429 SIB_INDEX_NONE,
430 #define ENTRY(x) SIB_INDEX_##x,
431 ALL_EA_BASES
432 REGS_XMM
433 REGS_YMM
434 REGS_ZMM
435 #undef ENTRY
436 SIB_INDEX_max
439 /// All possible values of the SIB base field.
440 enum SIBBase {
441 SIB_BASE_NONE,
442 #define ENTRY(x) SIB_BASE_##x,
443 ALL_SIB_BASES
444 #undef ENTRY
445 SIB_BASE_max
448 /// Possible displacement types for effective-address computations.
449 typedef enum {
450 EA_DISP_NONE,
451 EA_DISP_8,
452 EA_DISP_16,
453 EA_DISP_32
454 } EADisplacement;
456 /// All possible values of the reg field in the ModR/M byte.
457 enum Reg {
458 #define ENTRY(x) MODRM_REG_##x,
459 ALL_REGS
460 #undef ENTRY
461 MODRM_REG_max
464 /// All possible segment overrides.
465 enum SegmentOverride {
466 SEG_OVERRIDE_NONE,
467 SEG_OVERRIDE_CS,
468 SEG_OVERRIDE_SS,
469 SEG_OVERRIDE_DS,
470 SEG_OVERRIDE_ES,
471 SEG_OVERRIDE_FS,
472 SEG_OVERRIDE_GS,
473 SEG_OVERRIDE_max
476 /// Possible values for the VEX.m-mmmm field
477 enum VEXLeadingOpcodeByte {
478 VEX_LOB_0F = 0x1,
479 VEX_LOB_0F38 = 0x2,
480 VEX_LOB_0F3A = 0x3
483 enum XOPMapSelect {
484 XOP_MAP_SELECT_8 = 0x8,
485 XOP_MAP_SELECT_9 = 0x9,
486 XOP_MAP_SELECT_A = 0xA
489 /// Possible values for the VEX.pp/EVEX.pp field
490 enum VEXPrefixCode {
491 VEX_PREFIX_NONE = 0x0,
492 VEX_PREFIX_66 = 0x1,
493 VEX_PREFIX_F3 = 0x2,
494 VEX_PREFIX_F2 = 0x3
497 enum VectorExtensionType {
498 TYPE_NO_VEX_XOP = 0x0,
499 TYPE_VEX_2B = 0x1,
500 TYPE_VEX_3B = 0x2,
501 TYPE_EVEX = 0x3,
502 TYPE_XOP = 0x4
505 /// Type for the byte reader that the consumer must provide to
506 /// the decoder. Reads a single byte from the instruction's address space.
507 /// \param arg A baton that the consumer can associate with any internal
508 /// state that it needs.
509 /// \param byte A pointer to a single byte in memory that should be set to
510 /// contain the value at address.
511 /// \param address The address in the instruction's address space that should
512 /// be read from.
513 /// \return -1 if the byte cannot be read for any reason; 0 otherwise.
514 typedef int (*byteReader_t)(const void *arg, uint8_t *byte, uint64_t address);
516 /// Type for the logging function that the consumer can provide to
517 /// get debugging output from the decoder.
518 /// \param arg A baton that the consumer can associate with any internal
519 /// state that it needs.
520 /// \param log A string that contains the message. Will be reused after
521 /// the logger returns.
522 typedef void (*dlog_t)(void *arg, const char *log);
524 /// The specification for how to extract and interpret a full instruction and
525 /// its operands.
526 struct InstructionSpecifier {
527 uint16_t operands;
530 /// The x86 internal instruction, which is produced by the decoder.
531 struct InternalInstruction {
532 // Reader interface (C)
533 byteReader_t reader;
534 // Opaque value passed to the reader
535 const void* readerArg;
536 // The address of the next byte to read via the reader
537 uint64_t readerCursor;
539 // Logger interface (C)
540 dlog_t dlog;
541 // Opaque value passed to the logger
542 void* dlogArg;
544 // General instruction information
546 // The mode to disassemble for (64-bit, protected, real)
547 DisassemblerMode mode;
548 // The start of the instruction, usable with the reader
549 uint64_t startLocation;
550 // The length of the instruction, in bytes
551 size_t length;
553 // Prefix state
555 // The possible mandatory prefix
556 uint8_t mandatoryPrefix;
557 // The value of the vector extension prefix(EVEX/VEX/XOP), if present
558 uint8_t vectorExtensionPrefix[4];
559 // The type of the vector extension prefix
560 VectorExtensionType vectorExtensionType;
561 // The value of the REX prefix, if present
562 uint8_t rexPrefix;
563 // The segment override type
564 SegmentOverride segmentOverride;
565 // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease
566 bool xAcquireRelease;
568 // Address-size override
569 bool hasAdSize;
570 // Operand-size override
571 bool hasOpSize;
572 // Lock prefix
573 bool hasLockPrefix;
574 // The repeat prefix if any
575 uint8_t repeatPrefix;
577 // Sizes of various critical pieces of data, in bytes
578 uint8_t registerSize;
579 uint8_t addressSize;
580 uint8_t displacementSize;
581 uint8_t immediateSize;
583 // Offsets from the start of the instruction to the pieces of data, which is
584 // needed to find relocation entries for adding symbolic operands.
585 uint8_t displacementOffset;
586 uint8_t immediateOffset;
588 // opcode state
590 // The last byte of the opcode, not counting any ModR/M extension
591 uint8_t opcode;
593 // decode state
595 // The type of opcode, used for indexing into the array of decode tables
596 OpcodeType opcodeType;
597 // The instruction ID, extracted from the decode table
598 uint16_t instructionID;
599 // The specifier for the instruction, from the instruction info table
600 const InstructionSpecifier *spec;
602 // state for additional bytes, consumed during operand decode. Pattern:
603 // consumed___ indicates that the byte was already consumed and does not
604 // need to be consumed again.
606 // The VEX.vvvv field, which contains a third register operand for some AVX
607 // instructions.
608 Reg vvvv;
610 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
611 Reg writemask;
613 // The ModR/M byte, which contains most register operands and some portion of
614 // all memory operands.
615 bool consumedModRM;
616 uint8_t modRM;
618 // The SIB byte, used for more complex 32- or 64-bit memory operands
619 bool consumedSIB;
620 uint8_t sib;
622 // The displacement, used for memory operands
623 bool consumedDisplacement;
624 int32_t displacement;
626 // Immediates. There can be two in some cases
627 uint8_t numImmediatesConsumed;
628 uint8_t numImmediatesTranslated;
629 uint64_t immediates[2];
631 // A register or immediate operand encoded into the opcode
632 Reg opcodeRegister;
634 // Portions of the ModR/M byte
636 // These fields determine the allowable values for the ModR/M fields, which
637 // depend on operand and address widths.
638 EABase eaRegBase;
639 Reg regBase;
641 // The Mod and R/M fields can encode a base for an effective address, or a
642 // register. These are separated into two fields here.
643 EABase eaBase;
644 EADisplacement eaDisplacement;
645 // The reg field always encodes a register
646 Reg reg;
648 // SIB state
649 SIBIndex sibIndexBase;
650 SIBIndex sibIndex;
651 uint8_t sibScale;
652 SIBBase sibBase;
654 // Embedded rounding control.
655 uint8_t RC;
657 ArrayRef<OperandSpecifier> operands;
660 /// Decode one instruction and store the decoding results in
661 /// a buffer provided by the consumer.
662 /// \param insn The buffer to store the instruction in. Allocated by the
663 /// consumer.
664 /// \param reader The byteReader_t for the bytes to be read.
665 /// \param readerArg An argument to pass to the reader for storing context
666 /// specific to the consumer. May be NULL.
667 /// \param logger The dlog_t to be used in printing status messages from the
668 /// disassembler. May be NULL.
669 /// \param loggerArg An argument to pass to the logger for storing context
670 /// specific to the logger. May be NULL.
671 /// \param startLoc The address (in the reader's address space) of the first
672 /// byte in the instruction.
673 /// \param mode The mode (16-bit, 32-bit, 64-bit) to decode in.
674 /// \return Nonzero if there was an error during decode, 0 otherwise.
675 int decodeInstruction(InternalInstruction *insn,
676 byteReader_t reader,
677 const void *readerArg,
678 dlog_t logger,
679 void *loggerArg,
680 const void *miiArg,
681 uint64_t startLoc,
682 DisassemblerMode mode);
684 /// Print a message to debugs()
685 /// \param file The name of the file printing the debug message.
686 /// \param line The line number that printed the debug message.
687 /// \param s The message to print.
688 void Debug(const char *file, unsigned line, const char *s);
690 StringRef GetInstrName(unsigned Opcode, const void *mii);
692 } // namespace X86Disassembler
693 } // namespace llvm
695 #endif