1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 // This file is responsible for the frame pointer elimination optimization
13 //===----------------------------------------------------------------------===//
15 #include "X86RegisterInfo.h"
16 #include "X86FrameLowering.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetFrameLowering.h"
26 #include "llvm/CodeGen/TargetInstrInfo.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
37 #define GET_REGINFO_TARGET_DESC
38 #include "X86GenRegisterInfo.inc"
41 EnableBasePointer("x86-use-base-pointer", cl::Hidden
, cl::init(true),
42 cl::desc("Enable use of a base pointer for complex stack frames"));
44 X86RegisterInfo::X86RegisterInfo(const Triple
&TT
)
45 : X86GenRegisterInfo((TT
.isArch64Bit() ? X86::RIP
: X86::EIP
),
46 X86_MC::getDwarfRegFlavour(TT
, false),
47 X86_MC::getDwarfRegFlavour(TT
, true),
48 (TT
.isArch64Bit() ? X86::RIP
: X86::EIP
)) {
49 X86_MC::initLLVMToSEHAndCVRegMapping(this);
51 // Cache some information.
52 Is64Bit
= TT
.isArch64Bit();
53 IsWin64
= Is64Bit
&& TT
.isOSWindows();
55 // Use a callee-saved register as the base pointer. These registers must
56 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
57 // requires GOT in the EBX register before function calls via PLT GOT pointer.
60 // This matches the simplified 32-bit pointer code in the data layout
62 // FIXME: Should use the data layout?
63 bool Use64BitReg
= TT
.getEnvironment() != Triple::GNUX32
;
64 StackPtr
= Use64BitReg
? X86::RSP
: X86::ESP
;
65 FramePtr
= Use64BitReg
? X86::RBP
: X86::EBP
;
66 BasePtr
= Use64BitReg
? X86::RBX
: X86::EBX
;
76 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction
&MF
) const {
77 // ExecutionDomainFix, BreakFalseDeps and PostRAScheduler require liveness.
82 X86RegisterInfo::getSEHRegNum(unsigned i
) const {
83 return getEncodingValue(i
);
86 const TargetRegisterClass
*
87 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass
*RC
,
89 // The sub_8bit sub-register index is more constrained in 32-bit mode.
90 // It behaves just like the sub_8bit_hi index.
91 if (!Is64Bit
&& Idx
== X86::sub_8bit
)
92 Idx
= X86::sub_8bit_hi
;
94 // Forward to TableGen's default version.
95 return X86GenRegisterInfo::getSubClassWithSubReg(RC
, Idx
);
98 const TargetRegisterClass
*
99 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass
*A
,
100 const TargetRegisterClass
*B
,
101 unsigned SubIdx
) const {
102 // The sub_8bit sub-register index is more constrained in 32-bit mode.
103 if (!Is64Bit
&& SubIdx
== X86::sub_8bit
) {
104 A
= X86GenRegisterInfo::getSubClassWithSubReg(A
, X86::sub_8bit_hi
);
108 return X86GenRegisterInfo::getMatchingSuperRegClass(A
, B
, SubIdx
);
111 const TargetRegisterClass
*
112 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass
*RC
,
113 const MachineFunction
&MF
) const {
114 // Don't allow super-classes of GR8_NOREX. This class is only used after
115 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
116 // to the full GR8 register class in 64-bit mode, so we cannot allow the
117 // reigster class inflation.
119 // The GR8_NOREX class is always used in a way that won't be constrained to a
120 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
122 if (RC
== &X86::GR8_NOREXRegClass
)
125 const X86Subtarget
&Subtarget
= MF
.getSubtarget
<X86Subtarget
>();
127 const TargetRegisterClass
*Super
= RC
;
128 TargetRegisterClass::sc_iterator I
= RC
->getSuperClasses();
130 switch (Super
->getID()) {
131 case X86::FR32RegClassID
:
132 case X86::FR64RegClassID
:
133 // If AVX-512 isn't supported we should only inflate to these classes.
134 if (!Subtarget
.hasAVX512() &&
135 getRegSizeInBits(*Super
) == getRegSizeInBits(*RC
))
138 case X86::VR128RegClassID
:
139 case X86::VR256RegClassID
:
140 // If VLX isn't supported we should only inflate to these classes.
141 if (!Subtarget
.hasVLX() &&
142 getRegSizeInBits(*Super
) == getRegSizeInBits(*RC
))
145 case X86::VR128XRegClassID
:
146 case X86::VR256XRegClassID
:
147 // If VLX isn't support we shouldn't inflate to these classes.
148 if (Subtarget
.hasVLX() &&
149 getRegSizeInBits(*Super
) == getRegSizeInBits(*RC
))
152 case X86::FR32XRegClassID
:
153 case X86::FR64XRegClassID
:
154 // If AVX-512 isn't support we shouldn't inflate to these classes.
155 if (Subtarget
.hasAVX512() &&
156 getRegSizeInBits(*Super
) == getRegSizeInBits(*RC
))
159 case X86::GR8RegClassID
:
160 case X86::GR16RegClassID
:
161 case X86::GR32RegClassID
:
162 case X86::GR64RegClassID
:
163 case X86::RFP32RegClassID
:
164 case X86::RFP64RegClassID
:
165 case X86::RFP80RegClassID
:
166 case X86::VR512_0_15RegClassID
:
167 case X86::VR512RegClassID
:
168 // Don't return a super-class that would shrink the spill size.
169 // That can happen with the vector and float classes.
170 if (getRegSizeInBits(*Super
) == getRegSizeInBits(*RC
))
178 const TargetRegisterClass
*
179 X86RegisterInfo::getPointerRegClass(const MachineFunction
&MF
,
180 unsigned Kind
) const {
181 const X86Subtarget
&Subtarget
= MF
.getSubtarget
<X86Subtarget
>();
183 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
184 case 0: // Normal GPRs.
185 if (Subtarget
.isTarget64BitLP64())
186 return &X86::GR64RegClass
;
187 // If the target is 64bit but we have been told to use 32bit addresses,
188 // we can still use 64-bit register as long as we know the high bits
190 // Reflect that in the returned register class.
192 // When the target also allows 64-bit frame pointer and we do have a
193 // frame, this is fine to use it for the address accesses as well.
194 const X86FrameLowering
*TFI
= getFrameLowering(MF
);
195 return TFI
->hasFP(MF
) && TFI
->Uses64BitFramePtr
196 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
197 : &X86::LOW32_ADDR_ACCESSRegClass
;
199 return &X86::GR32RegClass
;
200 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
201 if (Subtarget
.isTarget64BitLP64())
202 return &X86::GR64_NOSPRegClass
;
203 // NOSP does not contain RIP, so no special case here.
204 return &X86::GR32_NOSPRegClass
;
205 case 2: // NOREX GPRs.
206 if (Subtarget
.isTarget64BitLP64())
207 return &X86::GR64_NOREXRegClass
;
208 return &X86::GR32_NOREXRegClass
;
209 case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
210 if (Subtarget
.isTarget64BitLP64())
211 return &X86::GR64_NOREX_NOSPRegClass
;
212 // NOSP does not contain RIP, so no special case here.
213 return &X86::GR32_NOREX_NOSPRegClass
;
214 case 4: // Available for tailcall (not callee-saved GPRs).
215 return getGPRsForTailCall(MF
);
219 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass
*DefRC
,
221 const TargetRegisterClass
*SrcRC
,
222 unsigned SrcSubReg
) const {
223 // Prevent rewriting a copy where the destination size is larger than the
224 // input size. See PR41619.
225 // FIXME: Should this be factored into the base implementation somehow.
226 if (DefRC
->hasSuperClassEq(&X86::GR64RegClass
) && DefSubReg
== 0 &&
227 SrcRC
->hasSuperClassEq(&X86::GR64RegClass
) && SrcSubReg
== X86::sub_32bit
)
230 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC
, DefSubReg
,
234 const TargetRegisterClass
*
235 X86RegisterInfo::getGPRsForTailCall(const MachineFunction
&MF
) const {
236 const Function
&F
= MF
.getFunction();
237 if (IsWin64
|| (F
.getCallingConv() == CallingConv::Win64
))
238 return &X86::GR64_TCW64RegClass
;
240 return &X86::GR64_TCRegClass
;
242 bool hasHipeCC
= (F
.getCallingConv() == CallingConv::HiPE
);
244 return &X86::GR32RegClass
;
245 return &X86::GR32_TCRegClass
;
248 const TargetRegisterClass
*
249 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass
*RC
) const {
250 if (RC
== &X86::CCRRegClass
) {
252 return &X86::GR64RegClass
;
254 return &X86::GR32RegClass
;
260 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass
*RC
,
261 MachineFunction
&MF
) const {
262 const X86FrameLowering
*TFI
= getFrameLowering(MF
);
264 unsigned FPDiff
= TFI
->hasFP(MF
) ? 1 : 0;
265 switch (RC
->getID()) {
268 case X86::GR32RegClassID
:
270 case X86::GR64RegClassID
:
272 case X86::VR128RegClassID
:
273 return Is64Bit
? 10 : 4;
274 case X86::VR64RegClassID
:
280 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF
) const {
281 assert(MF
&& "MachineFunction required");
283 const X86Subtarget
&Subtarget
= MF
->getSubtarget
<X86Subtarget
>();
284 const Function
&F
= MF
->getFunction();
285 bool HasSSE
= Subtarget
.hasSSE1();
286 bool HasAVX
= Subtarget
.hasAVX();
287 bool HasAVX512
= Subtarget
.hasAVX512();
288 bool CallsEHReturn
= MF
->callsEHReturn();
290 CallingConv::ID CC
= F
.getCallingConv();
292 // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
293 // convention because it has the CSR list.
294 if (MF
->getFunction().hasFnAttribute("no_caller_saved_registers"))
295 CC
= CallingConv::X86_INTR
;
298 case CallingConv::GHC
:
299 case CallingConv::HiPE
:
300 return CSR_NoRegs_SaveList
;
301 case CallingConv::AnyReg
:
303 return CSR_64_AllRegs_AVX_SaveList
;
304 return CSR_64_AllRegs_SaveList
;
305 case CallingConv::PreserveMost
:
306 return CSR_64_RT_MostRegs_SaveList
;
307 case CallingConv::PreserveAll
:
309 return CSR_64_RT_AllRegs_AVX_SaveList
;
310 return CSR_64_RT_AllRegs_SaveList
;
311 case CallingConv::CXX_FAST_TLS
:
313 return MF
->getInfo
<X86MachineFunctionInfo
>()->isSplitCSR() ?
314 CSR_64_CXX_TLS_Darwin_PE_SaveList
: CSR_64_TLS_Darwin_SaveList
;
316 case CallingConv::Intel_OCL_BI
: {
317 if (HasAVX512
&& IsWin64
)
318 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
319 if (HasAVX512
&& Is64Bit
)
320 return CSR_64_Intel_OCL_BI_AVX512_SaveList
;
321 if (HasAVX
&& IsWin64
)
322 return CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
323 if (HasAVX
&& Is64Bit
)
324 return CSR_64_Intel_OCL_BI_AVX_SaveList
;
325 if (!HasAVX
&& !IsWin64
&& Is64Bit
)
326 return CSR_64_Intel_OCL_BI_SaveList
;
329 case CallingConv::HHVM
:
330 return CSR_64_HHVM_SaveList
;
331 case CallingConv::X86_RegCall
:
334 return (HasSSE
? CSR_Win64_RegCall_SaveList
:
335 CSR_Win64_RegCall_NoSSE_SaveList
);
337 return (HasSSE
? CSR_SysV64_RegCall_SaveList
:
338 CSR_SysV64_RegCall_NoSSE_SaveList
);
341 return (HasSSE
? CSR_32_RegCall_SaveList
:
342 CSR_32_RegCall_NoSSE_SaveList
);
344 case CallingConv::Cold
:
346 return CSR_64_MostRegs_SaveList
;
348 case CallingConv::Win64
:
350 return CSR_Win64_NoSSE_SaveList
;
351 return CSR_Win64_SaveList
;
352 case CallingConv::X86_64_SysV
:
354 return CSR_64EHRet_SaveList
;
355 return CSR_64_SaveList
;
356 case CallingConv::X86_INTR
:
359 return CSR_64_AllRegs_AVX512_SaveList
;
361 return CSR_64_AllRegs_AVX_SaveList
;
363 return CSR_64_AllRegs_SaveList
;
364 return CSR_64_AllRegs_NoSSE_SaveList
;
367 return CSR_32_AllRegs_AVX512_SaveList
;
369 return CSR_32_AllRegs_AVX_SaveList
;
371 return CSR_32_AllRegs_SSE_SaveList
;
372 return CSR_32_AllRegs_SaveList
;
379 bool IsSwiftCC
= Subtarget
.getTargetLowering()->supportSwiftError() &&
380 F
.getAttributes().hasAttrSomewhere(Attribute::SwiftError
);
382 return IsWin64
? CSR_Win64_SwiftError_SaveList
383 : CSR_64_SwiftError_SaveList
;
386 return HasSSE
? CSR_Win64_SaveList
: CSR_Win64_NoSSE_SaveList
;
388 return CSR_64EHRet_SaveList
;
389 return CSR_64_SaveList
;
392 return CallsEHReturn
? CSR_32EHRet_SaveList
: CSR_32_SaveList
;
395 const MCPhysReg
*X86RegisterInfo::getCalleeSavedRegsViaCopy(
396 const MachineFunction
*MF
) const {
397 assert(MF
&& "Invalid MachineFunction pointer.");
398 if (MF
->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS
&&
399 MF
->getInfo
<X86MachineFunctionInfo
>()->isSplitCSR())
400 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList
;
405 X86RegisterInfo::getCallPreservedMask(const MachineFunction
&MF
,
406 CallingConv::ID CC
) const {
407 const X86Subtarget
&Subtarget
= MF
.getSubtarget
<X86Subtarget
>();
408 bool HasSSE
= Subtarget
.hasSSE1();
409 bool HasAVX
= Subtarget
.hasAVX();
410 bool HasAVX512
= Subtarget
.hasAVX512();
413 case CallingConv::GHC
:
414 case CallingConv::HiPE
:
415 return CSR_NoRegs_RegMask
;
416 case CallingConv::AnyReg
:
418 return CSR_64_AllRegs_AVX_RegMask
;
419 return CSR_64_AllRegs_RegMask
;
420 case CallingConv::PreserveMost
:
421 return CSR_64_RT_MostRegs_RegMask
;
422 case CallingConv::PreserveAll
:
424 return CSR_64_RT_AllRegs_AVX_RegMask
;
425 return CSR_64_RT_AllRegs_RegMask
;
426 case CallingConv::CXX_FAST_TLS
:
428 return CSR_64_TLS_Darwin_RegMask
;
430 case CallingConv::Intel_OCL_BI
: {
431 if (HasAVX512
&& IsWin64
)
432 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask
;
433 if (HasAVX512
&& Is64Bit
)
434 return CSR_64_Intel_OCL_BI_AVX512_RegMask
;
435 if (HasAVX
&& IsWin64
)
436 return CSR_Win64_Intel_OCL_BI_AVX_RegMask
;
437 if (HasAVX
&& Is64Bit
)
438 return CSR_64_Intel_OCL_BI_AVX_RegMask
;
439 if (!HasAVX
&& !IsWin64
&& Is64Bit
)
440 return CSR_64_Intel_OCL_BI_RegMask
;
443 case CallingConv::HHVM
:
444 return CSR_64_HHVM_RegMask
;
445 case CallingConv::X86_RegCall
:
448 return (HasSSE
? CSR_Win64_RegCall_RegMask
:
449 CSR_Win64_RegCall_NoSSE_RegMask
);
451 return (HasSSE
? CSR_SysV64_RegCall_RegMask
:
452 CSR_SysV64_RegCall_NoSSE_RegMask
);
455 return (HasSSE
? CSR_32_RegCall_RegMask
:
456 CSR_32_RegCall_NoSSE_RegMask
);
458 case CallingConv::Cold
:
460 return CSR_64_MostRegs_RegMask
;
462 case CallingConv::Win64
:
463 return CSR_Win64_RegMask
;
464 case CallingConv::X86_64_SysV
:
465 return CSR_64_RegMask
;
466 case CallingConv::X86_INTR
:
469 return CSR_64_AllRegs_AVX512_RegMask
;
471 return CSR_64_AllRegs_AVX_RegMask
;
473 return CSR_64_AllRegs_RegMask
;
474 return CSR_64_AllRegs_NoSSE_RegMask
;
477 return CSR_32_AllRegs_AVX512_RegMask
;
479 return CSR_32_AllRegs_AVX_RegMask
;
481 return CSR_32_AllRegs_SSE_RegMask
;
482 return CSR_32_AllRegs_RegMask
;
488 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
491 const Function
&F
= MF
.getFunction();
492 bool IsSwiftCC
= Subtarget
.getTargetLowering()->supportSwiftError() &&
493 F
.getAttributes().hasAttrSomewhere(Attribute::SwiftError
);
495 return IsWin64
? CSR_Win64_SwiftError_RegMask
: CSR_64_SwiftError_RegMask
;
496 return IsWin64
? CSR_Win64_RegMask
: CSR_64_RegMask
;
499 return CSR_32_RegMask
;
503 X86RegisterInfo::getNoPreservedMask() const {
504 return CSR_NoRegs_RegMask
;
507 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
508 return CSR_64_TLS_Darwin_RegMask
;
511 BitVector
X86RegisterInfo::getReservedRegs(const MachineFunction
&MF
) const {
512 BitVector
Reserved(getNumRegs());
513 const X86FrameLowering
*TFI
= getFrameLowering(MF
);
515 // Set the floating point control register as reserved.
516 Reserved
.set(X86::FPCW
);
518 // Set the stack-pointer register and its aliases as reserved.
519 for (MCSubRegIterator
I(X86::RSP
, this, /*IncludeSelf=*/true); I
.isValid();
523 // Set the Shadow Stack Pointer as reserved.
524 Reserved
.set(X86::SSP
);
526 // Set the instruction pointer register and its aliases as reserved.
527 for (MCSubRegIterator
I(X86::RIP
, this, /*IncludeSelf=*/true); I
.isValid();
531 // Set the frame-pointer register and its aliases as reserved if needed.
532 if (TFI
->hasFP(MF
)) {
533 for (MCSubRegIterator
I(X86::RBP
, this, /*IncludeSelf=*/true); I
.isValid();
538 // Set the base-pointer register and its aliases as reserved if needed.
539 if (hasBasePointer(MF
)) {
540 CallingConv::ID CC
= MF
.getFunction().getCallingConv();
541 const uint32_t *RegMask
= getCallPreservedMask(MF
, CC
);
542 if (MachineOperand::clobbersPhysReg(RegMask
, getBaseRegister()))
544 "Stack realignment in presence of dynamic allocas is not supported with"
545 "this calling convention.");
547 Register BasePtr
= getX86SubSuperRegister(getBaseRegister(), 64);
548 for (MCSubRegIterator
I(BasePtr
, this, /*IncludeSelf=*/true);
553 // Mark the segment registers as reserved.
554 Reserved
.set(X86::CS
);
555 Reserved
.set(X86::SS
);
556 Reserved
.set(X86::DS
);
557 Reserved
.set(X86::ES
);
558 Reserved
.set(X86::FS
);
559 Reserved
.set(X86::GS
);
561 // Mark the floating point stack registers as reserved.
562 for (unsigned n
= 0; n
!= 8; ++n
)
563 Reserved
.set(X86::ST0
+ n
);
565 // Reserve the registers that only exist in 64-bit mode.
567 // These 8-bit registers are part of the x86-64 extension even though their
568 // super-registers are old 32-bits.
569 Reserved
.set(X86::SIL
);
570 Reserved
.set(X86::DIL
);
571 Reserved
.set(X86::BPL
);
572 Reserved
.set(X86::SPL
);
573 Reserved
.set(X86::SIH
);
574 Reserved
.set(X86::DIH
);
575 Reserved
.set(X86::BPH
);
576 Reserved
.set(X86::SPH
);
578 for (unsigned n
= 0; n
!= 8; ++n
) {
580 for (MCRegAliasIterator
AI(X86::R8
+ n
, this, true); AI
.isValid(); ++AI
)
584 for (MCRegAliasIterator
AI(X86::XMM8
+ n
, this, true); AI
.isValid(); ++AI
)
588 if (!Is64Bit
|| !MF
.getSubtarget
<X86Subtarget
>().hasAVX512()) {
589 for (unsigned n
= 16; n
!= 32; ++n
) {
590 for (MCRegAliasIterator
AI(X86::XMM0
+ n
, this, true); AI
.isValid(); ++AI
)
595 assert(checkAllSuperRegsMarked(Reserved
,
596 {X86::SIL
, X86::DIL
, X86::BPL
, X86::SPL
,
597 X86::SIH
, X86::DIH
, X86::BPH
, X86::SPH
}));
601 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask
) const {
602 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
603 // because the calling convention defines the EFLAGS register as NOT
606 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
607 // an assert to track this and clear the register afterwards to avoid
608 // unnecessary crashes during release builds.
609 assert(!(Mask
[X86::EFLAGS
/ 32] & (1U << (X86::EFLAGS
% 32))) &&
610 "EFLAGS are not live-out from a patchpoint.");
612 // Also clean other registers that don't need preserving (IP).
613 for (auto Reg
: {X86::EFLAGS
, X86::RIP
, X86::EIP
, X86::IP
})
614 Mask
[Reg
/ 32] &= ~(1U << (Reg
% 32));
617 //===----------------------------------------------------------------------===//
618 // Stack Frame Processing methods
619 //===----------------------------------------------------------------------===//
621 static bool CantUseSP(const MachineFrameInfo
&MFI
) {
622 return MFI
.hasVarSizedObjects() || MFI
.hasOpaqueSPAdjustment();
625 bool X86RegisterInfo::hasBasePointer(const MachineFunction
&MF
) const {
626 const MachineFrameInfo
&MFI
= MF
.getFrameInfo();
628 if (!EnableBasePointer
)
631 // When we need stack realignment, we can't address the stack from the frame
632 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
633 // can't address variables from the stack pointer. MS inline asm can
634 // reference locals while also adjusting the stack pointer. When we can't
635 // use both the SP and the FP, we need a separate base pointer register.
636 bool CantUseFP
= needsStackRealignment(MF
);
637 return CantUseFP
&& CantUseSP(MFI
);
640 bool X86RegisterInfo::canRealignStack(const MachineFunction
&MF
) const {
641 if (!TargetRegisterInfo::canRealignStack(MF
))
644 const MachineFrameInfo
&MFI
= MF
.getFrameInfo();
645 const MachineRegisterInfo
*MRI
= &MF
.getRegInfo();
647 // Stack realignment requires a frame pointer. If we already started
648 // register allocation with frame pointer elimination, it is too late now.
649 if (!MRI
->canReserveReg(FramePtr
))
652 // If a base pointer is necessary. Check that it isn't too late to reserve
655 return MRI
->canReserveReg(BasePtr
);
659 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction
&MF
,
660 unsigned Reg
, int &FrameIdx
) const {
661 // Since X86 defines assignCalleeSavedSpillSlots which always return true
662 // this function neither used nor tested.
663 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
666 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
667 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
668 // TODO: In this case we should be really trying first to entirely eliminate
669 // this instruction which is a plain copy.
670 static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II
) {
671 MachineInstr
&MI
= *II
;
672 unsigned Opc
= II
->getOpcode();
673 // Check if this is a LEA of the form 'lea (%esp), %ebx'
674 if ((Opc
!= X86::LEA32r
&& Opc
!= X86::LEA64r
&& Opc
!= X86::LEA64_32r
) ||
675 MI
.getOperand(2).getImm() != 1 ||
676 MI
.getOperand(3).getReg() != X86::NoRegister
||
677 MI
.getOperand(4).getImm() != 0 ||
678 MI
.getOperand(5).getReg() != X86::NoRegister
)
680 Register BasePtr
= MI
.getOperand(1).getReg();
681 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
682 // be replaced with a 32-bit operand MOV which will zero extend the upper
683 // 32-bits of the super register.
684 if (Opc
== X86::LEA64_32r
)
685 BasePtr
= getX86SubSuperRegister(BasePtr
, 32);
686 Register NewDestReg
= MI
.getOperand(0).getReg();
687 const X86InstrInfo
*TII
=
688 MI
.getParent()->getParent()->getSubtarget
<X86Subtarget
>().getInstrInfo();
689 TII
->copyPhysReg(*MI
.getParent(), II
, MI
.getDebugLoc(), NewDestReg
, BasePtr
,
690 MI
.getOperand(1).isKill());
691 MI
.eraseFromParent();
695 static bool isFuncletReturnInstr(MachineInstr
&MI
) {
696 switch (MI
.getOpcode()) {
698 case X86::CLEANUPRET
:
703 llvm_unreachable("impossible");
707 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II
,
708 int SPAdj
, unsigned FIOperandNum
,
709 RegScavenger
*RS
) const {
710 MachineInstr
&MI
= *II
;
711 MachineBasicBlock
&MBB
= *MI
.getParent();
712 MachineFunction
&MF
= *MBB
.getParent();
713 MachineBasicBlock::iterator MBBI
= MBB
.getFirstTerminator();
714 bool IsEHFuncletEpilogue
= MBBI
== MBB
.end() ? false
715 : isFuncletReturnInstr(*MBBI
);
716 const X86FrameLowering
*TFI
= getFrameLowering(MF
);
717 int FrameIndex
= MI
.getOperand(FIOperandNum
).getIndex();
719 // Determine base register and offset.
723 assert((!needsStackRealignment(MF
) ||
724 MF
.getFrameInfo().isFixedObjectIndex(FrameIndex
)) &&
725 "Return instruction can only reference SP relative frame objects");
726 FIOffset
= TFI
->getFrameIndexReferenceSP(MF
, FrameIndex
, BasePtr
, 0);
727 } else if (TFI
->Is64Bit
&& (MBB
.isEHFuncletEntry() || IsEHFuncletEpilogue
)) {
728 FIOffset
= TFI
->getWin64EHFrameIndexRef(MF
, FrameIndex
, BasePtr
);
730 FIOffset
= TFI
->getFrameIndexReference(MF
, FrameIndex
, BasePtr
);
733 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
734 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
735 // offset is from the traditional base pointer location. On 64-bit, the
736 // offset is from the SP at the end of the prologue, not the FP location. This
737 // matches the behavior of llvm.frameaddress.
738 unsigned Opc
= MI
.getOpcode();
739 if (Opc
== TargetOpcode::LOCAL_ESCAPE
) {
740 MachineOperand
&FI
= MI
.getOperand(FIOperandNum
);
741 FI
.ChangeToImmediate(FIOffset
);
745 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
746 // register as source operand, semantic is the same and destination is
747 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
748 // Don't change BasePtr since it is used later for stack adjustment.
749 Register MachineBasePtr
= BasePtr
;
750 if (Opc
== X86::LEA64_32r
&& X86::GR32RegClass
.contains(BasePtr
))
751 MachineBasePtr
= getX86SubSuperRegister(BasePtr
, 64);
753 // This must be part of a four operand memory reference. Replace the
754 // FrameIndex with base register. Add an offset to the offset.
755 MI
.getOperand(FIOperandNum
).ChangeToRegister(MachineBasePtr
, false);
757 if (BasePtr
== StackPtr
)
760 // The frame index format for stackmaps and patchpoints is different from the
761 // X86 format. It only has a FI and an offset.
762 if (Opc
== TargetOpcode::STACKMAP
|| Opc
== TargetOpcode::PATCHPOINT
) {
763 assert(BasePtr
== FramePtr
&& "Expected the FP as base register");
764 int64_t Offset
= MI
.getOperand(FIOperandNum
+ 1).getImm() + FIOffset
;
765 MI
.getOperand(FIOperandNum
+ 1).ChangeToImmediate(Offset
);
769 if (MI
.getOperand(FIOperandNum
+3).isImm()) {
770 // Offset is a 32-bit integer.
771 int Imm
= (int)(MI
.getOperand(FIOperandNum
+ 3).getImm());
772 int Offset
= FIOffset
+ Imm
;
773 assert((!Is64Bit
|| isInt
<32>((long long)FIOffset
+ Imm
)) &&
774 "Requesting 64-bit offset in 32-bit immediate!");
775 if (Offset
!= 0 || !tryOptimizeLEAtoMOV(II
))
776 MI
.getOperand(FIOperandNum
+ 3).ChangeToImmediate(Offset
);
778 // Offset is symbolic. This is extremely rare.
779 uint64_t Offset
= FIOffset
+
780 (uint64_t)MI
.getOperand(FIOperandNum
+3).getOffset();
781 MI
.getOperand(FIOperandNum
+ 3).setOffset(Offset
);
785 Register
X86RegisterInfo::getFrameRegister(const MachineFunction
&MF
) const {
786 const X86FrameLowering
*TFI
= getFrameLowering(MF
);
787 return TFI
->hasFP(MF
) ? FramePtr
: StackPtr
;
791 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction
&MF
) const {
792 const X86Subtarget
&Subtarget
= MF
.getSubtarget
<X86Subtarget
>();
793 Register FrameReg
= getFrameRegister(MF
);
794 if (Subtarget
.isTarget64BitILP32())
795 FrameReg
= getX86SubSuperRegister(FrameReg
, 32);
800 X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction
&MF
) const {
801 const X86Subtarget
&Subtarget
= MF
.getSubtarget
<X86Subtarget
>();
802 Register StackReg
= getStackRegister();
803 if (Subtarget
.isTarget64BitILP32())
804 StackReg
= getX86SubSuperRegister(StackReg
, 32);