| blob | d83eb4a3bf095882039f06068c72d422561291a0 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>)
36 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
37 ; CHECK-LABEL: v16i8:
38 ; CHECK: // %bb.0:
39 ; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b
40 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
41 ; CHECK-NEXT: movi v3.16b, #127
42 ; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
43 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
44 ; CHECK-NEXT: mvn v5.16b, v4.16b
45 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
46 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
47 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
48 ; CHECK-NEXT: ret
49 %z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
50 ret <16 x i8> %z
51 }
53 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
54 ; CHECK-LABEL: v32i8:
55 ; CHECK: // %bb.0:
56 ; CHECK-NEXT: sub v4.16b, v0.16b, v2.16b
57 ; CHECK-NEXT: cmlt v7.16b, v4.16b, #0
58 ; CHECK-NEXT: movi v6.16b, #127
59 ; CHECK-NEXT: mvn v16.16b, v7.16b
60 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
61 ; CHECK-NEXT: sub v7.16b, v1.16b, v3.16b
62 ; CHECK-NEXT: cmgt v2.16b, v2.16b, #0
63 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v4.16b
64 ; CHECK-NEXT: cmlt v16.16b, v7.16b, #0
65 ; CHECK-NEXT: movi v5.16b, #127
66 ; CHECK-NEXT: cmgt v3.16b, v3.16b, #0
67 ; CHECK-NEXT: cmgt v1.16b, v1.16b, v7.16b
68 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
69 ; CHECK-NEXT: mvn v2.16b, v16.16b
70 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
71 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
72 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
73 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
74 ; CHECK-NEXT: ret
75 %z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
76 ret <32 x i8> %z
77 }
79 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
80 ; CHECK-LABEL: v64i8:
81 ; CHECK: // %bb.0:
82 ; CHECK-NEXT: sub v16.16b, v0.16b, v4.16b
83 ; CHECK-NEXT: cmlt v24.16b, v16.16b, #0
84 ; CHECK-NEXT: movi v18.16b, #127
85 ; CHECK-NEXT: sub v19.16b, v1.16b, v5.16b
86 ; CHECK-NEXT: mvn v25.16b, v24.16b
87 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
88 ; CHECK-NEXT: cmlt v24.16b, v19.16b, #0
89 ; CHECK-NEXT: movi v20.16b, #127
90 ; CHECK-NEXT: sub v21.16b, v2.16b, v6.16b
91 ; CHECK-NEXT: mvn v25.16b, v24.16b
92 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
93 ; CHECK-NEXT: cmlt v24.16b, v21.16b, #0
94 ; CHECK-NEXT: cmgt v4.16b, v4.16b, #0
95 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v16.16b
96 ; CHECK-NEXT: movi v22.16b, #127
97 ; CHECK-NEXT: sub v23.16b, v3.16b, v7.16b
98 ; CHECK-NEXT: mvn v25.16b, v24.16b
99 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
100 ; CHECK-NEXT: cmgt v4.16b, v5.16b, #0
101 ; CHECK-NEXT: cmgt v1.16b, v1.16b, v19.16b
102 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
103 ; CHECK-NEXT: cmlt v24.16b, v23.16b, #0
104 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
105 ; CHECK-NEXT: cmgt v4.16b, v6.16b, #0
106 ; CHECK-NEXT: cmgt v2.16b, v2.16b, v21.16b
107 ; CHECK-NEXT: movi v17.16b, #127
108 ; CHECK-NEXT: mvn v25.16b, v24.16b
109 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
110 ; CHECK-NEXT: cmgt v4.16b, v7.16b, #0
111 ; CHECK-NEXT: cmgt v3.16b, v3.16b, v23.16b
112 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
113 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
114 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
115 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
116 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
117 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
118 ; CHECK-NEXT: ret
119 %z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
120 ret <64 x i8> %z
121 }
123 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
124 ; CHECK-LABEL: v8i16:
125 ; CHECK: // %bb.0:
126 ; CHECK-NEXT: sub v2.8h, v0.8h, v1.8h
127 ; CHECK-NEXT: cmlt v4.8h, v2.8h, #0
128 ; CHECK-NEXT: mvni v3.8h, #128, lsl #8
129 ; CHECK-NEXT: cmgt v1.8h, v1.8h, #0
130 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v2.8h
131 ; CHECK-NEXT: mvn v5.16b, v4.16b
132 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
133 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
134 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
135 ; CHECK-NEXT: ret
136 %z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
137 ret <8 x i16> %z
138 }
140 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
141 ; CHECK-LABEL: v16i16:
142 ; CHECK: // %bb.0:
143 ; CHECK-NEXT: sub v4.8h, v0.8h, v2.8h
144 ; CHECK-NEXT: cmlt v7.8h, v4.8h, #0
145 ; CHECK-NEXT: mvni v6.8h, #128, lsl #8
146 ; CHECK-NEXT: mvn v16.16b, v7.16b
147 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
148 ; CHECK-NEXT: sub v7.8h, v1.8h, v3.8h
149 ; CHECK-NEXT: cmgt v2.8h, v2.8h, #0
150 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v4.8h
151 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
152 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
153 ; CHECK-NEXT: cmgt v3.8h, v3.8h, #0
154 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v7.8h
155 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
156 ; CHECK-NEXT: mvn v2.16b, v16.16b
157 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
158 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
159 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
160 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
161 ; CHECK-NEXT: ret
162 %z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
163 ret <16 x i16> %z
164 }
166 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
167 ; CHECK-LABEL: v32i16:
168 ; CHECK: // %bb.0:
169 ; CHECK-NEXT: sub v16.8h, v0.8h, v4.8h
170 ; CHECK-NEXT: cmlt v24.8h, v16.8h, #0
171 ; CHECK-NEXT: mvni v18.8h, #128, lsl #8
172 ; CHECK-NEXT: sub v19.8h, v1.8h, v5.8h
173 ; CHECK-NEXT: mvn v25.16b, v24.16b
174 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
175 ; CHECK-NEXT: cmlt v24.8h, v19.8h, #0
176 ; CHECK-NEXT: mvni v20.8h, #128, lsl #8
177 ; CHECK-NEXT: sub v21.8h, v2.8h, v6.8h
178 ; CHECK-NEXT: mvn v25.16b, v24.16b
179 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
180 ; CHECK-NEXT: cmlt v24.8h, v21.8h, #0
181 ; CHECK-NEXT: cmgt v4.8h, v4.8h, #0
182 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v16.8h
183 ; CHECK-NEXT: mvni v22.8h, #128, lsl #8
184 ; CHECK-NEXT: sub v23.8h, v3.8h, v7.8h
185 ; CHECK-NEXT: mvn v25.16b, v24.16b
186 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
187 ; CHECK-NEXT: cmgt v4.8h, v5.8h, #0
188 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v19.8h
189 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
190 ; CHECK-NEXT: cmlt v24.8h, v23.8h, #0
191 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
192 ; CHECK-NEXT: cmgt v4.8h, v6.8h, #0
193 ; CHECK-NEXT: cmgt v2.8h, v2.8h, v21.8h
194 ; CHECK-NEXT: mvni v17.8h, #128, lsl #8
195 ; CHECK-NEXT: mvn v25.16b, v24.16b
196 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
197 ; CHECK-NEXT: cmgt v4.8h, v7.8h, #0
198 ; CHECK-NEXT: cmgt v3.8h, v3.8h, v23.8h
199 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
200 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
201 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
202 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
203 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
204 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
205 ; CHECK-NEXT: ret
206 %z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
207 ret <32 x i16> %z
208 }
210 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
211 ; CHECK-LABEL: v8i8:
212 ; CHECK: // %bb.0:
213 ; CHECK-NEXT: ldr d0, [x0]
214 ; CHECK-NEXT: ldr d1, [x1]
215 ; CHECK-NEXT: movi v2.8b, #127
216 ; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
217 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
218 ; CHECK-NEXT: cmgt v1.8b, v1.8b, #0
219 ; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
220 ; CHECK-NEXT: mvn v5.8b, v4.8b
221 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
222 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
223 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
224 ; CHECK-NEXT: str d0, [x2]
225 ; CHECK-NEXT: ret
226 %x = load <8 x i8>, <8 x i8>* %px
227 %y = load <8 x i8>, <8 x i8>* %py
228 %z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
229 store <8 x i8> %z, <8 x i8>* %pz
230 ret void
231 }
233 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
234 ; CHECK-LABEL: v4i8:
235 ; CHECK: // %bb.0:
236 ; CHECK-NEXT: ldrsb w8, [x0]
237 ; CHECK-NEXT: ldrsb w9, [x1]
238 ; CHECK-NEXT: ldrsb w10, [x0, #1]
239 ; CHECK-NEXT: ldrsb w11, [x1, #1]
240 ; CHECK-NEXT: fmov s0, w8
241 ; CHECK-NEXT: fmov s1, w9
242 ; CHECK-NEXT: ldrsb w8, [x0, #2]
243 ; CHECK-NEXT: ldrsb w9, [x1, #2]
244 ; CHECK-NEXT: mov v0.h[1], w10
245 ; CHECK-NEXT: mov v1.h[1], w11
246 ; CHECK-NEXT: ldrsb w10, [x0, #3]
247 ; CHECK-NEXT: ldrsb w11, [x1, #3]
248 ; CHECK-NEXT: mov v0.h[2], w8
249 ; CHECK-NEXT: mov v1.h[2], w9
250 ; CHECK-NEXT: mov v0.h[3], w10
251 ; CHECK-NEXT: mov v1.h[3], w11
252 ; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
253 ; CHECK-NEXT: movi v1.4h, #127
254 ; CHECK-NEXT: smin v0.4h, v0.4h, v1.4h
255 ; CHECK-NEXT: mvni v1.4h, #127
256 ; CHECK-NEXT: smax v0.4h, v0.4h, v1.4h
257 ; CHECK-NEXT: xtn v0.8b, v0.8h
258 ; CHECK-NEXT: str s0, [x2]
259 ; CHECK-NEXT: ret
260 %x = load <4 x i8>, <4 x i8>* %px
261 %y = load <4 x i8>, <4 x i8>* %py
262 %z = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
263 store <4 x i8> %z, <4 x i8>* %pz
264 ret void
265 }
267 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
268 ; CHECK-LABEL: v2i8:
269 ; CHECK: // %bb.0:
270 ; CHECK-NEXT: ldrsb w8, [x0]
271 ; CHECK-NEXT: ldrsb w9, [x1]
272 ; CHECK-NEXT: ldrsb w10, [x0, #1]
273 ; CHECK-NEXT: ldrsb w11, [x1, #1]
274 ; CHECK-NEXT: fmov s0, w8
275 ; CHECK-NEXT: fmov s1, w9
276 ; CHECK-NEXT: mov v0.s[1], w10
277 ; CHECK-NEXT: mov v1.s[1], w11
278 ; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
279 ; CHECK-NEXT: movi v1.2s, #127
280 ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
281 ; CHECK-NEXT: mvni v1.2s, #127
282 ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
283 ; CHECK-NEXT: mov w8, v0.s[1]
284 ; CHECK-NEXT: fmov w9, s0
285 ; CHECK-NEXT: strb w8, [x2, #1]
286 ; CHECK-NEXT: strb w9, [x2]
287 ; CHECK-NEXT: ret
288 %x = load <2 x i8>, <2 x i8>* %px
289 %y = load <2 x i8>, <2 x i8>* %py
290 %z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
291 store <2 x i8> %z, <2 x i8>* %pz
292 ret void
293 }
295 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
296 ; CHECK-LABEL: v4i16:
297 ; CHECK: // %bb.0:
298 ; CHECK-NEXT: ldr d0, [x0]
299 ; CHECK-NEXT: ldr d1, [x1]
300 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
301 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
302 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
303 ; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
304 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
305 ; CHECK-NEXT: mvn v5.8b, v4.8b
306 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
307 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
308 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
309 ; CHECK-NEXT: str d0, [x2]
310 ; CHECK-NEXT: ret
311 %x = load <4 x i16>, <4 x i16>* %px
312 %y = load <4 x i16>, <4 x i16>* %py
313 %z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
314 store <4 x i16> %z, <4 x i16>* %pz
315 ret void
316 }
318 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
319 ; CHECK-LABEL: v2i16:
320 ; CHECK: // %bb.0:
321 ; CHECK-NEXT: ldrsh w8, [x0]
322 ; CHECK-NEXT: ldrsh w9, [x1]
323 ; CHECK-NEXT: ldrsh w10, [x0, #2]
324 ; CHECK-NEXT: ldrsh w11, [x1, #2]
325 ; CHECK-NEXT: fmov s0, w8
326 ; CHECK-NEXT: fmov s1, w9
327 ; CHECK-NEXT: mov v0.s[1], w10
328 ; CHECK-NEXT: mov v1.s[1], w11
329 ; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
330 ; CHECK-NEXT: movi v1.2s, #127, msl #8
331 ; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
332 ; CHECK-NEXT: mvni v1.2s, #127, msl #8
333 ; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
334 ; CHECK-NEXT: mov w8, v0.s[1]
335 ; CHECK-NEXT: fmov w9, s0
336 ; CHECK-NEXT: strh w8, [x2, #2]
337 ; CHECK-NEXT: strh w9, [x2]
338 ; CHECK-NEXT: ret
339 %x = load <2 x i16>, <2 x i16>* %px
340 %y = load <2 x i16>, <2 x i16>* %py
341 %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
342 store <2 x i16> %z, <2 x i16>* %pz
343 ret void
344 }
346 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
347 ; CHECK-LABEL: v12i8:
348 ; CHECK: // %bb.0:
349 ; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b
350 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
351 ; CHECK-NEXT: movi v3.16b, #127
352 ; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
353 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
354 ; CHECK-NEXT: mvn v5.16b, v4.16b
355 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
356 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
357 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
358 ; CHECK-NEXT: ret
359 %z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
360 ret <12 x i8> %z
361 }
363 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
364 ; CHECK-LABEL: v12i16:
365 ; CHECK: // %bb.0:
366 ; CHECK-NEXT: ldp q0, q1, [x0]
367 ; CHECK-NEXT: ldp q3, q2, [x1]
368 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
369 ; CHECK-NEXT: mvni v4.8h, #128, lsl #8
370 ; CHECK-NEXT: sub v6.8h, v1.8h, v2.8h
371 ; CHECK-NEXT: cmlt v7.8h, v6.8h, #0
372 ; CHECK-NEXT: mvn v16.16b, v7.16b
373 ; CHECK-NEXT: bsl v5.16b, v7.16b, v16.16b
374 ; CHECK-NEXT: sub v7.8h, v0.8h, v3.8h
375 ; CHECK-NEXT: cmgt v2.8h, v2.8h, #0
376 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v6.8h
377 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
378 ; CHECK-NEXT: cmgt v3.8h, v3.8h, #0
379 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v7.8h
380 ; CHECK-NEXT: eor v1.16b, v2.16b, v1.16b
381 ; CHECK-NEXT: mvn v2.16b, v16.16b
382 ; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b
383 ; CHECK-NEXT: bsl v4.16b, v16.16b, v2.16b
384 ; CHECK-NEXT: bsl v1.16b, v5.16b, v6.16b
385 ; CHECK-NEXT: bsl v0.16b, v4.16b, v7.16b
386 ; CHECK-NEXT: str q0, [x2]
387 ; CHECK-NEXT: str d1, [x2, #16]
388 ; CHECK-NEXT: ret
389 %x = load <12 x i16>, <12 x i16>* %px
390 %y = load <12 x i16>, <12 x i16>* %py
391 %z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
392 store <12 x i16> %z, <12 x i16>* %pz
393 ret void
394 }
396 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
397 ; CHECK-LABEL: v1i8:
398 ; CHECK: // %bb.0:
399 ; CHECK-NEXT: ldr b0, [x0]
400 ; CHECK-NEXT: ldr b1, [x1]
401 ; CHECK-NEXT: movi v2.8b, #127
402 ; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
403 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
404 ; CHECK-NEXT: cmgt v1.8b, v1.8b, #0
405 ; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
406 ; CHECK-NEXT: mvn v5.8b, v4.8b
407 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
408 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
409 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
410 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
411 ; CHECK-NEXT: ret
412 %x = load <1 x i8>, <1 x i8>* %px
413 %y = load <1 x i8>, <1 x i8>* %py
414 %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
415 store <1 x i8> %z, <1 x i8>* %pz
416 ret void
417 }
419 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
420 ; CHECK-LABEL: v1i16:
421 ; CHECK: // %bb.0:
422 ; CHECK-NEXT: ldr h0, [x0]
423 ; CHECK-NEXT: ldr h1, [x1]
424 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
425 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
426 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
427 ; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
428 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
429 ; CHECK-NEXT: mvn v5.8b, v4.8b
430 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
431 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
432 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
433 ; CHECK-NEXT: str h0, [x2]
434 ; CHECK-NEXT: ret
435 %x = load <1 x i16>, <1 x i16>* %px
436 %y = load <1 x i16>, <1 x i16>* %py
437 %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
438 store <1 x i16> %z, <1 x i16>* %pz
439 ret void
440 }
442 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
443 ; CHECK-LABEL: v16i4:
444 ; CHECK: // %bb.0:
445 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
446 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
447 ; CHECK-NEXT: sshr v1.16b, v1.16b, #4
448 ; CHECK-NEXT: sshr v0.16b, v0.16b, #4
449 ; CHECK-NEXT: movi v2.16b, #7
450 ; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
451 ; CHECK-NEXT: smin v0.16b, v0.16b, v2.16b
452 ; CHECK-NEXT: movi v1.16b, #248
453 ; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
454 ; CHECK-NEXT: ret
455 %z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
456 ret <16 x i4> %z
457 }
459 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
460 ; CHECK-LABEL: v16i1:
461 ; CHECK: // %bb.0:
462 ; CHECK-NEXT: shl v1.16b, v1.16b, #7
463 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
464 ; CHECK-NEXT: sshr v1.16b, v1.16b, #7
465 ; CHECK-NEXT: sshr v0.16b, v0.16b, #7
466 ; CHECK-NEXT: movi v2.2d, #0000000000000000
467 ; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
468 ; CHECK-NEXT: smin v0.16b, v0.16b, v2.16b
469 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
470 ; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
471 ; CHECK-NEXT: ret
472 %z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
473 ret <16 x i1> %z
474 }
476 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
477 ; CHECK-LABEL: v2i32:
478 ; CHECK: // %bb.0:
479 ; CHECK-NEXT: sub v2.2s, v0.2s, v1.2s
480 ; CHECK-NEXT: cmlt v4.2s, v2.2s, #0
481 ; CHECK-NEXT: mvni v3.2s, #128, lsl #24
482 ; CHECK-NEXT: cmgt v1.2s, v1.2s, #0
483 ; CHECK-NEXT: cmgt v0.2s, v0.2s, v2.2s
484 ; CHECK-NEXT: mvn v5.8b, v4.8b
485 ; CHECK-NEXT: bsl v3.8b, v4.8b, v5.8b
486 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
487 ; CHECK-NEXT: bsl v0.8b, v3.8b, v2.8b
488 ; CHECK-NEXT: ret
489 %z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
490 ret <2 x i32> %z
491 }
493 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
494 ; CHECK-LABEL: v4i32:
495 ; CHECK: // %bb.0:
496 ; CHECK-NEXT: sub v2.4s, v0.4s, v1.4s
497 ; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
498 ; CHECK-NEXT: mvni v3.4s, #128, lsl #24
499 ; CHECK-NEXT: cmgt v1.4s, v1.4s, #0
500 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
501 ; CHECK-NEXT: mvn v5.16b, v4.16b
502 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
503 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
504 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
505 ; CHECK-NEXT: ret
506 %z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
507 ret <4 x i32> %z
508 }
510 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
511 ; CHECK-LABEL: v8i32:
512 ; CHECK: // %bb.0:
513 ; CHECK-NEXT: sub v4.4s, v0.4s, v2.4s
514 ; CHECK-NEXT: cmlt v7.4s, v4.4s, #0
515 ; CHECK-NEXT: mvni v6.4s, #128, lsl #24
516 ; CHECK-NEXT: mvn v16.16b, v7.16b
517 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
518 ; CHECK-NEXT: sub v7.4s, v1.4s, v3.4s
519 ; CHECK-NEXT: cmgt v2.4s, v2.4s, #0
520 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v4.4s
521 ; CHECK-NEXT: cmlt v16.4s, v7.4s, #0
522 ; CHECK-NEXT: mvni v5.4s, #128, lsl #24
523 ; CHECK-NEXT: cmgt v3.4s, v3.4s, #0
524 ; CHECK-NEXT: cmgt v1.4s, v1.4s, v7.4s
525 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
526 ; CHECK-NEXT: mvn v2.16b, v16.16b
527 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
528 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
529 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
530 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
531 ; CHECK-NEXT: ret
532 %z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
533 ret <8 x i32> %z
534 }
536 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
537 ; CHECK-LABEL: v16i32:
538 ; CHECK: // %bb.0:
539 ; CHECK-NEXT: sub v16.4s, v0.4s, v4.4s
540 ; CHECK-NEXT: cmlt v24.4s, v16.4s, #0
541 ; CHECK-NEXT: mvni v18.4s, #128, lsl #24
542 ; CHECK-NEXT: sub v19.4s, v1.4s, v5.4s
543 ; CHECK-NEXT: mvn v25.16b, v24.16b
544 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
545 ; CHECK-NEXT: cmlt v24.4s, v19.4s, #0
546 ; CHECK-NEXT: mvni v20.4s, #128, lsl #24
547 ; CHECK-NEXT: sub v21.4s, v2.4s, v6.4s
548 ; CHECK-NEXT: mvn v25.16b, v24.16b
549 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
550 ; CHECK-NEXT: cmlt v24.4s, v21.4s, #0
551 ; CHECK-NEXT: cmgt v4.4s, v4.4s, #0
552 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v16.4s
553 ; CHECK-NEXT: mvni v22.4s, #128, lsl #24
554 ; CHECK-NEXT: sub v23.4s, v3.4s, v7.4s
555 ; CHECK-NEXT: mvn v25.16b, v24.16b
556 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
557 ; CHECK-NEXT: cmgt v4.4s, v5.4s, #0
558 ; CHECK-NEXT: cmgt v1.4s, v1.4s, v19.4s
559 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
560 ; CHECK-NEXT: cmlt v24.4s, v23.4s, #0
561 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
562 ; CHECK-NEXT: cmgt v4.4s, v6.4s, #0
563 ; CHECK-NEXT: cmgt v2.4s, v2.4s, v21.4s
564 ; CHECK-NEXT: mvni v17.4s, #128, lsl #24
565 ; CHECK-NEXT: mvn v25.16b, v24.16b
566 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
567 ; CHECK-NEXT: cmgt v4.4s, v7.4s, #0
568 ; CHECK-NEXT: cmgt v3.4s, v3.4s, v23.4s
569 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
570 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
571 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
572 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
573 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
574 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
575 ; CHECK-NEXT: ret
576 %z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
577 ret <16 x i32> %z
578 }
580 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
581 ; CHECK-LABEL: v2i64:
582 ; CHECK: // %bb.0:
583 ; CHECK-NEXT: sub v2.2d, v0.2d, v1.2d
584 ; CHECK-NEXT: mov x8, #9223372036854775807
585 ; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
586 ; CHECK-NEXT: cmgt v1.2d, v1.2d, #0
587 ; CHECK-NEXT: dup v4.2d, x8
588 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v2.2d
589 ; CHECK-NEXT: mvn v5.16b, v3.16b
590 ; CHECK-NEXT: bsl v4.16b, v3.16b, v5.16b
591 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
592 ; CHECK-NEXT: bsl v0.16b, v4.16b, v2.16b
593 ; CHECK-NEXT: ret
594 %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
595 ret <2 x i64> %z
596 }
598 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
599 ; CHECK-LABEL: v4i64:
600 ; CHECK: // %bb.0:
601 ; CHECK-NEXT: sub v4.2d, v0.2d, v2.2d
602 ; CHECK-NEXT: mov x8, #9223372036854775807
603 ; CHECK-NEXT: cmlt v5.2d, v4.2d, #0
604 ; CHECK-NEXT: dup v6.2d, x8
605 ; CHECK-NEXT: mvn v7.16b, v5.16b
606 ; CHECK-NEXT: mov v16.16b, v6.16b
607 ; CHECK-NEXT: bsl v16.16b, v5.16b, v7.16b
608 ; CHECK-NEXT: sub v5.2d, v1.2d, v3.2d
609 ; CHECK-NEXT: cmgt v2.2d, v2.2d, #0
610 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v4.2d
611 ; CHECK-NEXT: cmlt v7.2d, v5.2d, #0
612 ; CHECK-NEXT: cmgt v3.2d, v3.2d, #0
613 ; CHECK-NEXT: cmgt v1.2d, v1.2d, v5.2d
614 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
615 ; CHECK-NEXT: mvn v2.16b, v7.16b
616 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
617 ; CHECK-NEXT: bsl v6.16b, v7.16b, v2.16b
618 ; CHECK-NEXT: bsl v0.16b, v16.16b, v4.16b
619 ; CHECK-NEXT: bsl v1.16b, v6.16b, v5.16b
620 ; CHECK-NEXT: ret
621 %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
622 ret <4 x i64> %z
623 }
625 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
626 ; CHECK-LABEL: v8i64:
627 ; CHECK: // %bb.0:
628 ; CHECK-NEXT: sub v16.2d, v0.2d, v4.2d
629 ; CHECK-NEXT: mov x8, #9223372036854775807
630 ; CHECK-NEXT: sub v17.2d, v1.2d, v5.2d
631 ; CHECK-NEXT: cmlt v20.2d, v16.2d, #0
632 ; CHECK-NEXT: dup v21.2d, x8
633 ; CHECK-NEXT: sub v18.2d, v2.2d, v6.2d
634 ; CHECK-NEXT: cmlt v22.2d, v17.2d, #0
635 ; CHECK-NEXT: mvn v24.16b, v20.16b
636 ; CHECK-NEXT: mov v25.16b, v21.16b
637 ; CHECK-NEXT: cmlt v23.2d, v18.2d, #0
638 ; CHECK-NEXT: bsl v25.16b, v20.16b, v24.16b
639 ; CHECK-NEXT: mvn v20.16b, v22.16b
640 ; CHECK-NEXT: mov v24.16b, v21.16b
641 ; CHECK-NEXT: cmgt v4.2d, v4.2d, #0
642 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v16.2d
643 ; CHECK-NEXT: sub v19.2d, v3.2d, v7.2d
644 ; CHECK-NEXT: bsl v24.16b, v22.16b, v20.16b
645 ; CHECK-NEXT: mvn v20.16b, v23.16b
646 ; CHECK-NEXT: mov v22.16b, v21.16b
647 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
648 ; CHECK-NEXT: cmgt v4.2d, v5.2d, #0
649 ; CHECK-NEXT: cmgt v1.2d, v1.2d, v17.2d
650 ; CHECK-NEXT: bsl v22.16b, v23.16b, v20.16b
651 ; CHECK-NEXT: cmlt v20.2d, v19.2d, #0
652 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
653 ; CHECK-NEXT: cmgt v4.2d, v6.2d, #0
654 ; CHECK-NEXT: cmgt v2.2d, v2.2d, v18.2d
655 ; CHECK-NEXT: mvn v23.16b, v20.16b
656 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
657 ; CHECK-NEXT: cmgt v4.2d, v7.2d, #0
658 ; CHECK-NEXT: cmgt v3.2d, v3.2d, v19.2d
659 ; CHECK-NEXT: bsl v21.16b, v20.16b, v23.16b
660 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
661 ; CHECK-NEXT: bsl v0.16b, v25.16b, v16.16b
662 ; CHECK-NEXT: bsl v1.16b, v24.16b, v17.16b
663 ; CHECK-NEXT: bsl v2.16b, v22.16b, v18.16b
664 ; CHECK-NEXT: bsl v3.16b, v21.16b, v19.16b
665 ; CHECK-NEXT: ret
666 %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
667 ret <8 x i64> %z
668 }
670 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
671 ; CHECK-LABEL: v2i128:
672 ; CHECK: // %bb.0:
673 ; CHECK-NEXT: cmp x7, #0 // =0
674 ; CHECK-NEXT: cset w9, ge
675 ; CHECK-NEXT: csinc w9, w9, wzr, ne
676 ; CHECK-NEXT: cmp x3, #0 // =0
677 ; CHECK-NEXT: cset w10, ge
678 ; CHECK-NEXT: csinc w10, w10, wzr, ne
679 ; CHECK-NEXT: cmp w10, w9
680 ; CHECK-NEXT: cset w9, ne
681 ; CHECK-NEXT: subs x11, x2, x6
682 ; CHECK-NEXT: sbcs x12, x3, x7
683 ; CHECK-NEXT: cmp x12, #0 // =0
684 ; CHECK-NEXT: cset w13, ge
685 ; CHECK-NEXT: mov x8, #9223372036854775807
686 ; CHECK-NEXT: csinc w13, w13, wzr, ne
687 ; CHECK-NEXT: cinv x14, x8, ge
688 ; CHECK-NEXT: cmp w10, w13
689 ; CHECK-NEXT: cset w13, ne
690 ; CHECK-NEXT: asr x10, x12, #63
691 ; CHECK-NEXT: tst w9, w13
692 ; CHECK-NEXT: csel x3, x14, x12, ne
693 ; CHECK-NEXT: csel x2, x10, x11, ne
694 ; CHECK-NEXT: cmp x5, #0 // =0
695 ; CHECK-NEXT: cset w9, ge
696 ; CHECK-NEXT: csinc w9, w9, wzr, ne
697 ; CHECK-NEXT: cmp x1, #0 // =0
698 ; CHECK-NEXT: cset w10, ge
699 ; CHECK-NEXT: csinc w10, w10, wzr, ne
700 ; CHECK-NEXT: cmp w10, w9
701 ; CHECK-NEXT: cset w9, ne
702 ; CHECK-NEXT: subs x11, x0, x4
703 ; CHECK-NEXT: sbcs x12, x1, x5
704 ; CHECK-NEXT: cmp x12, #0 // =0
705 ; CHECK-NEXT: cset w13, ge
706 ; CHECK-NEXT: csinc w13, w13, wzr, ne
707 ; CHECK-NEXT: cinv x8, x8, ge
708 ; CHECK-NEXT: cmp w10, w13
709 ; CHECK-NEXT: cset w10, ne
710 ; CHECK-NEXT: tst w9, w10
711 ; CHECK-NEXT: asr x9, x12, #63
712 ; CHECK-NEXT: csel x9, x9, x11, ne
713 ; CHECK-NEXT: csel x1, x8, x12, ne
714 ; CHECK-NEXT: fmov d0, x9
715 ; CHECK-NEXT: mov v0.d[1], x1
716 ; CHECK-NEXT: fmov x0, d0
717 ; CHECK-NEXT: ret
718 %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
719 ret <2 x i128> %z
720 }