| blob | 4ff14c72e1f8b7c0d68e3c89faf06bf0109822dd |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.uadd.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128>, <2 x i128>)
35 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
36 ; CHECK-LABEL: v16i8:
37 ; CHECK: // %bb.0:
38 ; CHECK-NEXT: mvn v2.16b, v1.16b
39 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
40 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
41 ; CHECK-NEXT: ret
42 %z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
43 ret <16 x i8> %z
44 }
46 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
47 ; CHECK-LABEL: v32i8:
48 ; CHECK: // %bb.0:
49 ; CHECK-NEXT: mvn v4.16b, v2.16b
50 ; CHECK-NEXT: mvn v5.16b, v3.16b
51 ; CHECK-NEXT: umin v0.16b, v0.16b, v4.16b
52 ; CHECK-NEXT: umin v1.16b, v1.16b, v5.16b
53 ; CHECK-NEXT: add v0.16b, v0.16b, v2.16b
54 ; CHECK-NEXT: add v1.16b, v1.16b, v3.16b
55 ; CHECK-NEXT: ret
56 %z = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
57 ret <32 x i8> %z
58 }
60 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
61 ; CHECK-LABEL: v64i8:
62 ; CHECK: // %bb.0:
63 ; CHECK-NEXT: mvn v16.16b, v4.16b
64 ; CHECK-NEXT: umin v0.16b, v0.16b, v16.16b
65 ; CHECK-NEXT: mvn v16.16b, v5.16b
66 ; CHECK-NEXT: umin v1.16b, v1.16b, v16.16b
67 ; CHECK-NEXT: mvn v16.16b, v6.16b
68 ; CHECK-NEXT: umin v2.16b, v2.16b, v16.16b
69 ; CHECK-NEXT: mvn v16.16b, v7.16b
70 ; CHECK-NEXT: umin v3.16b, v3.16b, v16.16b
71 ; CHECK-NEXT: add v0.16b, v0.16b, v4.16b
72 ; CHECK-NEXT: add v1.16b, v1.16b, v5.16b
73 ; CHECK-NEXT: add v2.16b, v2.16b, v6.16b
74 ; CHECK-NEXT: add v3.16b, v3.16b, v7.16b
75 ; CHECK-NEXT: ret
76 %z = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
77 ret <64 x i8> %z
78 }
80 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
81 ; CHECK-LABEL: v8i16:
82 ; CHECK: // %bb.0:
83 ; CHECK-NEXT: mvn v2.16b, v1.16b
84 ; CHECK-NEXT: umin v0.8h, v0.8h, v2.8h
85 ; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
86 ; CHECK-NEXT: ret
87 %z = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
88 ret <8 x i16> %z
89 }
91 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
92 ; CHECK-LABEL: v16i16:
93 ; CHECK: // %bb.0:
94 ; CHECK-NEXT: mvn v4.16b, v2.16b
95 ; CHECK-NEXT: mvn v5.16b, v3.16b
96 ; CHECK-NEXT: umin v0.8h, v0.8h, v4.8h
97 ; CHECK-NEXT: umin v1.8h, v1.8h, v5.8h
98 ; CHECK-NEXT: add v0.8h, v0.8h, v2.8h
99 ; CHECK-NEXT: add v1.8h, v1.8h, v3.8h
100 ; CHECK-NEXT: ret
101 %z = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
102 ret <16 x i16> %z
103 }
105 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
106 ; CHECK-LABEL: v32i16:
107 ; CHECK: // %bb.0:
108 ; CHECK-NEXT: mvn v16.16b, v4.16b
109 ; CHECK-NEXT: umin v0.8h, v0.8h, v16.8h
110 ; CHECK-NEXT: mvn v16.16b, v5.16b
111 ; CHECK-NEXT: umin v1.8h, v1.8h, v16.8h
112 ; CHECK-NEXT: mvn v16.16b, v6.16b
113 ; CHECK-NEXT: umin v2.8h, v2.8h, v16.8h
114 ; CHECK-NEXT: mvn v16.16b, v7.16b
115 ; CHECK-NEXT: umin v3.8h, v3.8h, v16.8h
116 ; CHECK-NEXT: add v0.8h, v0.8h, v4.8h
117 ; CHECK-NEXT: add v1.8h, v1.8h, v5.8h
118 ; CHECK-NEXT: add v2.8h, v2.8h, v6.8h
119 ; CHECK-NEXT: add v3.8h, v3.8h, v7.8h
120 ; CHECK-NEXT: ret
121 %z = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
122 ret <32 x i16> %z
123 }
125 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
126 ; CHECK-LABEL: v8i8:
127 ; CHECK: // %bb.0:
128 ; CHECK-NEXT: ldr d0, [x1]
129 ; CHECK-NEXT: ldr d1, [x0]
130 ; CHECK-NEXT: mvn v2.8b, v0.8b
131 ; CHECK-NEXT: umin v1.8b, v1.8b, v2.8b
132 ; CHECK-NEXT: add v0.8b, v1.8b, v0.8b
133 ; CHECK-NEXT: str d0, [x2]
134 ; CHECK-NEXT: ret
135 %x = load <8 x i8>, <8 x i8>* %px
136 %y = load <8 x i8>, <8 x i8>* %py
137 %z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
138 store <8 x i8> %z, <8 x i8>* %pz
139 ret void
140 }
142 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
143 ; CHECK-LABEL: v4i8:
144 ; CHECK: // %bb.0:
145 ; CHECK-NEXT: ldrb w8, [x0]
146 ; CHECK-NEXT: ldrb w9, [x1]
147 ; CHECK-NEXT: ldrb w10, [x0, #1]
148 ; CHECK-NEXT: ldrb w11, [x1, #1]
149 ; CHECK-NEXT: ldrb w12, [x0, #2]
150 ; CHECK-NEXT: fmov s0, w8
151 ; CHECK-NEXT: ldrb w8, [x1, #2]
152 ; CHECK-NEXT: fmov s1, w9
153 ; CHECK-NEXT: mov v0.h[1], w10
154 ; CHECK-NEXT: ldrb w9, [x0, #3]
155 ; CHECK-NEXT: ldrb w10, [x1, #3]
156 ; CHECK-NEXT: mov v1.h[1], w11
157 ; CHECK-NEXT: mov v0.h[2], w12
158 ; CHECK-NEXT: mov v1.h[2], w8
159 ; CHECK-NEXT: mov v0.h[3], w9
160 ; CHECK-NEXT: mov v1.h[3], w10
161 ; CHECK-NEXT: movi d2, #0xff00ff00ff00ff
162 ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
163 ; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h
164 ; CHECK-NEXT: xtn v0.8b, v0.8h
165 ; CHECK-NEXT: str s0, [x2]
166 ; CHECK-NEXT: ret
167 %x = load <4 x i8>, <4 x i8>* %px
168 %y = load <4 x i8>, <4 x i8>* %py
169 %z = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
170 store <4 x i8> %z, <4 x i8>* %pz
171 ret void
172 }
174 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
175 ; CHECK-LABEL: v2i8:
176 ; CHECK: // %bb.0:
177 ; CHECK-NEXT: ldrb w8, [x0]
178 ; CHECK-NEXT: ldrb w9, [x1]
179 ; CHECK-NEXT: ldrb w10, [x0, #1]
180 ; CHECK-NEXT: ldrb w11, [x1, #1]
181 ; CHECK-NEXT: fmov s0, w8
182 ; CHECK-NEXT: fmov s2, w9
183 ; CHECK-NEXT: mov v0.s[1], w10
184 ; CHECK-NEXT: mov v2.s[1], w11
185 ; CHECK-NEXT: movi d1, #0x0000ff000000ff
186 ; CHECK-NEXT: add v0.2s, v0.2s, v2.2s
187 ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
188 ; CHECK-NEXT: mov w8, v0.s[1]
189 ; CHECK-NEXT: fmov w9, s0
190 ; CHECK-NEXT: strb w8, [x2, #1]
191 ; CHECK-NEXT: strb w9, [x2]
192 ; CHECK-NEXT: ret
193 %x = load <2 x i8>, <2 x i8>* %px
194 %y = load <2 x i8>, <2 x i8>* %py
195 %z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
196 store <2 x i8> %z, <2 x i8>* %pz
197 ret void
198 }
200 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
201 ; CHECK-LABEL: v4i16:
202 ; CHECK: // %bb.0:
203 ; CHECK-NEXT: ldr d0, [x1]
204 ; CHECK-NEXT: ldr d1, [x0]
205 ; CHECK-NEXT: mvn v2.8b, v0.8b
206 ; CHECK-NEXT: umin v1.4h, v1.4h, v2.4h
207 ; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
208 ; CHECK-NEXT: str d0, [x2]
209 ; CHECK-NEXT: ret
210 %x = load <4 x i16>, <4 x i16>* %px
211 %y = load <4 x i16>, <4 x i16>* %py
212 %z = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
213 store <4 x i16> %z, <4 x i16>* %pz
214 ret void
215 }
217 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
218 ; CHECK-LABEL: v2i16:
219 ; CHECK: // %bb.0:
220 ; CHECK-NEXT: ldrh w8, [x0]
221 ; CHECK-NEXT: ldrh w9, [x1]
222 ; CHECK-NEXT: ldrh w10, [x0, #2]
223 ; CHECK-NEXT: ldrh w11, [x1, #2]
224 ; CHECK-NEXT: fmov s0, w8
225 ; CHECK-NEXT: fmov s2, w9
226 ; CHECK-NEXT: mov v0.s[1], w10
227 ; CHECK-NEXT: mov v2.s[1], w11
228 ; CHECK-NEXT: movi d1, #0x00ffff0000ffff
229 ; CHECK-NEXT: add v0.2s, v0.2s, v2.2s
230 ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
231 ; CHECK-NEXT: mov w8, v0.s[1]
232 ; CHECK-NEXT: fmov w9, s0
233 ; CHECK-NEXT: strh w8, [x2, #2]
234 ; CHECK-NEXT: strh w9, [x2]
235 ; CHECK-NEXT: ret
236 %x = load <2 x i16>, <2 x i16>* %px
237 %y = load <2 x i16>, <2 x i16>* %py
238 %z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
239 store <2 x i16> %z, <2 x i16>* %pz
240 ret void
241 }
243 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
244 ; CHECK-LABEL: v12i8:
245 ; CHECK: // %bb.0:
246 ; CHECK-NEXT: mvn v2.16b, v1.16b
247 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
248 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
249 ; CHECK-NEXT: ret
250 %z = call <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
251 ret <12 x i8> %z
252 }
254 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
255 ; CHECK-LABEL: v12i16:
256 ; CHECK: // %bb.0:
257 ; CHECK-NEXT: ldp q1, q0, [x1]
258 ; CHECK-NEXT: ldp q3, q2, [x0]
259 ; CHECK-NEXT: mvn v4.16b, v0.16b
260 ; CHECK-NEXT: mvn v5.16b, v1.16b
261 ; CHECK-NEXT: umin v2.8h, v2.8h, v4.8h
262 ; CHECK-NEXT: umin v3.8h, v3.8h, v5.8h
263 ; CHECK-NEXT: add v0.8h, v2.8h, v0.8h
264 ; CHECK-NEXT: add v1.8h, v3.8h, v1.8h
265 ; CHECK-NEXT: str q1, [x2]
266 ; CHECK-NEXT: str d0, [x2, #16]
267 ; CHECK-NEXT: ret
268 %x = load <12 x i16>, <12 x i16>* %px
269 %y = load <12 x i16>, <12 x i16>* %py
270 %z = call <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
271 store <12 x i16> %z, <12 x i16>* %pz
272 ret void
273 }
275 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
276 ; CHECK-LABEL: v1i8:
277 ; CHECK: // %bb.0:
278 ; CHECK-NEXT: ldr b0, [x1]
279 ; CHECK-NEXT: ldr b1, [x0]
280 ; CHECK-NEXT: mvn v2.8b, v0.8b
281 ; CHECK-NEXT: umin v1.8b, v1.8b, v2.8b
282 ; CHECK-NEXT: add v0.8b, v1.8b, v0.8b
283 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
284 ; CHECK-NEXT: ret
285 %x = load <1 x i8>, <1 x i8>* %px
286 %y = load <1 x i8>, <1 x i8>* %py
287 %z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
288 store <1 x i8> %z, <1 x i8>* %pz
289 ret void
290 }
292 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
293 ; CHECK-LABEL: v1i16:
294 ; CHECK: // %bb.0:
295 ; CHECK-NEXT: ldr h0, [x1]
296 ; CHECK-NEXT: ldr h1, [x0]
297 ; CHECK-NEXT: mvn v2.8b, v0.8b
298 ; CHECK-NEXT: umin v1.4h, v1.4h, v2.4h
299 ; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
300 ; CHECK-NEXT: str h0, [x2]
301 ; CHECK-NEXT: ret
302 %x = load <1 x i16>, <1 x i16>* %px
303 %y = load <1 x i16>, <1 x i16>* %py
304 %z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
305 store <1 x i16> %z, <1 x i16>* %pz
306 ret void
307 }
309 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
310 ; CHECK-LABEL: v16i4:
311 ; CHECK: // %bb.0:
312 ; CHECK-NEXT: movi v2.16b, #15
313 ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
314 ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
315 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
316 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
317 ; CHECK-NEXT: ret
318 %z = call <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
319 ret <16 x i4> %z
320 }
322 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
323 ; CHECK-LABEL: v16i1:
324 ; CHECK: // %bb.0:
325 ; CHECK-NEXT: movi v2.16b, #1
326 ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
327 ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
328 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
329 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
330 ; CHECK-NEXT: ret
331 %z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
332 ret <16 x i1> %z
333 }
335 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
336 ; CHECK-LABEL: v2i32:
337 ; CHECK: // %bb.0:
338 ; CHECK-NEXT: mvn v2.8b, v1.8b
339 ; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
340 ; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
341 ; CHECK-NEXT: ret
342 %z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
343 ret <2 x i32> %z
344 }
346 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
347 ; CHECK-LABEL: v4i32:
348 ; CHECK: // %bb.0:
349 ; CHECK-NEXT: mvn v2.16b, v1.16b
350 ; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
351 ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
352 ; CHECK-NEXT: ret
353 %z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
354 ret <4 x i32> %z
355 }
357 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
358 ; CHECK-LABEL: v8i32:
359 ; CHECK: // %bb.0:
360 ; CHECK-NEXT: mvn v4.16b, v2.16b
361 ; CHECK-NEXT: mvn v5.16b, v3.16b
362 ; CHECK-NEXT: umin v0.4s, v0.4s, v4.4s
363 ; CHECK-NEXT: umin v1.4s, v1.4s, v5.4s
364 ; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
365 ; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
366 ; CHECK-NEXT: ret
367 %z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
368 ret <8 x i32> %z
369 }
371 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
372 ; CHECK-LABEL: v16i32:
373 ; CHECK: // %bb.0:
374 ; CHECK-NEXT: mvn v16.16b, v4.16b
375 ; CHECK-NEXT: umin v0.4s, v0.4s, v16.4s
376 ; CHECK-NEXT: mvn v16.16b, v5.16b
377 ; CHECK-NEXT: umin v1.4s, v1.4s, v16.4s
378 ; CHECK-NEXT: mvn v16.16b, v6.16b
379 ; CHECK-NEXT: umin v2.4s, v2.4s, v16.4s
380 ; CHECK-NEXT: mvn v16.16b, v7.16b
381 ; CHECK-NEXT: umin v3.4s, v3.4s, v16.4s
382 ; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
383 ; CHECK-NEXT: add v1.4s, v1.4s, v5.4s
384 ; CHECK-NEXT: add v2.4s, v2.4s, v6.4s
385 ; CHECK-NEXT: add v3.4s, v3.4s, v7.4s
386 ; CHECK-NEXT: ret
387 %z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
388 ret <16 x i32> %z
389 }
391 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
392 ; CHECK-LABEL: v2i64:
393 ; CHECK: // %bb.0:
394 ; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
395 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
396 ; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
397 ; CHECK-NEXT: ret
398 %z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
399 ret <2 x i64> %z
400 }
402 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
403 ; CHECK-LABEL: v4i64:
404 ; CHECK: // %bb.0:
405 ; CHECK-NEXT: add v2.2d, v0.2d, v2.2d
406 ; CHECK-NEXT: add v3.2d, v1.2d, v3.2d
407 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v2.2d
408 ; CHECK-NEXT: cmhi v1.2d, v1.2d, v3.2d
409 ; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b
410 ; CHECK-NEXT: orr v1.16b, v3.16b, v1.16b
411 ; CHECK-NEXT: ret
412 %z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
413 ret <4 x i64> %z
414 }
416 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
417 ; CHECK-LABEL: v8i64:
418 ; CHECK: // %bb.0:
419 ; CHECK-NEXT: add v4.2d, v0.2d, v4.2d
420 ; CHECK-NEXT: add v5.2d, v1.2d, v5.2d
421 ; CHECK-NEXT: add v6.2d, v2.2d, v6.2d
422 ; CHECK-NEXT: add v7.2d, v3.2d, v7.2d
423 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v4.2d
424 ; CHECK-NEXT: cmhi v1.2d, v1.2d, v5.2d
425 ; CHECK-NEXT: cmhi v2.2d, v2.2d, v6.2d
426 ; CHECK-NEXT: cmhi v3.2d, v3.2d, v7.2d
427 ; CHECK-NEXT: orr v0.16b, v4.16b, v0.16b
428 ; CHECK-NEXT: orr v1.16b, v5.16b, v1.16b
429 ; CHECK-NEXT: orr v2.16b, v6.16b, v2.16b
430 ; CHECK-NEXT: orr v3.16b, v7.16b, v3.16b
431 ; CHECK-NEXT: ret
432 %z = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
433 ret <8 x i64> %z
434 }
436 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
437 ; CHECK-LABEL: v2i128:
438 ; CHECK: // %bb.0:
439 ; CHECK-NEXT: adds x8, x2, x6
440 ; CHECK-NEXT: adcs x9, x3, x7
441 ; CHECK-NEXT: cmp x8, x2
442 ; CHECK-NEXT: cset w10, lo
443 ; CHECK-NEXT: cmp x9, x3
444 ; CHECK-NEXT: cset w11, lo
445 ; CHECK-NEXT: csel w10, w10, w11, eq
446 ; CHECK-NEXT: cmp w10, #0 // =0
447 ; CHECK-NEXT: csinv x3, x9, xzr, eq
448 ; CHECK-NEXT: csinv x2, x8, xzr, eq
449 ; CHECK-NEXT: adds x8, x0, x4
450 ; CHECK-NEXT: adcs x9, x1, x5
451 ; CHECK-NEXT: cmp x8, x0
452 ; CHECK-NEXT: cset w10, lo
453 ; CHECK-NEXT: cmp x9, x1
454 ; CHECK-NEXT: cset w11, lo
455 ; CHECK-NEXT: csel w10, w10, w11, eq
456 ; CHECK-NEXT: cmp w10, #0 // =0
457 ; CHECK-NEXT: csinv x8, x8, xzr, eq
458 ; CHECK-NEXT: csinv x1, x9, xzr, eq
459 ; CHECK-NEXT: fmov d0, x8
460 ; CHECK-NEXT: mov v0.d[1], x1
461 ; CHECK-NEXT: fmov x0, d0
462 ; CHECK-NEXT: ret
463 %z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
464 ret <2 x i128> %z
465 }