| blob | db982cc42d0cc599e54ccf08d6499e39f4fb086b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.usub.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.usub.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.usub.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.usub.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.usub.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.usub.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.usub.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.usub.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.usub.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.usub.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.usub.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.usub.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.usub.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.usub.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.usub.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.usub.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.usub.sat.v2i128(<2 x i128>, <2 x i128>)
36 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
37 ; CHECK-LABEL: v16i8:
38 ; CHECK: // %bb.0:
39 ; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b
40 ; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
41 ; CHECK-NEXT: ret
42 %z = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
43 ret <16 x i8> %z
44 }
46 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
47 ; CHECK-LABEL: v32i8:
48 ; CHECK: // %bb.0:
49 ; CHECK-NEXT: umax v0.16b, v0.16b, v2.16b
50 ; CHECK-NEXT: umax v1.16b, v1.16b, v3.16b
51 ; CHECK-NEXT: sub v0.16b, v0.16b, v2.16b
52 ; CHECK-NEXT: sub v1.16b, v1.16b, v3.16b
53 ; CHECK-NEXT: ret
54 %z = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
55 ret <32 x i8> %z
56 }
58 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
59 ; CHECK-LABEL: v64i8:
60 ; CHECK: // %bb.0:
61 ; CHECK-NEXT: umax v0.16b, v0.16b, v4.16b
62 ; CHECK-NEXT: umax v1.16b, v1.16b, v5.16b
63 ; CHECK-NEXT: umax v2.16b, v2.16b, v6.16b
64 ; CHECK-NEXT: umax v3.16b, v3.16b, v7.16b
65 ; CHECK-NEXT: sub v0.16b, v0.16b, v4.16b
66 ; CHECK-NEXT: sub v1.16b, v1.16b, v5.16b
67 ; CHECK-NEXT: sub v2.16b, v2.16b, v6.16b
68 ; CHECK-NEXT: sub v3.16b, v3.16b, v7.16b
69 ; CHECK-NEXT: ret
70 %z = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
71 ret <64 x i8> %z
72 }
74 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
75 ; CHECK-LABEL: v8i16:
76 ; CHECK: // %bb.0:
77 ; CHECK-NEXT: umax v0.8h, v0.8h, v1.8h
78 ; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h
79 ; CHECK-NEXT: ret
80 %z = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
81 ret <8 x i16> %z
82 }
84 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
85 ; CHECK-LABEL: v16i16:
86 ; CHECK: // %bb.0:
87 ; CHECK-NEXT: umax v0.8h, v0.8h, v2.8h
88 ; CHECK-NEXT: umax v1.8h, v1.8h, v3.8h
89 ; CHECK-NEXT: sub v0.8h, v0.8h, v2.8h
90 ; CHECK-NEXT: sub v1.8h, v1.8h, v3.8h
91 ; CHECK-NEXT: ret
92 %z = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
93 ret <16 x i16> %z
94 }
96 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
97 ; CHECK-LABEL: v32i16:
98 ; CHECK: // %bb.0:
99 ; CHECK-NEXT: umax v0.8h, v0.8h, v4.8h
100 ; CHECK-NEXT: umax v1.8h, v1.8h, v5.8h
101 ; CHECK-NEXT: umax v2.8h, v2.8h, v6.8h
102 ; CHECK-NEXT: umax v3.8h, v3.8h, v7.8h
103 ; CHECK-NEXT: sub v0.8h, v0.8h, v4.8h
104 ; CHECK-NEXT: sub v1.8h, v1.8h, v5.8h
105 ; CHECK-NEXT: sub v2.8h, v2.8h, v6.8h
106 ; CHECK-NEXT: sub v3.8h, v3.8h, v7.8h
107 ; CHECK-NEXT: ret
108 %z = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
109 ret <32 x i16> %z
110 }
112 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
113 ; CHECK-LABEL: v8i8:
114 ; CHECK: // %bb.0:
115 ; CHECK-NEXT: ldr d0, [x0]
116 ; CHECK-NEXT: ldr d1, [x1]
117 ; CHECK-NEXT: umax v0.8b, v0.8b, v1.8b
118 ; CHECK-NEXT: sub v0.8b, v0.8b, v1.8b
119 ; CHECK-NEXT: str d0, [x2]
120 ; CHECK-NEXT: ret
121 %x = load <8 x i8>, <8 x i8>* %px
122 %y = load <8 x i8>, <8 x i8>* %py
123 %z = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
124 store <8 x i8> %z, <8 x i8>* %pz
125 ret void
126 }
128 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
129 ; CHECK-LABEL: v4i8:
130 ; CHECK: // %bb.0:
131 ; CHECK-NEXT: ldrb w8, [x0]
132 ; CHECK-NEXT: ldrb w9, [x1]
133 ; CHECK-NEXT: ldrb w10, [x0, #1]
134 ; CHECK-NEXT: ldrb w11, [x1, #1]
135 ; CHECK-NEXT: fmov s0, w8
136 ; CHECK-NEXT: fmov s1, w9
137 ; CHECK-NEXT: ldrb w8, [x0, #2]
138 ; CHECK-NEXT: ldrb w9, [x1, #2]
139 ; CHECK-NEXT: mov v0.h[1], w10
140 ; CHECK-NEXT: mov v1.h[1], w11
141 ; CHECK-NEXT: ldrb w10, [x0, #3]
142 ; CHECK-NEXT: ldrb w11, [x1, #3]
143 ; CHECK-NEXT: mov v0.h[2], w8
144 ; CHECK-NEXT: mov v1.h[2], w9
145 ; CHECK-NEXT: mov v0.h[3], w10
146 ; CHECK-NEXT: mov v1.h[3], w11
147 ; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h
148 ; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
149 ; CHECK-NEXT: xtn v0.8b, v0.8h
150 ; CHECK-NEXT: str s0, [x2]
151 ; CHECK-NEXT: ret
152 %x = load <4 x i8>, <4 x i8>* %px
153 %y = load <4 x i8>, <4 x i8>* %py
154 %z = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
155 store <4 x i8> %z, <4 x i8>* %pz
156 ret void
157 }
159 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
160 ; CHECK-LABEL: v2i8:
161 ; CHECK: // %bb.0:
162 ; CHECK-NEXT: ldrb w8, [x0]
163 ; CHECK-NEXT: ldrb w9, [x1]
164 ; CHECK-NEXT: ldrb w10, [x0, #1]
165 ; CHECK-NEXT: ldrb w11, [x1, #1]
166 ; CHECK-NEXT: fmov s0, w8
167 ; CHECK-NEXT: fmov s1, w9
168 ; CHECK-NEXT: mov v0.s[1], w10
169 ; CHECK-NEXT: mov v1.s[1], w11
170 ; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s
171 ; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
172 ; CHECK-NEXT: mov w8, v0.s[1]
173 ; CHECK-NEXT: fmov w9, s0
174 ; CHECK-NEXT: strb w8, [x2, #1]
175 ; CHECK-NEXT: strb w9, [x2]
176 ; CHECK-NEXT: ret
177 %x = load <2 x i8>, <2 x i8>* %px
178 %y = load <2 x i8>, <2 x i8>* %py
179 %z = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
180 store <2 x i8> %z, <2 x i8>* %pz
181 ret void
182 }
184 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
185 ; CHECK-LABEL: v4i16:
186 ; CHECK: // %bb.0:
187 ; CHECK-NEXT: ldr d0, [x0]
188 ; CHECK-NEXT: ldr d1, [x1]
189 ; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h
190 ; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
191 ; CHECK-NEXT: str d0, [x2]
192 ; CHECK-NEXT: ret
193 %x = load <4 x i16>, <4 x i16>* %px
194 %y = load <4 x i16>, <4 x i16>* %py
195 %z = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
196 store <4 x i16> %z, <4 x i16>* %pz
197 ret void
198 }
200 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
201 ; CHECK-LABEL: v2i16:
202 ; CHECK: // %bb.0:
203 ; CHECK-NEXT: ldrh w8, [x0]
204 ; CHECK-NEXT: ldrh w9, [x1]
205 ; CHECK-NEXT: ldrh w10, [x0, #2]
206 ; CHECK-NEXT: ldrh w11, [x1, #2]
207 ; CHECK-NEXT: fmov s0, w8
208 ; CHECK-NEXT: fmov s1, w9
209 ; CHECK-NEXT: mov v0.s[1], w10
210 ; CHECK-NEXT: mov v1.s[1], w11
211 ; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s
212 ; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
213 ; CHECK-NEXT: mov w8, v0.s[1]
214 ; CHECK-NEXT: fmov w9, s0
215 ; CHECK-NEXT: strh w8, [x2, #2]
216 ; CHECK-NEXT: strh w9, [x2]
217 ; CHECK-NEXT: ret
218 %x = load <2 x i16>, <2 x i16>* %px
219 %y = load <2 x i16>, <2 x i16>* %py
220 %z = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
221 store <2 x i16> %z, <2 x i16>* %pz
222 ret void
223 }
225 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
226 ; CHECK-LABEL: v12i8:
227 ; CHECK: // %bb.0:
228 ; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b
229 ; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
230 ; CHECK-NEXT: ret
231 %z = call <12 x i8> @llvm.usub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
232 ret <12 x i8> %z
233 }
235 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
236 ; CHECK-LABEL: v12i16:
237 ; CHECK: // %bb.0:
238 ; CHECK-NEXT: ldp q0, q1, [x0]
239 ; CHECK-NEXT: ldp q3, q2, [x1]
240 ; CHECK-NEXT: umax v1.8h, v1.8h, v2.8h
241 ; CHECK-NEXT: umax v0.8h, v0.8h, v3.8h
242 ; CHECK-NEXT: sub v1.8h, v1.8h, v2.8h
243 ; CHECK-NEXT: sub v0.8h, v0.8h, v3.8h
244 ; CHECK-NEXT: str q0, [x2]
245 ; CHECK-NEXT: str d1, [x2, #16]
246 ; CHECK-NEXT: ret
247 %x = load <12 x i16>, <12 x i16>* %px
248 %y = load <12 x i16>, <12 x i16>* %py
249 %z = call <12 x i16> @llvm.usub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
250 store <12 x i16> %z, <12 x i16>* %pz
251 ret void
252 }
254 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
255 ; CHECK-LABEL: v1i8:
256 ; CHECK: // %bb.0:
257 ; CHECK-NEXT: ldr b0, [x0]
258 ; CHECK-NEXT: ldr b1, [x1]
259 ; CHECK-NEXT: umax v0.8b, v0.8b, v1.8b
260 ; CHECK-NEXT: sub v0.8b, v0.8b, v1.8b
261 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
262 ; CHECK-NEXT: ret
263 %x = load <1 x i8>, <1 x i8>* %px
264 %y = load <1 x i8>, <1 x i8>* %py
265 %z = call <1 x i8> @llvm.usub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
266 store <1 x i8> %z, <1 x i8>* %pz
267 ret void
268 }
270 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
271 ; CHECK-LABEL: v1i16:
272 ; CHECK: // %bb.0:
273 ; CHECK-NEXT: ldr h0, [x0]
274 ; CHECK-NEXT: ldr h1, [x1]
275 ; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h
276 ; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
277 ; CHECK-NEXT: str h0, [x2]
278 ; CHECK-NEXT: ret
279 %x = load <1 x i16>, <1 x i16>* %px
280 %y = load <1 x i16>, <1 x i16>* %py
281 %z = call <1 x i16> @llvm.usub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
282 store <1 x i16> %z, <1 x i16>* %pz
283 ret void
284 }
286 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
287 ; CHECK-LABEL: v16i4:
288 ; CHECK: // %bb.0:
289 ; CHECK-NEXT: movi v2.16b, #15
290 ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
291 ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
292 ; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b
293 ; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
294 ; CHECK-NEXT: ret
295 %z = call <16 x i4> @llvm.usub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
296 ret <16 x i4> %z
297 }
299 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
300 ; CHECK-LABEL: v16i1:
301 ; CHECK: // %bb.0:
302 ; CHECK-NEXT: movi v2.16b, #1
303 ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
304 ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
305 ; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b
306 ; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
307 ; CHECK-NEXT: ret
308 %z = call <16 x i1> @llvm.usub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
309 ret <16 x i1> %z
310 }
312 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
313 ; CHECK-LABEL: v2i32:
314 ; CHECK: // %bb.0:
315 ; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s
316 ; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
317 ; CHECK-NEXT: ret
318 %z = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
319 ret <2 x i32> %z
320 }
322 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
323 ; CHECK-LABEL: v4i32:
324 ; CHECK: // %bb.0:
325 ; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
326 ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
327 ; CHECK-NEXT: ret
328 %z = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
329 ret <4 x i32> %z
330 }
332 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
333 ; CHECK-LABEL: v8i32:
334 ; CHECK: // %bb.0:
335 ; CHECK-NEXT: umax v0.4s, v0.4s, v2.4s
336 ; CHECK-NEXT: umax v1.4s, v1.4s, v3.4s
337 ; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s
338 ; CHECK-NEXT: sub v1.4s, v1.4s, v3.4s
339 ; CHECK-NEXT: ret
340 %z = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
341 ret <8 x i32> %z
342 }
344 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
345 ; CHECK-LABEL: v16i32:
346 ; CHECK: // %bb.0:
347 ; CHECK-NEXT: umax v0.4s, v0.4s, v4.4s
348 ; CHECK-NEXT: umax v1.4s, v1.4s, v5.4s
349 ; CHECK-NEXT: umax v2.4s, v2.4s, v6.4s
350 ; CHECK-NEXT: umax v3.4s, v3.4s, v7.4s
351 ; CHECK-NEXT: sub v0.4s, v0.4s, v4.4s
352 ; CHECK-NEXT: sub v1.4s, v1.4s, v5.4s
353 ; CHECK-NEXT: sub v2.4s, v2.4s, v6.4s
354 ; CHECK-NEXT: sub v3.4s, v3.4s, v7.4s
355 ; CHECK-NEXT: ret
356 %z = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
357 ret <16 x i32> %z
358 }
360 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
361 ; CHECK-LABEL: v2i64:
362 ; CHECK: // %bb.0:
363 ; CHECK-NEXT: sub v1.2d, v0.2d, v1.2d
364 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
365 ; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
366 ; CHECK-NEXT: ret
367 %z = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
368 ret <2 x i64> %z
369 }
371 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
372 ; CHECK-LABEL: v4i64:
373 ; CHECK: // %bb.0:
374 ; CHECK-NEXT: sub v2.2d, v0.2d, v2.2d
375 ; CHECK-NEXT: sub v3.2d, v1.2d, v3.2d
376 ; CHECK-NEXT: cmhi v0.2d, v2.2d, v0.2d
377 ; CHECK-NEXT: cmhi v1.2d, v3.2d, v1.2d
378 ; CHECK-NEXT: bic v0.16b, v2.16b, v0.16b
379 ; CHECK-NEXT: bic v1.16b, v3.16b, v1.16b
380 ; CHECK-NEXT: ret
381 %z = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
382 ret <4 x i64> %z
383 }
385 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
386 ; CHECK-LABEL: v8i64:
387 ; CHECK: // %bb.0:
388 ; CHECK-NEXT: sub v4.2d, v0.2d, v4.2d
389 ; CHECK-NEXT: sub v5.2d, v1.2d, v5.2d
390 ; CHECK-NEXT: sub v6.2d, v2.2d, v6.2d
391 ; CHECK-NEXT: sub v7.2d, v3.2d, v7.2d
392 ; CHECK-NEXT: cmhi v0.2d, v4.2d, v0.2d
393 ; CHECK-NEXT: cmhi v1.2d, v5.2d, v1.2d
394 ; CHECK-NEXT: cmhi v2.2d, v6.2d, v2.2d
395 ; CHECK-NEXT: cmhi v3.2d, v7.2d, v3.2d
396 ; CHECK-NEXT: bic v0.16b, v4.16b, v0.16b
397 ; CHECK-NEXT: bic v1.16b, v5.16b, v1.16b
398 ; CHECK-NEXT: bic v2.16b, v6.16b, v2.16b
399 ; CHECK-NEXT: bic v3.16b, v7.16b, v3.16b
400 ; CHECK-NEXT: ret
401 %z = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
402 ret <8 x i64> %z
403 }
405 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
406 ; CHECK-LABEL: v2i128:
407 ; CHECK: // %bb.0:
408 ; CHECK-NEXT: subs x8, x2, x6
409 ; CHECK-NEXT: sbcs x9, x3, x7
410 ; CHECK-NEXT: cmp x8, x2
411 ; CHECK-NEXT: cset w10, hi
412 ; CHECK-NEXT: cmp x9, x3
413 ; CHECK-NEXT: cset w11, hi
414 ; CHECK-NEXT: csel w10, w10, w11, eq
415 ; CHECK-NEXT: cmp w10, #0 // =0
416 ; CHECK-NEXT: csel x3, xzr, x9, ne
417 ; CHECK-NEXT: csel x2, xzr, x8, ne
418 ; CHECK-NEXT: subs x8, x0, x4
419 ; CHECK-NEXT: sbcs x9, x1, x5
420 ; CHECK-NEXT: cmp x8, x0
421 ; CHECK-NEXT: cset w10, hi
422 ; CHECK-NEXT: cmp x9, x1
423 ; CHECK-NEXT: cset w11, hi
424 ; CHECK-NEXT: csel w10, w10, w11, eq
425 ; CHECK-NEXT: cmp w10, #0 // =0
426 ; CHECK-NEXT: csel x8, xzr, x8, ne
427 ; CHECK-NEXT: csel x1, xzr, x9, ne
428 ; CHECK-NEXT: fmov d0, x8
429 ; CHECK-NEXT: mov v0.d[1], x1
430 ; CHECK-NEXT: fmov x0, d0
431 ; CHECK-NEXT: ret
432 %z = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
433 ret <2 x i128> %z
434 }