| blob | 2beebf0e310c714add2e12e2aa9ce13c510a29c7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
3 ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
4 ; RUN: < %s | FileCheck %s
6 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
7 ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \
8 ; RUN: < %s | FileCheck %s --check-prefix=P9BE
10 ; Function Attrs: norecurse nounwind readonly
11 define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
12 ; CHECK-LABEL: test_pre_inc_disable_1:
13 ; CHECK: # %bb.0: # %entry
14 ; CHECK-NEXT: lfd f0, 0(r5)
15 ; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha
16 ; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l
17 ; CHECK-NEXT: lxvx v2, 0, r5
18 ; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha
19 ; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l
20 ; CHECK-NEXT: lxvx v4, 0, r5
21 ; CHECK-NEXT: xxpermdi v5, f0, f0, 2
22 ; CHECK-NEXT: xxlxor v3, v3, v3
23 ; CHECK-NEXT: li r5, 4
24 ; CHECK-NEXT: vperm v0, v3, v5, v2
25 ; CHECK-NEXT: mtctr r5
26 ; CHECK-NEXT: li r5, 0
27 ; CHECK-NEXT: vperm v1, v5, v3, v4
28 ; CHECK-NEXT: li r6, 0
29 ; CHECK-NEXT: xvnegsp v5, v0
30 ; CHECK-NEXT: xvnegsp v0, v1
31 ; CHECK-NEXT: .p2align 4
32 ; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader
33 ; CHECK-NEXT: #
34 ; CHECK-NEXT: lfd f0, 0(r3)
35 ; CHECK-NEXT: xxpermdi v1, f0, f0, 2
36 ; CHECK-NEXT: vperm v6, v1, v3, v4
37 ; CHECK-NEXT: vperm v1, v3, v1, v2
38 ; CHECK-NEXT: xvnegsp v1, v1
39 ; CHECK-NEXT: xvnegsp v6, v6
40 ; CHECK-NEXT: vabsduw v1, v1, v5
41 ; CHECK-NEXT: vabsduw v6, v6, v0
42 ; CHECK-NEXT: vadduwm v1, v6, v1
43 ; CHECK-NEXT: xxswapd v6, v1
44 ; CHECK-NEXT: vadduwm v1, v1, v6
45 ; CHECK-NEXT: xxspltw v6, v1, 2
46 ; CHECK-NEXT: vadduwm v1, v1, v6
47 ; CHECK-NEXT: vextuwrx r7, r5, v1
48 ; CHECK-NEXT: lfdx f0, r3, r4
49 ; CHECK-NEXT: add r6, r7, r6
50 ; CHECK-NEXT: add r7, r3, r4
51 ; CHECK-NEXT: xxpermdi v1, f0, f0, 2
52 ; CHECK-NEXT: add r3, r7, r4
53 ; CHECK-NEXT: vperm v6, v3, v1, v2
54 ; CHECK-NEXT: vperm v1, v1, v3, v4
55 ; CHECK-NEXT: xvnegsp v6, v6
56 ; CHECK-NEXT: xvnegsp v1, v1
57 ; CHECK-NEXT: vabsduw v6, v6, v5
58 ; CHECK-NEXT: vabsduw v1, v1, v0
59 ; CHECK-NEXT: vadduwm v1, v1, v6
60 ; CHECK-NEXT: xxswapd v6, v1
61 ; CHECK-NEXT: vadduwm v1, v1, v6
62 ; CHECK-NEXT: xxspltw v6, v1, 2
63 ; CHECK-NEXT: vadduwm v1, v1, v6
64 ; CHECK-NEXT: vextuwrx r8, r5, v1
65 ; CHECK-NEXT: add r6, r8, r6
66 ; CHECK-NEXT: bdnz .LBB0_1
67 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
68 ; CHECK-NEXT: extsw r3, r6
69 ; CHECK-NEXT: blr
70 ;
71 ; P9BE-LABEL: test_pre_inc_disable_1:
72 ; P9BE: # %bb.0: # %entry
73 ; P9BE-NEXT: lfd f0, 0(r5)
74 ; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha
75 ; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l
76 ; P9BE-NEXT: lxvx v2, 0, r5
77 ; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha
78 ; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l
79 ; P9BE-NEXT: lxvx v4, 0, r5
80 ; P9BE-NEXT: li r5, 4
81 ; P9BE-NEXT: xxlor v5, vs0, vs0
82 ; P9BE-NEXT: xxlxor v3, v3, v3
83 ; P9BE-NEXT: vperm v0, v3, v5, v2
84 ; P9BE-NEXT: mtctr r5
85 ; P9BE-NEXT: li r5, 0
86 ; P9BE-NEXT: vperm v1, v3, v5, v4
87 ; P9BE-NEXT: li r6, 0
88 ; P9BE-NEXT: xvnegsp v5, v0
89 ; P9BE-NEXT: xvnegsp v0, v1
90 ; P9BE-NEXT: .p2align 4
91 ; P9BE-NEXT: .LBB0_1: # %for.cond1.preheader
92 ; P9BE-NEXT: #
93 ; P9BE-NEXT: lfd f0, 0(r3)
94 ; P9BE-NEXT: xxlor v1, vs0, vs0
95 ; P9BE-NEXT: vperm v6, v3, v1, v4
96 ; P9BE-NEXT: vperm v1, v3, v1, v2
97 ; P9BE-NEXT: xvnegsp v1, v1
98 ; P9BE-NEXT: xvnegsp v6, v6
99 ; P9BE-NEXT: vabsduw v1, v1, v5
100 ; P9BE-NEXT: vabsduw v6, v6, v0
101 ; P9BE-NEXT: vadduwm v1, v6, v1
102 ; P9BE-NEXT: xxswapd v6, v1
103 ; P9BE-NEXT: vadduwm v1, v1, v6
104 ; P9BE-NEXT: xxspltw v6, v1, 1
105 ; P9BE-NEXT: vadduwm v1, v1, v6
106 ; P9BE-NEXT: vextuwlx r7, r5, v1
107 ; P9BE-NEXT: lfdx f0, r3, r4
108 ; P9BE-NEXT: add r6, r7, r6
109 ; P9BE-NEXT: add r7, r3, r4
110 ; P9BE-NEXT: xxlor v1, vs0, vs0
111 ; P9BE-NEXT: add r3, r7, r4
112 ; P9BE-NEXT: vperm v6, v3, v1, v2
113 ; P9BE-NEXT: vperm v1, v3, v1, v4
114 ; P9BE-NEXT: xvnegsp v6, v6
115 ; P9BE-NEXT: xvnegsp v1, v1
116 ; P9BE-NEXT: vabsduw v6, v6, v5
117 ; P9BE-NEXT: vabsduw v1, v1, v0
118 ; P9BE-NEXT: vadduwm v1, v1, v6
119 ; P9BE-NEXT: xxswapd v6, v1
120 ; P9BE-NEXT: vadduwm v1, v1, v6
121 ; P9BE-NEXT: xxspltw v6, v1, 1
122 ; P9BE-NEXT: vadduwm v1, v1, v6
123 ; P9BE-NEXT: vextuwlx r8, r5, v1
124 ; P9BE-NEXT: add r6, r8, r6
125 ; P9BE-NEXT: bdnz .LBB0_1
126 ; P9BE-NEXT: # %bb.2: # %for.cond.cleanup
127 ; P9BE-NEXT: extsw r3, r6
128 ; P9BE-NEXT: blr
129 entry:
130 %idx.ext = sext i32 %i_stride_pix1 to i64
131 %0 = bitcast i8* %pix2 to <8 x i8>*
132 %1 = load <8 x i8>, <8 x i8>* %0, align 1
133 %2 = zext <8 x i8> %1 to <8 x i32>
134 br label %for.cond1.preheader
136 for.cond1.preheader: ; preds = %for.cond1.preheader, %entry
137 %y.024 = phi i32 [ 0, %entry ], [ %inc9.1, %for.cond1.preheader ]
138 %i_sum.023 = phi i32 [ 0, %entry ], [ %op.extra.1, %for.cond1.preheader ]
139 %pix1.addr.022 = phi i8* [ %pix1, %entry ], [ %add.ptr.1, %for.cond1.preheader ]
140 %3 = bitcast i8* %pix1.addr.022 to <8 x i8>*
141 %4 = load <8 x i8>, <8 x i8>* %3, align 1
142 %5 = zext <8 x i8> %4 to <8 x i32>
143 %6 = sub nsw <8 x i32> %5, %2
144 %7 = icmp slt <8 x i32> %6, zeroinitializer
145 %8 = sub nsw <8 x i32> zeroinitializer, %6
146 %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
147 %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
148 %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
149 %rdx.shuf32 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
150 %bin.rdx33 = add nsw <8 x i32> %bin.rdx, %rdx.shuf32
151 %rdx.shuf34 = shufflevector <8 x i32> %bin.rdx33, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
152 %bin.rdx35 = add nsw <8 x i32> %bin.rdx33, %rdx.shuf34
153 %10 = extractelement <8 x i32> %bin.rdx35, i32 0
154 %op.extra = add nsw i32 %10, %i_sum.023
155 %add.ptr = getelementptr inbounds i8, i8* %pix1.addr.022, i64 %idx.ext
156 %11 = bitcast i8* %add.ptr to <8 x i8>*
157 %12 = load <8 x i8>, <8 x i8>* %11, align 1
158 %13 = zext <8 x i8> %12 to <8 x i32>
159 %14 = sub nsw <8 x i32> %13, %2
160 %15 = icmp slt <8 x i32> %14, zeroinitializer
161 %16 = sub nsw <8 x i32> zeroinitializer, %14
162 %17 = select <8 x i1> %15, <8 x i32> %16, <8 x i32> %14
163 %rdx.shuf.1 = shufflevector <8 x i32> %17, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
164 %bin.rdx.1 = add nsw <8 x i32> %17, %rdx.shuf.1
165 %rdx.shuf32.1 = shufflevector <8 x i32> %bin.rdx.1, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
166 %bin.rdx33.1 = add nsw <8 x i32> %bin.rdx.1, %rdx.shuf32.1
167 %rdx.shuf34.1 = shufflevector <8 x i32> %bin.rdx33.1, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
168 %bin.rdx35.1 = add nsw <8 x i32> %bin.rdx33.1, %rdx.shuf34.1
169 %18 = extractelement <8 x i32> %bin.rdx35.1, i32 0
170 %op.extra.1 = add nsw i32 %18, %op.extra
171 %add.ptr.1 = getelementptr inbounds i8, i8* %add.ptr, i64 %idx.ext
172 %inc9.1 = add nuw nsw i32 %y.024, 2
173 %exitcond.1 = icmp eq i32 %inc9.1, 8
174 br i1 %exitcond.1, label %for.cond.cleanup, label %for.cond1.preheader
176 for.cond.cleanup: ; preds = %for.cond1.preheader
177 ret i32 %op.extra.1
178 }
180 ; Function Attrs: norecurse nounwind readonly
181 define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
182 ; CHECK-LABEL: test_pre_inc_disable_2:
183 ; CHECK: # %bb.0: # %entry
184 ; CHECK-NEXT: lfd f0, 0(r3)
185 ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
186 ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
187 ; CHECK-NEXT: lxvx v4, 0, r3
188 ; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha
189 ; CHECK-NEXT: xxpermdi v2, f0, f0, 2
190 ; CHECK-NEXT: lfd f0, 0(r4)
191 ; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l
192 ; CHECK-NEXT: xxlxor v3, v3, v3
193 ; CHECK-NEXT: lxvx v0, 0, r3
194 ; CHECK-NEXT: xxpermdi v1, f0, f0, 2
195 ; CHECK-NEXT: vperm v5, v2, v3, v4
196 ; CHECK-NEXT: vperm v2, v3, v2, v0
197 ; CHECK-NEXT: vperm v0, v3, v1, v0
198 ; CHECK-NEXT: vperm v3, v1, v3, v4
199 ; CHECK-NEXT: vabsduw v2, v2, v0
200 ; CHECK-NEXT: vabsduw v3, v5, v3
201 ; CHECK-NEXT: vadduwm v2, v3, v2
202 ; CHECK-NEXT: xxswapd v3, v2
203 ; CHECK-NEXT: li r3, 0
204 ; CHECK-NEXT: vadduwm v2, v2, v3
205 ; CHECK-NEXT: xxspltw v3, v2, 2
206 ; CHECK-NEXT: vadduwm v2, v2, v3
207 ; CHECK-NEXT: vextuwrx r3, r3, v2
208 ; CHECK-NEXT: extsw r3, r3
209 ; CHECK-NEXT: blr
210 ;
211 ; P9BE-LABEL: test_pre_inc_disable_2:
212 ; P9BE: # %bb.0: # %entry
213 ; P9BE-NEXT: lfd f0, 0(r3)
214 ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
215 ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
216 ; P9BE-NEXT: lxvx v4, 0, r3
217 ; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha
218 ; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l
219 ; P9BE-NEXT: xxlor v2, vs0, vs0
220 ; P9BE-NEXT: lfd f0, 0(r4)
221 ; P9BE-NEXT: lxvx v0, 0, r3
222 ; P9BE-NEXT: xxlxor v3, v3, v3
223 ; P9BE-NEXT: xxlor v1, vs0, vs0
224 ; P9BE-NEXT: vperm v5, v3, v2, v4
225 ; P9BE-NEXT: vperm v2, v3, v2, v0
226 ; P9BE-NEXT: vperm v0, v3, v1, v0
227 ; P9BE-NEXT: vperm v3, v3, v1, v4
228 ; P9BE-NEXT: vabsduw v2, v2, v0
229 ; P9BE-NEXT: vabsduw v3, v5, v3
230 ; P9BE-NEXT: vadduwm v2, v3, v2
231 ; P9BE-NEXT: xxswapd v3, v2
232 ; P9BE-NEXT: vadduwm v2, v2, v3
233 ; P9BE-NEXT: xxspltw v3, v2, 1
234 ; P9BE-NEXT: vadduwm v2, v2, v3
235 ; P9BE-NEXT: li r3, 0
236 ; P9BE-NEXT: vextuwlx r3, r3, v2
237 ; P9BE-NEXT: extsw r3, r3
238 ; P9BE-NEXT: blr
239 entry:
240 %0 = bitcast i8* %pix1 to <8 x i8>*
241 %1 = load <8 x i8>, <8 x i8>* %0, align 1
242 %2 = zext <8 x i8> %1 to <8 x i32>
243 %3 = bitcast i8* %pix2 to <8 x i8>*
244 %4 = load <8 x i8>, <8 x i8>* %3, align 1
245 %5 = zext <8 x i8> %4 to <8 x i32>
246 %6 = sub nsw <8 x i32> %2, %5
247 %7 = icmp slt <8 x i32> %6, zeroinitializer
248 %8 = sub nsw <8 x i32> zeroinitializer, %6
249 %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
250 %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
251 %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
252 %rdx.shuf12 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
253 %bin.rdx13 = add nsw <8 x i32> %bin.rdx, %rdx.shuf12
254 %rdx.shuf14 = shufflevector <8 x i32> %bin.rdx13, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
255 %bin.rdx15 = add nsw <8 x i32> %bin.rdx13, %rdx.shuf14
256 %10 = extractelement <8 x i32> %bin.rdx15, i32 0
257 ret i32 %10
258 }
261 ; Generated from C source:
262 ;
263 ;#include <stdint.h>
264 ;#include <stdlib.h>
265 ;int test_pre_inc_disable_1( uint8_t *pix1, int i_stride_pix1, uint8_t *pix2 ) {
266 ; int i_sum = 0;
267 ; for( int y = 0; y < 8; y++ ) {
268 ; for( int x = 0; x < 8; x++) {
269 ; i_sum += abs( pix1[x] - pix2[x] )
270 ; }
271 ; pix1 += i_stride_pix1;
272 ; }
273 ; return i_sum;
274 ;}
276 ;int test_pre_inc_disable_2( uint8_t *pix1, uint8_t *pix2 ) {
277 ; int i_sum = 0;
278 ; for( int x = 0; x < 8; x++ ) {
279 ; i_sum += abs( pix1[x] - pix2[x] );
280 ; }
281 ;
282 ; return i_sum;
283 ;}
285 define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
286 ; CHECK-LABEL: test32:
287 ; CHECK: # %bb.0: # %entry
288 ; CHECK-NEXT: add r5, r3, r4
289 ; CHECK-NEXT: lfiwzx f0, r3, r4
290 ; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha
291 ; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l
292 ; CHECK-NEXT: lxvx v4, 0, r3
293 ; CHECK-NEXT: li r3, 4
294 ; CHECK-NEXT: xxpermdi v2, f0, f0, 2
295 ; CHECK-NEXT: lfiwzx f0, r5, r3
296 ; CHECK-NEXT: xxlxor v3, v3, v3
297 ; CHECK-NEXT: vperm v2, v2, v3, v4
298 ; CHECK-NEXT: xxpermdi v5, f0, f0, 2
299 ; CHECK-NEXT: vperm v3, v5, v3, v4
300 ; CHECK-NEXT: vspltisw v4, 8
301 ; CHECK-NEXT: vnegw v3, v3
302 ; CHECK-NEXT: vadduwm v4, v4, v4
303 ; CHECK-NEXT: vslw v3, v3, v4
304 ; CHECK-NEXT: vsubuwm v2, v3, v2
305 ; CHECK-NEXT: xxswapd vs0, v2
306 ; CHECK-NEXT: stxvx vs0, 0, r3
307 ; CHECK-NEXT: blr
308 ;
309 ; P9BE-LABEL: test32:
310 ; P9BE: # %bb.0: # %entry
311 ; P9BE-NEXT: add r5, r3, r4
312 ; P9BE-NEXT: lfiwzx f0, r3, r4
313 ; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
314 ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
315 ; P9BE-NEXT: lxvx v4, 0, r3
316 ; P9BE-NEXT: li r3, 4
317 ; P9BE-NEXT: xxsldwi v2, f0, f0, 1
318 ; P9BE-NEXT: lfiwzx f0, r5, r3
319 ; P9BE-NEXT: xxlxor v3, v3, v3
320 ; P9BE-NEXT: vperm v2, v3, v2, v4
321 ; P9BE-NEXT: xxsldwi v5, f0, f0, 1
322 ; P9BE-NEXT: vperm v3, v3, v5, v4
323 ; P9BE-NEXT: vspltisw v4, 8
324 ; P9BE-NEXT: vnegw v3, v3
325 ; P9BE-NEXT: vadduwm v4, v4, v4
326 ; P9BE-NEXT: vslw v3, v3, v4
327 ; P9BE-NEXT: vsubuwm v2, v3, v2
328 ; P9BE-NEXT: xxswapd vs0, v2
329 ; P9BE-NEXT: stxvx vs0, 0, r3
330 ; P9BE-NEXT: blr
331 entry:
332 %idx.ext63 = sext i32 %i_pix2 to i64
333 %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
334 %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
335 %0 = bitcast i8* %add.ptr64 to <4 x i8>*
336 %1 = load <4 x i8>, <4 x i8>* %0, align 1
337 %reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
338 %2 = zext <4 x i8> %reorder_shuffle117 to <4 x i32>
339 %3 = sub nsw <4 x i32> zeroinitializer, %2
340 %4 = bitcast i8* %arrayidx5.1 to <4 x i8>*
341 %5 = load <4 x i8>, <4 x i8>* %4, align 1
342 %reorder_shuffle115 = shufflevector <4 x i8> %5, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
343 %6 = zext <4 x i8> %reorder_shuffle115 to <4 x i32>
344 %7 = sub nsw <4 x i32> zeroinitializer, %6
345 %8 = shl nsw <4 x i32> %7, <i32 16, i32 16, i32 16, i32 16>
346 %9 = add nsw <4 x i32> %8, %3
347 %10 = sub nsw <4 x i32> %9, zeroinitializer
348 %11 = shufflevector <4 x i32> undef, <4 x i32> %10, <4 x i32> <i32 2, i32 7, i32 0, i32 5>
349 %12 = add nsw <4 x i32> zeroinitializer, %11
350 %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
351 store <4 x i32> %13, <4 x i32>* undef, align 16
352 ret void
353 }
355 define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
356 ; CHECK-LABEL: test16:
357 ; CHECK: # %bb.0: # %entry
358 ; CHECK-NEXT: sldi r4, r4, 1
359 ; CHECK-NEXT: lxsihzx v2, r3, r4
360 ; CHECK-NEXT: vsplth v2, v2, 3
361 ; CHECK-NEXT: xxlxor v3, v3, v3
362 ; CHECK-NEXT: vmrglh v2, v3, v2
363 ; CHECK-NEXT: vsplth v4, v3, 7
364 ; CHECK-NEXT: add r6, r3, r4
365 ; CHECK-NEXT: li r3, 16
366 ; CHECK-NEXT: vmrglw v2, v2, v4
367 ; CHECK-NEXT: lxsihzx v4, r6, r3
368 ; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha
369 ; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l
370 ; CHECK-NEXT: vsplth v4, v4, 3
371 ; CHECK-NEXT: vmrglh v3, v3, v4
372 ; CHECK-NEXT: lxvx v4, 0, r3
373 ; CHECK-NEXT: li r3, 0
374 ; CHECK-NEXT: vperm v2, v3, v2, v4
375 ; CHECK-NEXT: xxspltw v3, v2, 2
376 ; CHECK-NEXT: vadduwm v2, v2, v3
377 ; CHECK-NEXT: vextuwrx r3, r3, v2
378 ; CHECK-NEXT: cmpw cr0, r3, r5
379 ; CHECK-NEXT: bgelr+ cr0
380 ; CHECK-NEXT: # %bb.1: # %if.then
381 ;
382 ; P9BE-LABEL: test16:
383 ; P9BE: # %bb.0: # %entry
384 ; P9BE-NEXT: sldi r4, r4, 1
385 ; P9BE-NEXT: add r6, r3, r4
386 ; P9BE-NEXT: li r7, 16
387 ; P9BE-NEXT: lxsihzx v2, r6, r7
388 ; P9BE-NEXT: vsplth v2, v2, 3
389 ; P9BE-NEXT: lxsihzx v4, r3, r4
390 ; P9BE-NEXT: li r6, 0
391 ; P9BE-NEXT: sldi r6, r6, 48
392 ; P9BE-NEXT: mtvsrd v3, r6
393 ; P9BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha
394 ; P9BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
395 ; P9BE-NEXT: vmrghh v2, v3, v2
396 ; P9BE-NEXT: vsplth v4, v4, 3
397 ; P9BE-NEXT: vmrghh v4, v3, v4
398 ; P9BE-NEXT: vsplth v3, v3, 0
399 ; P9BE-NEXT: vmrghw v3, v3, v4
400 ; P9BE-NEXT: lxvx v4, 0, r3
401 ; P9BE-NEXT: li r3, 0
402 ; P9BE-NEXT: vperm v2, v3, v2, v4
403 ; P9BE-NEXT: xxspltw v3, v2, 1
404 ; P9BE-NEXT: vadduwm v2, v2, v3
405 ; P9BE-NEXT: vextuwlx r3, r3, v2
406 ; P9BE-NEXT: cmpw cr0, r3, r5
407 ; P9BE-NEXT: bgelr+ cr0
408 ; P9BE-NEXT: # %bb.1: # %if.then
409 entry:
410 %idxprom = sext i32 %delta to i64
411 %add14 = add nsw i32 %delta, 8
412 %idxprom15 = sext i32 %add14 to i64
413 br label %for.body
415 for.body: ; preds = %entry
416 %arrayidx8 = getelementptr inbounds i16, i16* %sums, i64 %idxprom
417 %0 = load i16, i16* %arrayidx8, align 2
418 %arrayidx16 = getelementptr inbounds i16, i16* %sums, i64 %idxprom15
419 %1 = load i16, i16* %arrayidx16, align 2
420 %2 = insertelement <4 x i16> undef, i16 %0, i32 2
421 %3 = insertelement <4 x i16> %2, i16 %1, i32 3
422 %4 = zext <4 x i16> %3 to <4 x i32>
423 %5 = sub nsw <4 x i32> zeroinitializer, %4
424 %6 = sub nsw <4 x i32> zeroinitializer, %5
425 %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
426 %bin.rdx = add <4 x i32> %7, zeroinitializer
427 %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
428 %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
429 %8 = extractelement <4 x i32> %bin.rdx55, i32 0
430 %op.extra = add nuw i32 %8, 0
431 %cmp25 = icmp slt i32 %op.extra, %thresh
432 br i1 %cmp25, label %if.then, label %if.end
434 if.then: ; preds = %for.body
435 unreachable
437 if.end: ; preds = %for.body
438 ret void
439 }
441 define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
442 ; CHECK-LABEL: test8:
443 ; CHECK: # %bb.0: # %entry
444 ; CHECK-NEXT: lxsibzx v2, r3, r4
445 ; CHECK-NEXT: add r6, r3, r4
446 ; CHECK-NEXT: li r3, 0
447 ; CHECK-NEXT: mtvsrd f0, r3
448 ; CHECK-NEXT: li r3, 8
449 ; CHECK-NEXT: xxswapd v3, vs0
450 ; CHECK-NEXT: vspltb v2, v2, 7
451 ; CHECK-NEXT: lxsibzx v5, r6, r3
452 ; CHECK-NEXT: vspltb v5, v5, 7
453 ; CHECK-NEXT: vmrglb v2, v3, v2
454 ; CHECK-NEXT: vspltb v4, v3, 15
455 ; CHECK-NEXT: vmrglb v3, v3, v5
456 ; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
457 ; CHECK-NEXT: vmrglh v2, v2, v4
458 ; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
459 ; CHECK-NEXT: vmrglw v2, v2, v4
460 ; CHECK-NEXT: vmrglh v3, v3, v4
461 ; CHECK-NEXT: vmrglw v3, v4, v3
462 ; CHECK-NEXT: lxvx v4, 0, r3
463 ; CHECK-NEXT: li r3, 0
464 ; CHECK-NEXT: vperm v2, v3, v2, v4
465 ; CHECK-NEXT: xxspltw v3, v2, 2
466 ; CHECK-NEXT: vadduwm v2, v2, v3
467 ; CHECK-NEXT: vextuwrx r3, r3, v2
468 ; CHECK-NEXT: cmpw cr0, r3, r5
469 ; CHECK-NEXT: bgelr+ cr0
470 ; CHECK-NEXT: # %bb.1: # %if.then
471 ;
472 ; P9BE-LABEL: test8:
473 ; P9BE: # %bb.0: # %entry
474 ; P9BE-NEXT: add r6, r3, r4
475 ; P9BE-NEXT: li r7, 8
476 ; P9BE-NEXT: lxsibzx v2, r6, r7
477 ; P9BE-NEXT: vspltb v2, v2, 7
478 ; P9BE-NEXT: lxsibzx v4, r3, r4
479 ; P9BE-NEXT: li r6, 0
480 ; P9BE-NEXT: sldi r6, r6, 56
481 ; P9BE-NEXT: mtvsrd v3, r6
482 ; P9BE-NEXT: vmrghb v2, v3, v2
483 ; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
484 ; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
485 ; P9BE-NEXT: vspltb v4, v4, 7
486 ; P9BE-NEXT: vmrghb v4, v3, v4
487 ; P9BE-NEXT: vspltb v3, v3, 0
488 ; P9BE-NEXT: vmrghh v4, v4, v3
489 ; P9BE-NEXT: xxspltw v3, v3, 0
490 ; P9BE-NEXT: vmrghw v2, v4, v2
491 ; P9BE-NEXT: lxvx v4, 0, r3
492 ; P9BE-NEXT: li r3, 0
493 ; P9BE-NEXT: vperm v2, v3, v2, v4
494 ; P9BE-NEXT: xxspltw v3, v2, 1
495 ; P9BE-NEXT: vadduwm v2, v2, v3
496 ; P9BE-NEXT: vextuwlx r3, r3, v2
497 ; P9BE-NEXT: cmpw cr0, r3, r5
498 ; P9BE-NEXT: bgelr+ cr0
499 ; P9BE-NEXT: # %bb.1: # %if.then
500 entry:
501 %idxprom = sext i32 %delta to i64
502 %add14 = add nsw i32 %delta, 8
503 %idxprom15 = sext i32 %add14 to i64
504 br label %for.body
506 for.body: ; preds = %entry
507 %arrayidx8 = getelementptr inbounds i8, i8* %sums, i64 %idxprom
508 %0 = load i8, i8* %arrayidx8, align 2
509 %arrayidx16 = getelementptr inbounds i8, i8* %sums, i64 %idxprom15
510 %1 = load i8, i8* %arrayidx16, align 2
511 %2 = insertelement <4 x i8> undef, i8 %0, i32 2
512 %3 = insertelement <4 x i8> %2, i8 %1, i32 3
513 %4 = zext <4 x i8> %3 to <4 x i32>
514 %5 = sub nsw <4 x i32> zeroinitializer, %4
515 %6 = sub nsw <4 x i32> zeroinitializer, %5
516 %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
517 %bin.rdx = add <4 x i32> %7, zeroinitializer
518 %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
519 %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
520 %8 = extractelement <4 x i32> %bin.rdx55, i32 0
521 %op.extra = add nuw i32 %8, 0
522 %cmp25 = icmp slt i32 %op.extra, %thresh
523 br i1 %cmp25, label %if.then, label %if.end
525 if.then: ; preds = %for.body
526 unreachable
528 if.end: ; preds = %for.body
529 ret void
530 }