| blob | f03d0696f217d79e062fcd6180021e3965077f5f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
16 ; CHECK-P8-NEXT: mtvsrd f0, r3
17 ; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
18 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
19 ; CHECK-P8-NEXT: xxswapd v2, vs0
20 ; CHECK-P8-NEXT: lvx v3, 0, r3
21 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
22 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
23 ; CHECK-P8-NEXT: blr
24 ;
25 ; CHECK-P9-LABEL: test2elt:
26 ; CHECK-P9: # %bb.0: # %entry
27 ; CHECK-P9-NEXT: mtvsrws v2, r3
28 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
29 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
30 ; CHECK-P9-NEXT: lxvx v3, 0, r3
31 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
32 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
33 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
34 ; CHECK-P9-NEXT: blr
35 ;
36 ; CHECK-BE-LABEL: test2elt:
37 ; CHECK-BE: # %bb.0: # %entry
38 ; CHECK-BE-NEXT: mtvsrws v2, r3
39 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
40 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
41 ; CHECK-BE-NEXT: lxvx v3, 0, r3
42 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
43 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
44 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
45 ; CHECK-BE-NEXT: blr
46 entry:
47 %0 = bitcast i32 %a.coerce to <2 x i16>
48 %1 = uitofp <2 x i16> %0 to <2 x double>
49 ret <2 x double> %1
50 }
52 define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
53 ; CHECK-P8-LABEL: test4elt:
54 ; CHECK-P8: # %bb.0: # %entry
55 ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
56 ; CHECK-P8-NEXT: mtvsrd f0, r4
57 ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
58 ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
59 ; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
60 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
61 ; CHECK-P8-NEXT: lvx v2, 0, r5
62 ; CHECK-P8-NEXT: xxswapd v3, vs0
63 ; CHECK-P8-NEXT: lvx v5, 0, r4
64 ; CHECK-P8-NEXT: li r4, 16
65 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
66 ; CHECK-P8-NEXT: vperm v3, v4, v3, v5
67 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2
68 ; CHECK-P8-NEXT: xvcvuxddp vs1, v3
69 ; CHECK-P8-NEXT: xxswapd vs0, vs0
70 ; CHECK-P8-NEXT: xxswapd vs1, vs1
71 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
72 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
73 ; CHECK-P8-NEXT: blr
74 ;
75 ; CHECK-P9-LABEL: test4elt:
76 ; CHECK-P9: # %bb.0: # %entry
77 ; CHECK-P9-NEXT: mtvsrd f0, r4
78 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
79 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
80 ; CHECK-P9-NEXT: lxvx v3, 0, r4
81 ; CHECK-P9-NEXT: xxswapd v2, vs0
82 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
83 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
84 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
85 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
86 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
87 ; CHECK-P9-NEXT: lxvx v3, 0, r4
88 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
89 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
90 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
91 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
92 ; CHECK-P9-NEXT: blr
93 ;
94 ; CHECK-BE-LABEL: test4elt:
95 ; CHECK-BE: # %bb.0: # %entry
96 ; CHECK-BE-NEXT: mtvsrd v2, r4
97 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
98 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
99 ; CHECK-BE-NEXT: lxvx v3, 0, r4
100 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
101 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
102 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
103 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
104 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
105 ; CHECK-BE-NEXT: lxvx v3, 0, r4
106 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
107 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
108 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
109 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
110 ; CHECK-BE-NEXT: blr
111 entry:
112 %0 = bitcast i64 %a.coerce to <4 x i16>
113 %1 = uitofp <4 x i16> %0 to <4 x double>
114 store <4 x double> %1, <4 x double>* %agg.result, align 32
115 ret void
116 }
118 define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
119 ; CHECK-P8-LABEL: test8elt:
120 ; CHECK-P8: # %bb.0: # %entry
121 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha
122 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_2@toc@ha
123 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
124 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l
125 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_2@toc@l
126 ; CHECK-P8-NEXT: lvx v3, 0, r4
127 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha
128 ; CHECK-P8-NEXT: lvx v5, 0, r5
129 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha
130 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l
131 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l
132 ; CHECK-P8-NEXT: lvx v0, 0, r4
133 ; CHECK-P8-NEXT: lvx v1, 0, r5
134 ; CHECK-P8-NEXT: li r4, 48
135 ; CHECK-P8-NEXT: li r5, 32
136 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
137 ; CHECK-P8-NEXT: vperm v5, v4, v2, v5
138 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0
139 ; CHECK-P8-NEXT: vperm v2, v4, v2, v1
140 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3
141 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5
142 ; CHECK-P8-NEXT: xvcvuxddp vs2, v0
143 ; CHECK-P8-NEXT: xvcvuxddp vs3, v2
144 ; CHECK-P8-NEXT: xxswapd vs0, vs0
145 ; CHECK-P8-NEXT: xxswapd vs1, vs1
146 ; CHECK-P8-NEXT: xxswapd vs2, vs2
147 ; CHECK-P8-NEXT: xxswapd vs3, vs3
148 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
149 ; CHECK-P8-NEXT: li r4, 16
150 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
151 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
152 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
153 ; CHECK-P8-NEXT: blr
154 ;
155 ; CHECK-P9-LABEL: test8elt:
156 ; CHECK-P9: # %bb.0: # %entry
157 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
158 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
159 ; CHECK-P9-NEXT: lxvx v3, 0, r4
160 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
161 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
162 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
163 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
164 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
165 ; CHECK-P9-NEXT: lxvx v3, 0, r4
166 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
167 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
168 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
169 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
170 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
171 ; CHECK-P9-NEXT: lxvx v3, 0, r4
172 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
173 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
174 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
175 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
176 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
177 ; CHECK-P9-NEXT: lxvx v3, 0, r4
178 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
179 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
180 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
181 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
182 ; CHECK-P9-NEXT: blr
183 ;
184 ; CHECK-BE-LABEL: test8elt:
185 ; CHECK-BE: # %bb.0: # %entry
186 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
187 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
188 ; CHECK-BE-NEXT: lxvx v3, 0, r4
189 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
190 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
191 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
192 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
193 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
194 ; CHECK-BE-NEXT: lxvx v3, 0, r4
195 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
196 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
197 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
198 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
199 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
200 ; CHECK-BE-NEXT: lxvx v3, 0, r4
201 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
202 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
203 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
204 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
205 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
206 ; CHECK-BE-NEXT: lxvx v3, 0, r4
207 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
208 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
209 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
210 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
211 ; CHECK-BE-NEXT: blr
212 entry:
213 %0 = uitofp <8 x i16> %a to <8 x double>
214 store <8 x double> %0, <8 x double>* %agg.result, align 64
215 ret void
216 }
218 define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
219 ; CHECK-P8-LABEL: test16elt:
220 ; CHECK-P8: # %bb.0: # %entry
221 ; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha
222 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha
223 ; CHECK-P8-NEXT: lvx v4, 0, r4
224 ; CHECK-P8-NEXT: xxlxor v3, v3, v3
225 ; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2@toc@l
226 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l
227 ; CHECK-P8-NEXT: lvx v5, 0, r6
228 ; CHECK-P8-NEXT: li r6, 16
229 ; CHECK-P8-NEXT: lvx v2, 0, r5
230 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha
231 ; CHECK-P8-NEXT: lvx v0, r4, r6
232 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha
233 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l
234 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l
235 ; CHECK-P8-NEXT: lvx v1, 0, r5
236 ; CHECK-P8-NEXT: li r5, 96
237 ; CHECK-P8-NEXT: lvx v8, 0, r4
238 ; CHECK-P8-NEXT: vperm v6, v3, v4, v2
239 ; CHECK-P8-NEXT: li r4, 112
240 ; CHECK-P8-NEXT: vperm v7, v3, v4, v5
241 ; CHECK-P8-NEXT: vperm v2, v3, v0, v2
242 ; CHECK-P8-NEXT: vperm v9, v3, v0, v1
243 ; CHECK-P8-NEXT: vperm v5, v3, v0, v5
244 ; CHECK-P8-NEXT: vperm v0, v3, v0, v8
245 ; CHECK-P8-NEXT: vperm v1, v3, v4, v1
246 ; CHECK-P8-NEXT: vperm v3, v3, v4, v8
247 ; CHECK-P8-NEXT: xvcvuxddp vs1, v2
248 ; CHECK-P8-NEXT: xvcvuxddp vs4, v9
249 ; CHECK-P8-NEXT: xvcvuxddp vs2, v5
250 ; CHECK-P8-NEXT: xvcvuxddp vs3, v0
251 ; CHECK-P8-NEXT: xvcvuxddp vs0, v7
252 ; CHECK-P8-NEXT: xvcvuxddp vs5, v3
253 ; CHECK-P8-NEXT: xvcvuxddp vs6, v6
254 ; CHECK-P8-NEXT: xxswapd vs1, vs1
255 ; CHECK-P8-NEXT: xvcvuxddp vs7, v1
256 ; CHECK-P8-NEXT: xxswapd vs4, vs4
257 ; CHECK-P8-NEXT: xxswapd vs2, vs2
258 ; CHECK-P8-NEXT: xxswapd vs3, vs3
259 ; CHECK-P8-NEXT: xxswapd vs0, vs0
260 ; CHECK-P8-NEXT: xxswapd vs5, vs5
261 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
262 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
263 ; CHECK-P8-NEXT: li r4, 80
264 ; CHECK-P8-NEXT: li r5, 64
265 ; CHECK-P8-NEXT: xxswapd vs2, vs7
266 ; CHECK-P8-NEXT: xxswapd vs3, vs6
267 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
268 ; CHECK-P8-NEXT: li r4, 48
269 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
270 ; CHECK-P8-NEXT: li r5, 32
271 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
272 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
273 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
274 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
275 ; CHECK-P8-NEXT: blr
276 ;
277 ; CHECK-P9-LABEL: test16elt:
278 ; CHECK-P9: # %bb.0: # %entry
279 ; CHECK-P9-NEXT: lxv v2, 16(r4)
280 ; CHECK-P9-NEXT: lxv v3, 0(r4)
281 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
282 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
283 ; CHECK-P9-NEXT: lxvx v4, 0, r4
284 ; CHECK-P9-NEXT: xxlxor v5, v5, v5
285 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
286 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
287 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
288 ; CHECK-P9-NEXT: xvcvuxddp vs0, v0
289 ; CHECK-P9-NEXT: lxvx v0, 0, r4
290 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
291 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
292 ; CHECK-P9-NEXT: vperm v1, v5, v3, v0
293 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
294 ; CHECK-P9-NEXT: xvcvuxddp vs1, v1
295 ; CHECK-P9-NEXT: lxvx v1, 0, r4
296 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
297 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
298 ; CHECK-P9-NEXT: vperm v6, v5, v3, v1
299 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
300 ; CHECK-P9-NEXT: xvcvuxddp vs2, v6
301 ; CHECK-P9-NEXT: lxvx v6, 0, r4
302 ; CHECK-P9-NEXT: vperm v3, v5, v3, v6
303 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
304 ; CHECK-P9-NEXT: xvcvuxddp vs3, v3
305 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
306 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
307 ; CHECK-P9-NEXT: vperm v3, v5, v2, v0
308 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
309 ; CHECK-P9-NEXT: vperm v3, v5, v2, v1
310 ; CHECK-P9-NEXT: vperm v2, v5, v2, v6
311 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
312 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
313 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
314 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
315 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
316 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
317 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
318 ; CHECK-P9-NEXT: blr
319 ;
320 ; CHECK-BE-LABEL: test16elt:
321 ; CHECK-BE: # %bb.0: # %entry
322 ; CHECK-BE-NEXT: lxv v2, 16(r4)
323 ; CHECK-BE-NEXT: lxv v3, 0(r4)
324 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
325 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
326 ; CHECK-BE-NEXT: lxvx v4, 0, r4
327 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
328 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
329 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
330 ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
331 ; CHECK-BE-NEXT: xvcvuxddp vs0, v0
332 ; CHECK-BE-NEXT: lxvx v0, 0, r4
333 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
334 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
335 ; CHECK-BE-NEXT: vperm v1, v5, v3, v0
336 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
337 ; CHECK-BE-NEXT: xvcvuxddp vs1, v1
338 ; CHECK-BE-NEXT: lxvx v1, 0, r4
339 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
340 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
341 ; CHECK-BE-NEXT: vperm v6, v5, v3, v1
342 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
343 ; CHECK-BE-NEXT: xvcvuxddp vs2, v6
344 ; CHECK-BE-NEXT: lxvx v6, 0, r4
345 ; CHECK-BE-NEXT: vperm v3, v5, v3, v6
346 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
347 ; CHECK-BE-NEXT: xvcvuxddp vs3, v3
348 ; CHECK-BE-NEXT: vperm v3, v2, v5, v4
349 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
350 ; CHECK-BE-NEXT: vperm v3, v5, v2, v0
351 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
352 ; CHECK-BE-NEXT: vperm v3, v5, v2, v1
353 ; CHECK-BE-NEXT: vperm v2, v5, v2, v6
354 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
355 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
356 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
357 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
358 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
359 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
360 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
361 ; CHECK-BE-NEXT: blr
362 entry:
363 %a = load <16 x i16>, <16 x i16>* %0, align 32
364 %1 = uitofp <16 x i16> %a to <16 x double>
365 store <16 x double> %1, <16 x double>* %agg.result, align 128
366 ret void
367 }
369 define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
370 ; CHECK-P8-LABEL: test2elt_signed:
371 ; CHECK-P8: # %bb.0: # %entry
372 ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
373 ; CHECK-P8-NEXT: mtvsrd f0, r3
374 ; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
375 ; CHECK-P8-NEXT: xxswapd v2, vs0
376 ; CHECK-P8-NEXT: lvx v3, 0, r3
377 ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
378 ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
379 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
380 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
381 ; CHECK-P8-NEXT: xxswapd v3, vs0
382 ; CHECK-P8-NEXT: vsld v2, v2, v3
383 ; CHECK-P8-NEXT: vsrad v2, v2, v3
384 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
385 ; CHECK-P8-NEXT: blr
386 ;
387 ; CHECK-P9-LABEL: test2elt_signed:
388 ; CHECK-P9: # %bb.0: # %entry
389 ; CHECK-P9-NEXT: mtvsrws v2, r3
390 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
391 ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
392 ; CHECK-P9-NEXT: lxvx v3, 0, r3
393 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
394 ; CHECK-P9-NEXT: vextsh2d v2, v2
395 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
396 ; CHECK-P9-NEXT: blr
397 ;
398 ; CHECK-BE-LABEL: test2elt_signed:
399 ; CHECK-BE: # %bb.0: # %entry
400 ; CHECK-BE-NEXT: mtvsrws v2, r3
401 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
402 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
403 ; CHECK-BE-NEXT: lxvx v3, 0, r3
404 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
405 ; CHECK-BE-NEXT: vextsh2d v2, v2
406 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
407 ; CHECK-BE-NEXT: blr
408 entry:
409 %0 = bitcast i32 %a.coerce to <2 x i16>
410 %1 = sitofp <2 x i16> %0 to <2 x double>
411 ret <2 x double> %1
412 }
414 define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
415 ; CHECK-P8-LABEL: test4elt_signed:
416 ; CHECK-P8: # %bb.0: # %entry
417 ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
418 ; CHECK-P8-NEXT: mtvsrd f0, r4
419 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
420 ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
421 ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
422 ; CHECK-P8-NEXT: lvx v2, 0, r5
423 ; CHECK-P8-NEXT: xxswapd v3, vs0
424 ; CHECK-P8-NEXT: lvx v4, 0, r4
425 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
426 ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
427 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
428 ; CHECK-P8-NEXT: li r4, 16
429 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
430 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
431 ; CHECK-P8-NEXT: xxswapd v4, vs0
432 ; CHECK-P8-NEXT: vsld v2, v2, v4
433 ; CHECK-P8-NEXT: vsld v3, v3, v4
434 ; CHECK-P8-NEXT: vsrad v2, v2, v4
435 ; CHECK-P8-NEXT: vsrad v3, v3, v4
436 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
437 ; CHECK-P8-NEXT: xvcvsxddp vs1, v3
438 ; CHECK-P8-NEXT: xxswapd vs0, vs0
439 ; CHECK-P8-NEXT: xxswapd vs1, vs1
440 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
441 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
442 ; CHECK-P8-NEXT: blr
443 ;
444 ; CHECK-P9-LABEL: test4elt_signed:
445 ; CHECK-P9: # %bb.0: # %entry
446 ; CHECK-P9-NEXT: mtvsrd f0, r4
447 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
448 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
449 ; CHECK-P9-NEXT: lxvx v3, 0, r4
450 ; CHECK-P9-NEXT: xxswapd v2, vs0
451 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
452 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
453 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
454 ; CHECK-P9-NEXT: vextsh2d v3, v3
455 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
456 ; CHECK-P9-NEXT: lxvx v3, 0, r4
457 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
458 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
459 ; CHECK-P9-NEXT: vextsh2d v2, v2
460 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
461 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
462 ; CHECK-P9-NEXT: blr
463 ;
464 ; CHECK-BE-LABEL: test4elt_signed:
465 ; CHECK-BE: # %bb.0: # %entry
466 ; CHECK-BE-NEXT: mtvsrd v2, r4
467 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
468 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
469 ; CHECK-BE-NEXT: lxvx v4, 0, r4
470 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
471 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
472 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
473 ; CHECK-BE-NEXT: vextsh2d v3, v3
474 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
475 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
476 ; CHECK-BE-NEXT: lxvx v3, 0, r4
477 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
478 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
479 ; CHECK-BE-NEXT: vextsh2d v2, v2
480 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
481 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
482 ; CHECK-BE-NEXT: blr
483 entry:
484 %0 = bitcast i64 %a.coerce to <4 x i16>
485 %1 = sitofp <4 x i16> %0 to <4 x double>
486 store <4 x double> %1, <4 x double>* %agg.result, align 32
487 ret void
488 }
490 define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
491 ; CHECK-P8-LABEL: test8elt_signed:
492 ; CHECK-P8: # %bb.0: # %entry
493 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_2@toc@ha
494 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha
495 ; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha
496 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_2@toc@l
497 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l
498 ; CHECK-P8-NEXT: addi r6, r6, .LCPI6_3@toc@l
499 ; CHECK-P8-NEXT: lvx v4, 0, r5
500 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_4@toc@ha
501 ; CHECK-P8-NEXT: lvx v3, 0, r4
502 ; CHECK-P8-NEXT: lvx v5, 0, r6
503 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
504 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_4@toc@l
505 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l
506 ; CHECK-P8-NEXT: lvx v0, 0, r5
507 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
508 ; CHECK-P8-NEXT: li r4, 48
509 ; CHECK-P8-NEXT: li r5, 32
510 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
511 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
512 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
513 ; CHECK-P8-NEXT: vperm v2, v2, v2, v0
514 ; CHECK-P8-NEXT: xxswapd v0, vs0
515 ; CHECK-P8-NEXT: vsld v3, v3, v0
516 ; CHECK-P8-NEXT: vsld v4, v4, v0
517 ; CHECK-P8-NEXT: vsld v5, v5, v0
518 ; CHECK-P8-NEXT: vsld v2, v2, v0
519 ; CHECK-P8-NEXT: vsrad v3, v3, v0
520 ; CHECK-P8-NEXT: vsrad v2, v2, v0
521 ; CHECK-P8-NEXT: vsrad v4, v4, v0
522 ; CHECK-P8-NEXT: vsrad v5, v5, v0
523 ; CHECK-P8-NEXT: xvcvsxddp vs2, v2
524 ; CHECK-P8-NEXT: xvcvsxddp vs0, v3
525 ; CHECK-P8-NEXT: xvcvsxddp vs1, v5
526 ; CHECK-P8-NEXT: xvcvsxddp vs3, v4
527 ; CHECK-P8-NEXT: xxswapd vs2, vs2
528 ; CHECK-P8-NEXT: xxswapd vs0, vs0
529 ; CHECK-P8-NEXT: xxswapd vs1, vs1
530 ; CHECK-P8-NEXT: xxswapd vs3, vs3
531 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
532 ; CHECK-P8-NEXT: li r4, 16
533 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
534 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
535 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
536 ; CHECK-P8-NEXT: blr
537 ;
538 ; CHECK-P9-LABEL: test8elt_signed:
539 ; CHECK-P9: # %bb.0: # %entry
540 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
541 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
542 ; CHECK-P9-NEXT: lxvx v3, 0, r4
543 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
544 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
545 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
546 ; CHECK-P9-NEXT: vextsh2d v3, v3
547 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
548 ; CHECK-P9-NEXT: lxvx v3, 0, r4
549 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
550 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
551 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
552 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
553 ; CHECK-P9-NEXT: vextsh2d v3, v3
554 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
555 ; CHECK-P9-NEXT: lxvx v3, 0, r4
556 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
557 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
558 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
559 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
560 ; CHECK-P9-NEXT: vextsh2d v3, v3
561 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
562 ; CHECK-P9-NEXT: lxvx v3, 0, r4
563 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
564 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
565 ; CHECK-P9-NEXT: vextsh2d v2, v2
566 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
567 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
568 ; CHECK-P9-NEXT: blr
569 ;
570 ; CHECK-BE-LABEL: test8elt_signed:
571 ; CHECK-BE: # %bb.0: # %entry
572 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
573 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
574 ; CHECK-BE-NEXT: lxvx v3, 0, r4
575 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
576 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
577 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
578 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
579 ; CHECK-BE-NEXT: vextsh2d v3, v3
580 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
581 ; CHECK-BE-NEXT: lxvx v3, 0, r4
582 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
583 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
584 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
585 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
586 ; CHECK-BE-NEXT: vextsh2d v3, v3
587 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
588 ; CHECK-BE-NEXT: lxvx v3, 0, r4
589 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
590 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
591 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
592 ; CHECK-BE-NEXT: stxv vs1, 48(r3)
593 ; CHECK-BE-NEXT: vextsh2d v3, v3
594 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
595 ; CHECK-BE-NEXT: lxvx v3, 0, r4
596 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
597 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
598 ; CHECK-BE-NEXT: vextsh2d v2, v2
599 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
600 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
601 ; CHECK-BE-NEXT: blr
602 entry:
603 %0 = sitofp <8 x i16> %a to <8 x double>
604 store <8 x double> %0, <8 x double>* %agg.result, align 64
605 ret void
606 }
608 define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
609 ; CHECK-P8-LABEL: test16elt_signed:
610 ; CHECK-P8: # %bb.0: # %entry
611 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_0@toc@ha
612 ; CHECK-P8-NEXT: addis r6, r2, .LCPI7_2@toc@ha
613 ; CHECK-P8-NEXT: lvx v4, 0, r4
614 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_0@toc@l
615 ; CHECK-P8-NEXT: addi r6, r6, .LCPI7_2@toc@l
616 ; CHECK-P8-NEXT: lvx v2, 0, r5
617 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_3@toc@ha
618 ; CHECK-P8-NEXT: lvx v3, 0, r6
619 ; CHECK-P8-NEXT: addis r6, r2, .LCPI7_4@toc@ha
620 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_3@toc@l
621 ; CHECK-P8-NEXT: addi r6, r6, .LCPI7_4@toc@l
622 ; CHECK-P8-NEXT: lvx v5, 0, r5
623 ; CHECK-P8-NEXT: lvx v0, 0, r6
624 ; CHECK-P8-NEXT: li r6, 16
625 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha
626 ; CHECK-P8-NEXT: lvx v7, r4, r6
627 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l
628 ; CHECK-P8-NEXT: vperm v1, v4, v4, v2
629 ; CHECK-P8-NEXT: li r4, 112
630 ; CHECK-P8-NEXT: vperm v6, v4, v4, v3
631 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
632 ; CHECK-P8-NEXT: li r5, 96
633 ; CHECK-P8-NEXT: vperm v8, v4, v4, v5
634 ; CHECK-P8-NEXT: vperm v4, v4, v4, v0
635 ; CHECK-P8-NEXT: vperm v5, v7, v7, v5
636 ; CHECK-P8-NEXT: xxswapd v9, vs0
637 ; CHECK-P8-NEXT: vperm v0, v7, v7, v0
638 ; CHECK-P8-NEXT: vperm v2, v7, v7, v2
639 ; CHECK-P8-NEXT: vperm v3, v7, v7, v3
640 ; CHECK-P8-NEXT: vsld v1, v1, v9
641 ; CHECK-P8-NEXT: vsld v6, v6, v9
642 ; CHECK-P8-NEXT: vsld v5, v5, v9
643 ; CHECK-P8-NEXT: vsld v0, v0, v9
644 ; CHECK-P8-NEXT: vsld v2, v2, v9
645 ; CHECK-P8-NEXT: vsld v3, v3, v9
646 ; CHECK-P8-NEXT: vsrad v5, v5, v9
647 ; CHECK-P8-NEXT: vsrad v0, v0, v9
648 ; CHECK-P8-NEXT: vsld v7, v8, v9
649 ; CHECK-P8-NEXT: vsld v4, v4, v9
650 ; CHECK-P8-NEXT: vsrad v2, v2, v9
651 ; CHECK-P8-NEXT: vsrad v3, v3, v9
652 ; CHECK-P8-NEXT: xvcvsxddp vs2, v5
653 ; CHECK-P8-NEXT: xvcvsxddp vs3, v0
654 ; CHECK-P8-NEXT: vsrad v1, v1, v9
655 ; CHECK-P8-NEXT: vsrad v6, v6, v9
656 ; CHECK-P8-NEXT: vsrad v7, v7, v9
657 ; CHECK-P8-NEXT: vsrad v4, v4, v9
658 ; CHECK-P8-NEXT: xvcvsxddp vs1, v2
659 ; CHECK-P8-NEXT: xxswapd vs2, vs2
660 ; CHECK-P8-NEXT: xvcvsxddp vs4, v3
661 ; CHECK-P8-NEXT: xxswapd vs3, vs3
662 ; CHECK-P8-NEXT: xvcvsxddp vs0, v7
663 ; CHECK-P8-NEXT: xvcvsxddp vs5, v4
664 ; CHECK-P8-NEXT: xvcvsxddp vs6, v1
665 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
666 ; CHECK-P8-NEXT: li r4, 80
667 ; CHECK-P8-NEXT: xvcvsxddp vs7, v6
668 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
669 ; CHECK-P8-NEXT: li r5, 64
670 ; CHECK-P8-NEXT: xxswapd vs1, vs1
671 ; CHECK-P8-NEXT: xxswapd vs4, vs4
672 ; CHECK-P8-NEXT: xxswapd vs0, vs0
673 ; CHECK-P8-NEXT: xxswapd vs5, vs5
674 ; CHECK-P8-NEXT: xxswapd vs3, vs6
675 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
676 ; CHECK-P8-NEXT: li r4, 48
677 ; CHECK-P8-NEXT: xxswapd vs2, vs7
678 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
679 ; CHECK-P8-NEXT: li r5, 32
680 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
681 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
682 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r6
683 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
684 ; CHECK-P8-NEXT: blr
685 ;
686 ; CHECK-P9-LABEL: test16elt_signed:
687 ; CHECK-P9: # %bb.0: # %entry
688 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha
689 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l
690 ; CHECK-P9-NEXT: lxv v2, 0(r4)
691 ; CHECK-P9-NEXT: lxvx v3, 0, r5
692 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha
693 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l
694 ; CHECK-P9-NEXT: lxvx v5, 0, r5
695 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha
696 ; CHECK-P9-NEXT: vperm v4, v2, v2, v3
697 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l
698 ; CHECK-P9-NEXT: vextsh2d v4, v4
699 ; CHECK-P9-NEXT: lxvx v0, 0, r5
700 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha
701 ; CHECK-P9-NEXT: xvcvsxddp vs0, v4
702 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5
703 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l
704 ; CHECK-P9-NEXT: lxvx v1, 0, r5
705 ; CHECK-P9-NEXT: vextsh2d v4, v4
706 ; CHECK-P9-NEXT: xvcvsxddp vs1, v4
707 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0
708 ; CHECK-P9-NEXT: vperm v2, v2, v2, v1
709 ; CHECK-P9-NEXT: vextsh2d v4, v4
710 ; CHECK-P9-NEXT: xvcvsxddp vs2, v4
711 ; CHECK-P9-NEXT: lxv v4, 16(r4)
712 ; CHECK-P9-NEXT: vextsh2d v2, v2
713 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
714 ; CHECK-P9-NEXT: vperm v2, v4, v4, v3
715 ; CHECK-P9-NEXT: vextsh2d v2, v2
716 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
717 ; CHECK-P9-NEXT: xvcvsxddp vs4, v2
718 ; CHECK-P9-NEXT: vperm v2, v4, v4, v5
719 ; CHECK-P9-NEXT: vextsh2d v2, v2
720 ; CHECK-P9-NEXT: xvcvsxddp vs5, v2
721 ; CHECK-P9-NEXT: vperm v2, v4, v4, v0
722 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
723 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
724 ; CHECK-P9-NEXT: vextsh2d v2, v2
725 ; CHECK-P9-NEXT: xvcvsxddp vs6, v2
726 ; CHECK-P9-NEXT: vperm v2, v4, v4, v1
727 ; CHECK-P9-NEXT: vextsh2d v2, v2
728 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
729 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
730 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
731 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
732 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
733 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
734 ; CHECK-P9-NEXT: blr
735 ;
736 ; CHECK-BE-LABEL: test16elt_signed:
737 ; CHECK-BE: # %bb.0: # %entry
738 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
739 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
740 ; CHECK-BE-NEXT: lxvx v2, 0, r5
741 ; CHECK-BE-NEXT: lxv v4, 0(r4)
742 ; CHECK-BE-NEXT: lxv v1, 16(r4)
743 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
744 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l
745 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
746 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
747 ; CHECK-BE-NEXT: vperm v0, v5, v4, v2
748 ; CHECK-BE-NEXT: lxvx v3, 0, r5
749 ; CHECK-BE-NEXT: vperm v2, v5, v1, v2
750 ; CHECK-BE-NEXT: vextsh2d v2, v2
751 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
752 ; CHECK-BE-NEXT: vextsh2d v0, v0
753 ; CHECK-BE-NEXT: xvcvsxddp vs2, v2
754 ; CHECK-BE-NEXT: vperm v2, v5, v1, v3
755 ; CHECK-BE-NEXT: vextsh2d v2, v2
756 ; CHECK-BE-NEXT: stxv vs2, 80(r3)
757 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
758 ; CHECK-BE-NEXT: lxvx v2, 0, r4
759 ; CHECK-BE-NEXT: xvcvsxddp vs0, v0
760 ; CHECK-BE-NEXT: vperm v0, v5, v4, v3
761 ; CHECK-BE-NEXT: vperm v3, v4, v4, v2
762 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
763 ; CHECK-BE-NEXT: vextsh2d v0, v0
764 ; CHECK-BE-NEXT: xvcvsxddp vs1, v0
765 ; CHECK-BE-NEXT: stxv vs1, 48(r3)
766 ; CHECK-BE-NEXT: vextsh2d v3, v3
767 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
768 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3
769 ; CHECK-BE-NEXT: lxvx v3, 0, r4
770 ; CHECK-BE-NEXT: vperm v2, v1, v1, v2
771 ; CHECK-BE-NEXT: vextsh2d v2, v2
772 ; CHECK-BE-NEXT: xvcvsxddp vs6, v2
773 ; CHECK-BE-NEXT: vperm v2, v1, v1, v3
774 ; CHECK-BE-NEXT: vperm v4, v4, v4, v3
775 ; CHECK-BE-NEXT: vextsh2d v4, v4
776 ; CHECK-BE-NEXT: vextsh2d v2, v2
777 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
778 ; CHECK-BE-NEXT: xvcvsxddp vs5, v4
779 ; CHECK-BE-NEXT: stxv vs3, 112(r3)
780 ; CHECK-BE-NEXT: stxv vs6, 64(r3)
781 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
782 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
783 ; CHECK-BE-NEXT: stxv vs7, 96(r3)
784 ; CHECK-BE-NEXT: stxv vs5, 32(r3)
785 ; CHECK-BE-NEXT: blr
786 entry:
787 %a = load <16 x i16>, <16 x i16>* %0, align 32
788 %1 = sitofp <16 x i16> %a to <16 x double>
789 store <16 x double> %1, <16 x double>* %agg.result, align 128
790 ret void
791 }