| blob | 4d85e3ea006b8d3982b619535894304003adb352 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV32I %s
4 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefix=RV64I %s
7 ; These test that we can use both the architectural names (x*) and the ABI names
8 ; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
9 ; case, the named register should be used for the source register of the `addi`.
10 ; It is very likely that `a0` will be chosen as the designation register, but
11 ; this is left to the compiler to choose.
12 ;
13 ; The inline assembly will, by default, contain the ABI names for the registers.
14 ;
15 ; Parenthesised registers in comments are the other aliases for this register.
17 ; NOTE: This test has to pass in 0 to the inline asm, because that's the only
18 ; value `x0` (`zero`) can take.
19 define i32 @explicit_register_x0() nounwind {
20 ; RV32I-LABEL: explicit_register_x0:
21 ; RV32I: # %bb.0:
22 ; RV32I-NEXT: #APP
23 ; RV32I-NEXT: addi a0, zero, 0
24 ; RV32I-NEXT: #NO_APP
25 ; RV32I-NEXT: ret
26 ;
27 ; RV64I-LABEL: explicit_register_x0:
28 ; RV64I: # %bb.0:
29 ; RV64I-NEXT: #APP
30 ; RV64I-NEXT: addi a0, zero, 0
31 ; RV64I-NEXT: #NO_APP
32 ; RV64I-NEXT: ret
33 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x0}"(i32 0)
34 ret i32 %1
35 }
37 ; NOTE: This test has to pass in 0 to the inline asm, because that's the only
38 ; value that `zero` (`x0`) can take.
39 define i32 @explicit_register_zero() nounwind {
40 ; RV32I-LABEL: explicit_register_zero:
41 ; RV32I: # %bb.0:
42 ; RV32I-NEXT: #APP
43 ; RV32I-NEXT: addi a0, zero, 0
44 ; RV32I-NEXT: #NO_APP
45 ; RV32I-NEXT: ret
46 ;
47 ; RV64I-LABEL: explicit_register_zero:
48 ; RV64I: # %bb.0:
49 ; RV64I-NEXT: #APP
50 ; RV64I-NEXT: addi a0, zero, 0
51 ; RV64I-NEXT: #NO_APP
52 ; RV64I-NEXT: ret
53 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{zero}"(i32 0)
54 ret i32 %1
55 }
57 ; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved.
58 define i32 @explicit_register_x1(i32 %a) nounwind {
59 ; RV32I-LABEL: explicit_register_x1:
60 ; RV32I: # %bb.0:
61 ; RV32I-NEXT: addi sp, sp, -16
62 ; RV32I-NEXT: sw ra, 12(sp)
63 ; RV32I-NEXT: mv ra, a0
64 ; RV32I-NEXT: #APP
65 ; RV32I-NEXT: addi a0, ra, 0
66 ; RV32I-NEXT: #NO_APP
67 ; RV32I-NEXT: lw ra, 12(sp)
68 ; RV32I-NEXT: addi sp, sp, 16
69 ; RV32I-NEXT: ret
70 ;
71 ; RV64I-LABEL: explicit_register_x1:
72 ; RV64I: # %bb.0:
73 ; RV64I-NEXT: addi sp, sp, -16
74 ; RV64I-NEXT: sd ra, 8(sp)
75 ; RV64I-NEXT: mv ra, a0
76 ; RV64I-NEXT: #APP
77 ; RV64I-NEXT: addi a0, ra, 0
78 ; RV64I-NEXT: #NO_APP
79 ; RV64I-NEXT: ld ra, 8(sp)
80 ; RV64I-NEXT: addi sp, sp, 16
81 ; RV64I-NEXT: ret
82 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a)
83 ret i32 %1
84 }
86 ; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved.
87 define i32 @explicit_register_ra(i32 %a) nounwind {
88 ; RV32I-LABEL: explicit_register_ra:
89 ; RV32I: # %bb.0:
90 ; RV32I-NEXT: addi sp, sp, -16
91 ; RV32I-NEXT: sw ra, 12(sp)
92 ; RV32I-NEXT: mv ra, a0
93 ; RV32I-NEXT: #APP
94 ; RV32I-NEXT: addi a0, ra, 0
95 ; RV32I-NEXT: #NO_APP
96 ; RV32I-NEXT: lw ra, 12(sp)
97 ; RV32I-NEXT: addi sp, sp, 16
98 ; RV32I-NEXT: ret
99 ;
100 ; RV64I-LABEL: explicit_register_ra:
101 ; RV64I: # %bb.0:
102 ; RV64I-NEXT: addi sp, sp, -16
103 ; RV64I-NEXT: sd ra, 8(sp)
104 ; RV64I-NEXT: mv ra, a0
105 ; RV64I-NEXT: #APP
106 ; RV64I-NEXT: addi a0, ra, 0
107 ; RV64I-NEXT: #NO_APP
108 ; RV64I-NEXT: ld ra, 8(sp)
109 ; RV64I-NEXT: addi sp, sp, 16
110 ; RV64I-NEXT: ret
111 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a)
112 ret i32 %1
113 }
115 define i32 @explicit_register_x2(i32 %a) nounwind {
116 ; RV32I-LABEL: explicit_register_x2:
117 ; RV32I: # %bb.0:
118 ; RV32I-NEXT: mv sp, a0
119 ; RV32I-NEXT: #APP
120 ; RV32I-NEXT: addi a0, sp, 0
121 ; RV32I-NEXT: #NO_APP
122 ; RV32I-NEXT: ret
123 ;
124 ; RV64I-LABEL: explicit_register_x2:
125 ; RV64I: # %bb.0:
126 ; RV64I-NEXT: mv sp, a0
127 ; RV64I-NEXT: #APP
128 ; RV64I-NEXT: addi a0, sp, 0
129 ; RV64I-NEXT: #NO_APP
130 ; RV64I-NEXT: ret
131 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x2}"(i32 %a)
132 ret i32 %1
133 }
135 define i32 @explicit_register_sp(i32 %a) nounwind {
136 ; RV32I-LABEL: explicit_register_sp:
137 ; RV32I: # %bb.0:
138 ; RV32I-NEXT: mv sp, a0
139 ; RV32I-NEXT: #APP
140 ; RV32I-NEXT: addi a0, sp, 0
141 ; RV32I-NEXT: #NO_APP
142 ; RV32I-NEXT: ret
143 ;
144 ; RV64I-LABEL: explicit_register_sp:
145 ; RV64I: # %bb.0:
146 ; RV64I-NEXT: mv sp, a0
147 ; RV64I-NEXT: #APP
148 ; RV64I-NEXT: addi a0, sp, 0
149 ; RV64I-NEXT: #NO_APP
150 ; RV64I-NEXT: ret
151 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{sp}"(i32 %a)
152 ret i32 %1
153 }
155 ; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved.
156 define i32 @explicit_register_x3(i32 %a) nounwind {
157 ; RV32I-LABEL: explicit_register_x3:
158 ; RV32I: # %bb.0:
159 ; RV32I-NEXT: addi sp, sp, -16
160 ; RV32I-NEXT: sw gp, 12(sp)
161 ; RV32I-NEXT: mv gp, a0
162 ; RV32I-NEXT: #APP
163 ; RV32I-NEXT: addi a0, gp, 0
164 ; RV32I-NEXT: #NO_APP
165 ; RV32I-NEXT: lw gp, 12(sp)
166 ; RV32I-NEXT: addi sp, sp, 16
167 ; RV32I-NEXT: ret
168 ;
169 ; RV64I-LABEL: explicit_register_x3:
170 ; RV64I: # %bb.0:
171 ; RV64I-NEXT: addi sp, sp, -16
172 ; RV64I-NEXT: sd gp, 8(sp)
173 ; RV64I-NEXT: mv gp, a0
174 ; RV64I-NEXT: #APP
175 ; RV64I-NEXT: addi a0, gp, 0
176 ; RV64I-NEXT: #NO_APP
177 ; RV64I-NEXT: ld gp, 8(sp)
178 ; RV64I-NEXT: addi sp, sp, 16
179 ; RV64I-NEXT: ret
180 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a)
181 ret i32 %1
182 }
184 ; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved.
185 define i32 @explicit_register_gp(i32 %a) nounwind {
186 ; RV32I-LABEL: explicit_register_gp:
187 ; RV32I: # %bb.0:
188 ; RV32I-NEXT: addi sp, sp, -16
189 ; RV32I-NEXT: sw gp, 12(sp)
190 ; RV32I-NEXT: mv gp, a0
191 ; RV32I-NEXT: #APP
192 ; RV32I-NEXT: addi a0, gp, 0
193 ; RV32I-NEXT: #NO_APP
194 ; RV32I-NEXT: lw gp, 12(sp)
195 ; RV32I-NEXT: addi sp, sp, 16
196 ; RV32I-NEXT: ret
197 ;
198 ; RV64I-LABEL: explicit_register_gp:
199 ; RV64I: # %bb.0:
200 ; RV64I-NEXT: addi sp, sp, -16
201 ; RV64I-NEXT: sd gp, 8(sp)
202 ; RV64I-NEXT: mv gp, a0
203 ; RV64I-NEXT: #APP
204 ; RV64I-NEXT: addi a0, gp, 0
205 ; RV64I-NEXT: #NO_APP
206 ; RV64I-NEXT: ld gp, 8(sp)
207 ; RV64I-NEXT: addi sp, sp, 16
208 ; RV64I-NEXT: ret
209 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a)
210 ret i32 %1
211 }
213 ; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved.
214 define i32 @explicit_register_x4(i32 %a) nounwind {
215 ; RV32I-LABEL: explicit_register_x4:
216 ; RV32I: # %bb.0:
217 ; RV32I-NEXT: addi sp, sp, -16
218 ; RV32I-NEXT: sw tp, 12(sp)
219 ; RV32I-NEXT: mv tp, a0
220 ; RV32I-NEXT: #APP
221 ; RV32I-NEXT: addi a0, tp, 0
222 ; RV32I-NEXT: #NO_APP
223 ; RV32I-NEXT: lw tp, 12(sp)
224 ; RV32I-NEXT: addi sp, sp, 16
225 ; RV32I-NEXT: ret
226 ;
227 ; RV64I-LABEL: explicit_register_x4:
228 ; RV64I: # %bb.0:
229 ; RV64I-NEXT: addi sp, sp, -16
230 ; RV64I-NEXT: sd tp, 8(sp)
231 ; RV64I-NEXT: mv tp, a0
232 ; RV64I-NEXT: #APP
233 ; RV64I-NEXT: addi a0, tp, 0
234 ; RV64I-NEXT: #NO_APP
235 ; RV64I-NEXT: ld tp, 8(sp)
236 ; RV64I-NEXT: addi sp, sp, 16
237 ; RV64I-NEXT: ret
238 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a)
239 ret i32 %1
240 }
242 ; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved.
243 define i32 @explicit_register_tp(i32 %a) nounwind {
244 ; RV32I-LABEL: explicit_register_tp:
245 ; RV32I: # %bb.0:
246 ; RV32I-NEXT: addi sp, sp, -16
247 ; RV32I-NEXT: sw tp, 12(sp)
248 ; RV32I-NEXT: mv tp, a0
249 ; RV32I-NEXT: #APP
250 ; RV32I-NEXT: addi a0, tp, 0
251 ; RV32I-NEXT: #NO_APP
252 ; RV32I-NEXT: lw tp, 12(sp)
253 ; RV32I-NEXT: addi sp, sp, 16
254 ; RV32I-NEXT: ret
255 ;
256 ; RV64I-LABEL: explicit_register_tp:
257 ; RV64I: # %bb.0:
258 ; RV64I-NEXT: addi sp, sp, -16
259 ; RV64I-NEXT: sd tp, 8(sp)
260 ; RV64I-NEXT: mv tp, a0
261 ; RV64I-NEXT: #APP
262 ; RV64I-NEXT: addi a0, tp, 0
263 ; RV64I-NEXT: #NO_APP
264 ; RV64I-NEXT: ld tp, 8(sp)
265 ; RV64I-NEXT: addi sp, sp, 16
266 ; RV64I-NEXT: ret
267 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a)
268 ret i32 %1
269 }
271 define i32 @explicit_register_x5(i32 %a) nounwind {
272 ; RV32I-LABEL: explicit_register_x5:
273 ; RV32I: # %bb.0:
274 ; RV32I-NEXT: mv t0, a0
275 ; RV32I-NEXT: #APP
276 ; RV32I-NEXT: addi a0, t0, 0
277 ; RV32I-NEXT: #NO_APP
278 ; RV32I-NEXT: ret
279 ;
280 ; RV64I-LABEL: explicit_register_x5:
281 ; RV64I: # %bb.0:
282 ; RV64I-NEXT: mv t0, a0
283 ; RV64I-NEXT: #APP
284 ; RV64I-NEXT: addi a0, t0, 0
285 ; RV64I-NEXT: #NO_APP
286 ; RV64I-NEXT: ret
287 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x5}"(i32 %a)
288 ret i32 %1
289 }
291 define i32 @explicit_register_t0(i32 %a) nounwind {
292 ; RV32I-LABEL: explicit_register_t0:
293 ; RV32I: # %bb.0:
294 ; RV32I-NEXT: mv t0, a0
295 ; RV32I-NEXT: #APP
296 ; RV32I-NEXT: addi a0, t0, 0
297 ; RV32I-NEXT: #NO_APP
298 ; RV32I-NEXT: ret
299 ;
300 ; RV64I-LABEL: explicit_register_t0:
301 ; RV64I: # %bb.0:
302 ; RV64I-NEXT: mv t0, a0
303 ; RV64I-NEXT: #APP
304 ; RV64I-NEXT: addi a0, t0, 0
305 ; RV64I-NEXT: #NO_APP
306 ; RV64I-NEXT: ret
307 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t0}"(i32 %a)
308 ret i32 %1
309 }
311 define i32 @explicit_register_x6(i32 %a) nounwind {
312 ; RV32I-LABEL: explicit_register_x6:
313 ; RV32I: # %bb.0:
314 ; RV32I-NEXT: mv t1, a0
315 ; RV32I-NEXT: #APP
316 ; RV32I-NEXT: addi a0, t1, 0
317 ; RV32I-NEXT: #NO_APP
318 ; RV32I-NEXT: ret
319 ;
320 ; RV64I-LABEL: explicit_register_x6:
321 ; RV64I: # %bb.0:
322 ; RV64I-NEXT: mv t1, a0
323 ; RV64I-NEXT: #APP
324 ; RV64I-NEXT: addi a0, t1, 0
325 ; RV64I-NEXT: #NO_APP
326 ; RV64I-NEXT: ret
327 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x6}"(i32 %a)
328 ret i32 %1
329 }
331 define i32 @explicit_register_t1(i32 %a) nounwind {
332 ; RV32I-LABEL: explicit_register_t1:
333 ; RV32I: # %bb.0:
334 ; RV32I-NEXT: mv t1, a0
335 ; RV32I-NEXT: #APP
336 ; RV32I-NEXT: addi a0, t1, 0
337 ; RV32I-NEXT: #NO_APP
338 ; RV32I-NEXT: ret
339 ;
340 ; RV64I-LABEL: explicit_register_t1:
341 ; RV64I: # %bb.0:
342 ; RV64I-NEXT: mv t1, a0
343 ; RV64I-NEXT: #APP
344 ; RV64I-NEXT: addi a0, t1, 0
345 ; RV64I-NEXT: #NO_APP
346 ; RV64I-NEXT: ret
347 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t1}"(i32 %a)
348 ret i32 %1
349 }
351 define i32 @explicit_register_x7(i32 %a) nounwind {
352 ; RV32I-LABEL: explicit_register_x7:
353 ; RV32I: # %bb.0:
354 ; RV32I-NEXT: mv t2, a0
355 ; RV32I-NEXT: #APP
356 ; RV32I-NEXT: addi a0, t2, 0
357 ; RV32I-NEXT: #NO_APP
358 ; RV32I-NEXT: ret
359 ;
360 ; RV64I-LABEL: explicit_register_x7:
361 ; RV64I: # %bb.0:
362 ; RV64I-NEXT: mv t2, a0
363 ; RV64I-NEXT: #APP
364 ; RV64I-NEXT: addi a0, t2, 0
365 ; RV64I-NEXT: #NO_APP
366 ; RV64I-NEXT: ret
367 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x7}"(i32 %a)
368 ret i32 %1
369 }
371 define i32 @explicit_register_t2(i32 %a) nounwind {
372 ; RV32I-LABEL: explicit_register_t2:
373 ; RV32I: # %bb.0:
374 ; RV32I-NEXT: mv t2, a0
375 ; RV32I-NEXT: #APP
376 ; RV32I-NEXT: addi a0, t2, 0
377 ; RV32I-NEXT: #NO_APP
378 ; RV32I-NEXT: ret
379 ;
380 ; RV64I-LABEL: explicit_register_t2:
381 ; RV64I: # %bb.0:
382 ; RV64I-NEXT: mv t2, a0
383 ; RV64I-NEXT: #APP
384 ; RV64I-NEXT: addi a0, t2, 0
385 ; RV64I-NEXT: #NO_APP
386 ; RV64I-NEXT: ret
387 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t2}"(i32 %a)
388 ret i32 %1
389 }
391 ; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved.
392 define i32 @explicit_register_x8(i32 %a) nounwind {
393 ; RV32I-LABEL: explicit_register_x8:
394 ; RV32I: # %bb.0:
395 ; RV32I-NEXT: addi sp, sp, -16
396 ; RV32I-NEXT: sw s0, 12(sp)
397 ; RV32I-NEXT: mv s0, a0
398 ; RV32I-NEXT: #APP
399 ; RV32I-NEXT: addi a0, s0, 0
400 ; RV32I-NEXT: #NO_APP
401 ; RV32I-NEXT: lw s0, 12(sp)
402 ; RV32I-NEXT: addi sp, sp, 16
403 ; RV32I-NEXT: ret
404 ;
405 ; RV64I-LABEL: explicit_register_x8:
406 ; RV64I: # %bb.0:
407 ; RV64I-NEXT: addi sp, sp, -16
408 ; RV64I-NEXT: sd s0, 8(sp)
409 ; RV64I-NEXT: mv s0, a0
410 ; RV64I-NEXT: #APP
411 ; RV64I-NEXT: addi a0, s0, 0
412 ; RV64I-NEXT: #NO_APP
413 ; RV64I-NEXT: ld s0, 8(sp)
414 ; RV64I-NEXT: addi sp, sp, 16
415 ; RV64I-NEXT: ret
416 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a)
417 ret i32 %1
418 }
420 ; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved.
421 define i32 @explicit_register_s0(i32 %a) nounwind {
422 ; RV32I-LABEL: explicit_register_s0:
423 ; RV32I: # %bb.0:
424 ; RV32I-NEXT: addi sp, sp, -16
425 ; RV32I-NEXT: sw s0, 12(sp)
426 ; RV32I-NEXT: mv s0, a0
427 ; RV32I-NEXT: #APP
428 ; RV32I-NEXT: addi a0, s0, 0
429 ; RV32I-NEXT: #NO_APP
430 ; RV32I-NEXT: lw s0, 12(sp)
431 ; RV32I-NEXT: addi sp, sp, 16
432 ; RV32I-NEXT: ret
433 ;
434 ; RV64I-LABEL: explicit_register_s0:
435 ; RV64I: # %bb.0:
436 ; RV64I-NEXT: addi sp, sp, -16
437 ; RV64I-NEXT: sd s0, 8(sp)
438 ; RV64I-NEXT: mv s0, a0
439 ; RV64I-NEXT: #APP
440 ; RV64I-NEXT: addi a0, s0, 0
441 ; RV64I-NEXT: #NO_APP
442 ; RV64I-NEXT: ld s0, 8(sp)
443 ; RV64I-NEXT: addi sp, sp, 16
444 ; RV64I-NEXT: ret
445 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a)
446 ret i32 %1
447 }
449 ; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved.
450 define i32 @explicit_register_fp(i32 %a) nounwind {
451 ; RV32I-LABEL: explicit_register_fp:
452 ; RV32I: # %bb.0:
453 ; RV32I-NEXT: addi sp, sp, -16
454 ; RV32I-NEXT: sw s0, 12(sp)
455 ; RV32I-NEXT: mv s0, a0
456 ; RV32I-NEXT: #APP
457 ; RV32I-NEXT: addi a0, s0, 0
458 ; RV32I-NEXT: #NO_APP
459 ; RV32I-NEXT: lw s0, 12(sp)
460 ; RV32I-NEXT: addi sp, sp, 16
461 ; RV32I-NEXT: ret
462 ;
463 ; RV64I-LABEL: explicit_register_fp:
464 ; RV64I: # %bb.0:
465 ; RV64I-NEXT: addi sp, sp, -16
466 ; RV64I-NEXT: sd s0, 8(sp)
467 ; RV64I-NEXT: mv s0, a0
468 ; RV64I-NEXT: #APP
469 ; RV64I-NEXT: addi a0, s0, 0
470 ; RV64I-NEXT: #NO_APP
471 ; RV64I-NEXT: ld s0, 8(sp)
472 ; RV64I-NEXT: addi sp, sp, 16
473 ; RV64I-NEXT: ret
474 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a)
475 ret i32 %1
476 }
478 ; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved.
479 define i32 @explicit_register_x9(i32 %a) nounwind {
480 ; RV32I-LABEL: explicit_register_x9:
481 ; RV32I: # %bb.0:
482 ; RV32I-NEXT: addi sp, sp, -16
483 ; RV32I-NEXT: sw s1, 12(sp)
484 ; RV32I-NEXT: mv s1, a0
485 ; RV32I-NEXT: #APP
486 ; RV32I-NEXT: addi a0, s1, 0
487 ; RV32I-NEXT: #NO_APP
488 ; RV32I-NEXT: lw s1, 12(sp)
489 ; RV32I-NEXT: addi sp, sp, 16
490 ; RV32I-NEXT: ret
491 ;
492 ; RV64I-LABEL: explicit_register_x9:
493 ; RV64I: # %bb.0:
494 ; RV64I-NEXT: addi sp, sp, -16
495 ; RV64I-NEXT: sd s1, 8(sp)
496 ; RV64I-NEXT: mv s1, a0
497 ; RV64I-NEXT: #APP
498 ; RV64I-NEXT: addi a0, s1, 0
499 ; RV64I-NEXT: #NO_APP
500 ; RV64I-NEXT: ld s1, 8(sp)
501 ; RV64I-NEXT: addi sp, sp, 16
502 ; RV64I-NEXT: ret
503 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a)
504 ret i32 %1
505 }
507 ; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved.
508 define i32 @explicit_register_s1(i32 %a) nounwind {
509 ; RV32I-LABEL: explicit_register_s1:
510 ; RV32I: # %bb.0:
511 ; RV32I-NEXT: addi sp, sp, -16
512 ; RV32I-NEXT: sw s1, 12(sp)
513 ; RV32I-NEXT: mv s1, a0
514 ; RV32I-NEXT: #APP
515 ; RV32I-NEXT: addi a0, s1, 0
516 ; RV32I-NEXT: #NO_APP
517 ; RV32I-NEXT: lw s1, 12(sp)
518 ; RV32I-NEXT: addi sp, sp, 16
519 ; RV32I-NEXT: ret
520 ;
521 ; RV64I-LABEL: explicit_register_s1:
522 ; RV64I: # %bb.0:
523 ; RV64I-NEXT: addi sp, sp, -16
524 ; RV64I-NEXT: sd s1, 8(sp)
525 ; RV64I-NEXT: mv s1, a0
526 ; RV64I-NEXT: #APP
527 ; RV64I-NEXT: addi a0, s1, 0
528 ; RV64I-NEXT: #NO_APP
529 ; RV64I-NEXT: ld s1, 8(sp)
530 ; RV64I-NEXT: addi sp, sp, 16
531 ; RV64I-NEXT: ret
532 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a)
533 ret i32 %1
534 }
536 define i32 @explicit_register_x10(i32 %a) nounwind {
537 ; RV32I-LABEL: explicit_register_x10:
538 ; RV32I: # %bb.0:
539 ; RV32I-NEXT: #APP
540 ; RV32I-NEXT: addi a0, a0, 0
541 ; RV32I-NEXT: #NO_APP
542 ; RV32I-NEXT: ret
543 ;
544 ; RV64I-LABEL: explicit_register_x10:
545 ; RV64I: # %bb.0:
546 ; RV64I-NEXT: #APP
547 ; RV64I-NEXT: addi a0, a0, 0
548 ; RV64I-NEXT: #NO_APP
549 ; RV64I-NEXT: ret
550 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x10}"(i32 %a)
551 ret i32 %1
552 }
554 define i32 @explicit_register_a0(i32 %a) nounwind {
555 ; RV32I-LABEL: explicit_register_a0:
556 ; RV32I: # %bb.0:
557 ; RV32I-NEXT: #APP
558 ; RV32I-NEXT: addi a0, a0, 0
559 ; RV32I-NEXT: #NO_APP
560 ; RV32I-NEXT: ret
561 ;
562 ; RV64I-LABEL: explicit_register_a0:
563 ; RV64I: # %bb.0:
564 ; RV64I-NEXT: #APP
565 ; RV64I-NEXT: addi a0, a0, 0
566 ; RV64I-NEXT: #NO_APP
567 ; RV64I-NEXT: ret
568 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a0}"(i32 %a)
569 ret i32 %1
570 }
572 define i32 @explicit_register_x11(i32 %a) nounwind {
573 ; RV32I-LABEL: explicit_register_x11:
574 ; RV32I: # %bb.0:
575 ; RV32I-NEXT: mv a1, a0
576 ; RV32I-NEXT: #APP
577 ; RV32I-NEXT: addi a0, a1, 0
578 ; RV32I-NEXT: #NO_APP
579 ; RV32I-NEXT: ret
580 ;
581 ; RV64I-LABEL: explicit_register_x11:
582 ; RV64I: # %bb.0:
583 ; RV64I-NEXT: mv a1, a0
584 ; RV64I-NEXT: #APP
585 ; RV64I-NEXT: addi a0, a1, 0
586 ; RV64I-NEXT: #NO_APP
587 ; RV64I-NEXT: ret
588 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x11}"(i32 %a)
589 ret i32 %1
590 }
592 define i32 @explicit_register_a1(i32 %a) nounwind {
593 ; RV32I-LABEL: explicit_register_a1:
594 ; RV32I: # %bb.0:
595 ; RV32I-NEXT: mv a1, a0
596 ; RV32I-NEXT: #APP
597 ; RV32I-NEXT: addi a0, a1, 0
598 ; RV32I-NEXT: #NO_APP
599 ; RV32I-NEXT: ret
600 ;
601 ; RV64I-LABEL: explicit_register_a1:
602 ; RV64I: # %bb.0:
603 ; RV64I-NEXT: mv a1, a0
604 ; RV64I-NEXT: #APP
605 ; RV64I-NEXT: addi a0, a1, 0
606 ; RV64I-NEXT: #NO_APP
607 ; RV64I-NEXT: ret
608 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a1}"(i32 %a)
609 ret i32 %1
610 }
612 define i32 @explicit_register_x12(i32 %a) nounwind {
613 ; RV32I-LABEL: explicit_register_x12:
614 ; RV32I: # %bb.0:
615 ; RV32I-NEXT: mv a2, a0
616 ; RV32I-NEXT: #APP
617 ; RV32I-NEXT: addi a0, a2, 0
618 ; RV32I-NEXT: #NO_APP
619 ; RV32I-NEXT: ret
620 ;
621 ; RV64I-LABEL: explicit_register_x12:
622 ; RV64I: # %bb.0:
623 ; RV64I-NEXT: mv a2, a0
624 ; RV64I-NEXT: #APP
625 ; RV64I-NEXT: addi a0, a2, 0
626 ; RV64I-NEXT: #NO_APP
627 ; RV64I-NEXT: ret
628 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x12}"(i32 %a)
629 ret i32 %1
630 }
632 define i32 @explicit_register_a2(i32 %a) nounwind {
633 ; RV32I-LABEL: explicit_register_a2:
634 ; RV32I: # %bb.0:
635 ; RV32I-NEXT: mv a2, a0
636 ; RV32I-NEXT: #APP
637 ; RV32I-NEXT: addi a0, a2, 0
638 ; RV32I-NEXT: #NO_APP
639 ; RV32I-NEXT: ret
640 ;
641 ; RV64I-LABEL: explicit_register_a2:
642 ; RV64I: # %bb.0:
643 ; RV64I-NEXT: mv a2, a0
644 ; RV64I-NEXT: #APP
645 ; RV64I-NEXT: addi a0, a2, 0
646 ; RV64I-NEXT: #NO_APP
647 ; RV64I-NEXT: ret
648 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a2}"(i32 %a)
649 ret i32 %1
650 }
652 define i32 @explicit_register_x13(i32 %a) nounwind {
653 ; RV32I-LABEL: explicit_register_x13:
654 ; RV32I: # %bb.0:
655 ; RV32I-NEXT: mv a3, a0
656 ; RV32I-NEXT: #APP
657 ; RV32I-NEXT: addi a0, a3, 0
658 ; RV32I-NEXT: #NO_APP
659 ; RV32I-NEXT: ret
660 ;
661 ; RV64I-LABEL: explicit_register_x13:
662 ; RV64I: # %bb.0:
663 ; RV64I-NEXT: mv a3, a0
664 ; RV64I-NEXT: #APP
665 ; RV64I-NEXT: addi a0, a3, 0
666 ; RV64I-NEXT: #NO_APP
667 ; RV64I-NEXT: ret
668 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x13}"(i32 %a)
669 ret i32 %1
670 }
672 define i32 @explicit_register_a3(i32 %a) nounwind {
673 ; RV32I-LABEL: explicit_register_a3:
674 ; RV32I: # %bb.0:
675 ; RV32I-NEXT: mv a3, a0
676 ; RV32I-NEXT: #APP
677 ; RV32I-NEXT: addi a0, a3, 0
678 ; RV32I-NEXT: #NO_APP
679 ; RV32I-NEXT: ret
680 ;
681 ; RV64I-LABEL: explicit_register_a3:
682 ; RV64I: # %bb.0:
683 ; RV64I-NEXT: mv a3, a0
684 ; RV64I-NEXT: #APP
685 ; RV64I-NEXT: addi a0, a3, 0
686 ; RV64I-NEXT: #NO_APP
687 ; RV64I-NEXT: ret
688 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a3}"(i32 %a)
689 ret i32 %1
690 }
692 define i32 @explicit_register_x14(i32 %a) nounwind {
693 ; RV32I-LABEL: explicit_register_x14:
694 ; RV32I: # %bb.0:
695 ; RV32I-NEXT: mv a4, a0
696 ; RV32I-NEXT: #APP
697 ; RV32I-NEXT: addi a0, a4, 0
698 ; RV32I-NEXT: #NO_APP
699 ; RV32I-NEXT: ret
700 ;
701 ; RV64I-LABEL: explicit_register_x14:
702 ; RV64I: # %bb.0:
703 ; RV64I-NEXT: mv a4, a0
704 ; RV64I-NEXT: #APP
705 ; RV64I-NEXT: addi a0, a4, 0
706 ; RV64I-NEXT: #NO_APP
707 ; RV64I-NEXT: ret
708 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x14}"(i32 %a)
709 ret i32 %1
710 }
712 define i32 @explicit_register_a4(i32 %a) nounwind {
713 ; RV32I-LABEL: explicit_register_a4:
714 ; RV32I: # %bb.0:
715 ; RV32I-NEXT: mv a4, a0
716 ; RV32I-NEXT: #APP
717 ; RV32I-NEXT: addi a0, a4, 0
718 ; RV32I-NEXT: #NO_APP
719 ; RV32I-NEXT: ret
720 ;
721 ; RV64I-LABEL: explicit_register_a4:
722 ; RV64I: # %bb.0:
723 ; RV64I-NEXT: mv a4, a0
724 ; RV64I-NEXT: #APP
725 ; RV64I-NEXT: addi a0, a4, 0
726 ; RV64I-NEXT: #NO_APP
727 ; RV64I-NEXT: ret
728 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a4}"(i32 %a)
729 ret i32 %1
730 }
732 define i32 @explicit_register_x15(i32 %a) nounwind {
733 ; RV32I-LABEL: explicit_register_x15:
734 ; RV32I: # %bb.0:
735 ; RV32I-NEXT: mv a5, a0
736 ; RV32I-NEXT: #APP
737 ; RV32I-NEXT: addi a0, a5, 0
738 ; RV32I-NEXT: #NO_APP
739 ; RV32I-NEXT: ret
740 ;
741 ; RV64I-LABEL: explicit_register_x15:
742 ; RV64I: # %bb.0:
743 ; RV64I-NEXT: mv a5, a0
744 ; RV64I-NEXT: #APP
745 ; RV64I-NEXT: addi a0, a5, 0
746 ; RV64I-NEXT: #NO_APP
747 ; RV64I-NEXT: ret
748 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x15}"(i32 %a)
749 ret i32 %1
750 }
752 define i32 @explicit_register_a5(i32 %a) nounwind {
753 ; RV32I-LABEL: explicit_register_a5:
754 ; RV32I: # %bb.0:
755 ; RV32I-NEXT: mv a5, a0
756 ; RV32I-NEXT: #APP
757 ; RV32I-NEXT: addi a0, a5, 0
758 ; RV32I-NEXT: #NO_APP
759 ; RV32I-NEXT: ret
760 ;
761 ; RV64I-LABEL: explicit_register_a5:
762 ; RV64I: # %bb.0:
763 ; RV64I-NEXT: mv a5, a0
764 ; RV64I-NEXT: #APP
765 ; RV64I-NEXT: addi a0, a5, 0
766 ; RV64I-NEXT: #NO_APP
767 ; RV64I-NEXT: ret
768 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a5}"(i32 %a)
769 ret i32 %1
770 }
772 define i32 @explicit_register_x16(i32 %a) nounwind {
773 ; RV32I-LABEL: explicit_register_x16:
774 ; RV32I: # %bb.0:
775 ; RV32I-NEXT: mv a6, a0
776 ; RV32I-NEXT: #APP
777 ; RV32I-NEXT: addi a0, a6, 0
778 ; RV32I-NEXT: #NO_APP
779 ; RV32I-NEXT: ret
780 ;
781 ; RV64I-LABEL: explicit_register_x16:
782 ; RV64I: # %bb.0:
783 ; RV64I-NEXT: mv a6, a0
784 ; RV64I-NEXT: #APP
785 ; RV64I-NEXT: addi a0, a6, 0
786 ; RV64I-NEXT: #NO_APP
787 ; RV64I-NEXT: ret
788 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x16}"(i32 %a)
789 ret i32 %1
790 }
792 define i32 @explicit_register_a6(i32 %a) nounwind {
793 ; RV32I-LABEL: explicit_register_a6:
794 ; RV32I: # %bb.0:
795 ; RV32I-NEXT: mv a6, a0
796 ; RV32I-NEXT: #APP
797 ; RV32I-NEXT: addi a0, a6, 0
798 ; RV32I-NEXT: #NO_APP
799 ; RV32I-NEXT: ret
800 ;
801 ; RV64I-LABEL: explicit_register_a6:
802 ; RV64I: # %bb.0:
803 ; RV64I-NEXT: mv a6, a0
804 ; RV64I-NEXT: #APP
805 ; RV64I-NEXT: addi a0, a6, 0
806 ; RV64I-NEXT: #NO_APP
807 ; RV64I-NEXT: ret
808 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a6}"(i32 %a)
809 ret i32 %1
810 }
812 define i32 @explicit_register_x17(i32 %a) nounwind {
813 ; RV32I-LABEL: explicit_register_x17:
814 ; RV32I: # %bb.0:
815 ; RV32I-NEXT: mv a7, a0
816 ; RV32I-NEXT: #APP
817 ; RV32I-NEXT: addi a0, a7, 0
818 ; RV32I-NEXT: #NO_APP
819 ; RV32I-NEXT: ret
820 ;
821 ; RV64I-LABEL: explicit_register_x17:
822 ; RV64I: # %bb.0:
823 ; RV64I-NEXT: mv a7, a0
824 ; RV64I-NEXT: #APP
825 ; RV64I-NEXT: addi a0, a7, 0
826 ; RV64I-NEXT: #NO_APP
827 ; RV64I-NEXT: ret
828 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x17}"(i32 %a)
829 ret i32 %1
830 }
832 define i32 @explicit_register_a7(i32 %a) nounwind {
833 ; RV32I-LABEL: explicit_register_a7:
834 ; RV32I: # %bb.0:
835 ; RV32I-NEXT: mv a7, a0
836 ; RV32I-NEXT: #APP
837 ; RV32I-NEXT: addi a0, a7, 0
838 ; RV32I-NEXT: #NO_APP
839 ; RV32I-NEXT: ret
840 ;
841 ; RV64I-LABEL: explicit_register_a7:
842 ; RV64I: # %bb.0:
843 ; RV64I-NEXT: mv a7, a0
844 ; RV64I-NEXT: #APP
845 ; RV64I-NEXT: addi a0, a7, 0
846 ; RV64I-NEXT: #NO_APP
847 ; RV64I-NEXT: ret
848 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a7}"(i32 %a)
849 ret i32 %1
850 }
852 ; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved.
853 define i32 @explicit_register_x18(i32 %a) nounwind {
854 ; RV32I-LABEL: explicit_register_x18:
855 ; RV32I: # %bb.0:
856 ; RV32I-NEXT: addi sp, sp, -16
857 ; RV32I-NEXT: sw s2, 12(sp)
858 ; RV32I-NEXT: mv s2, a0
859 ; RV32I-NEXT: #APP
860 ; RV32I-NEXT: addi a0, s2, 0
861 ; RV32I-NEXT: #NO_APP
862 ; RV32I-NEXT: lw s2, 12(sp)
863 ; RV32I-NEXT: addi sp, sp, 16
864 ; RV32I-NEXT: ret
865 ;
866 ; RV64I-LABEL: explicit_register_x18:
867 ; RV64I: # %bb.0:
868 ; RV64I-NEXT: addi sp, sp, -16
869 ; RV64I-NEXT: sd s2, 8(sp)
870 ; RV64I-NEXT: mv s2, a0
871 ; RV64I-NEXT: #APP
872 ; RV64I-NEXT: addi a0, s2, 0
873 ; RV64I-NEXT: #NO_APP
874 ; RV64I-NEXT: ld s2, 8(sp)
875 ; RV64I-NEXT: addi sp, sp, 16
876 ; RV64I-NEXT: ret
877 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a)
878 ret i32 %1
879 }
881 ; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved.
882 define i32 @explicit_register_s2(i32 %a) nounwind {
883 ; RV32I-LABEL: explicit_register_s2:
884 ; RV32I: # %bb.0:
885 ; RV32I-NEXT: addi sp, sp, -16
886 ; RV32I-NEXT: sw s2, 12(sp)
887 ; RV32I-NEXT: mv s2, a0
888 ; RV32I-NEXT: #APP
889 ; RV32I-NEXT: addi a0, s2, 0
890 ; RV32I-NEXT: #NO_APP
891 ; RV32I-NEXT: lw s2, 12(sp)
892 ; RV32I-NEXT: addi sp, sp, 16
893 ; RV32I-NEXT: ret
894 ;
895 ; RV64I-LABEL: explicit_register_s2:
896 ; RV64I: # %bb.0:
897 ; RV64I-NEXT: addi sp, sp, -16
898 ; RV64I-NEXT: sd s2, 8(sp)
899 ; RV64I-NEXT: mv s2, a0
900 ; RV64I-NEXT: #APP
901 ; RV64I-NEXT: addi a0, s2, 0
902 ; RV64I-NEXT: #NO_APP
903 ; RV64I-NEXT: ld s2, 8(sp)
904 ; RV64I-NEXT: addi sp, sp, 16
905 ; RV64I-NEXT: ret
906 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a)
907 ret i32 %1
908 }
910 ; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved.
911 define i32 @explicit_register_x19(i32 %a) nounwind {
912 ; RV32I-LABEL: explicit_register_x19:
913 ; RV32I: # %bb.0:
914 ; RV32I-NEXT: addi sp, sp, -16
915 ; RV32I-NEXT: sw s3, 12(sp)
916 ; RV32I-NEXT: mv s3, a0
917 ; RV32I-NEXT: #APP
918 ; RV32I-NEXT: addi a0, s3, 0
919 ; RV32I-NEXT: #NO_APP
920 ; RV32I-NEXT: lw s3, 12(sp)
921 ; RV32I-NEXT: addi sp, sp, 16
922 ; RV32I-NEXT: ret
923 ;
924 ; RV64I-LABEL: explicit_register_x19:
925 ; RV64I: # %bb.0:
926 ; RV64I-NEXT: addi sp, sp, -16
927 ; RV64I-NEXT: sd s3, 8(sp)
928 ; RV64I-NEXT: mv s3, a0
929 ; RV64I-NEXT: #APP
930 ; RV64I-NEXT: addi a0, s3, 0
931 ; RV64I-NEXT: #NO_APP
932 ; RV64I-NEXT: ld s3, 8(sp)
933 ; RV64I-NEXT: addi sp, sp, 16
934 ; RV64I-NEXT: ret
935 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a)
936 ret i32 %1
937 }
939 ; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved.
940 define i32 @explicit_register_s3(i32 %a) nounwind {
941 ; RV32I-LABEL: explicit_register_s3:
942 ; RV32I: # %bb.0:
943 ; RV32I-NEXT: addi sp, sp, -16
944 ; RV32I-NEXT: sw s3, 12(sp)
945 ; RV32I-NEXT: mv s3, a0
946 ; RV32I-NEXT: #APP
947 ; RV32I-NEXT: addi a0, s3, 0
948 ; RV32I-NEXT: #NO_APP
949 ; RV32I-NEXT: lw s3, 12(sp)
950 ; RV32I-NEXT: addi sp, sp, 16
951 ; RV32I-NEXT: ret
952 ;
953 ; RV64I-LABEL: explicit_register_s3:
954 ; RV64I: # %bb.0:
955 ; RV64I-NEXT: addi sp, sp, -16
956 ; RV64I-NEXT: sd s3, 8(sp)
957 ; RV64I-NEXT: mv s3, a0
958 ; RV64I-NEXT: #APP
959 ; RV64I-NEXT: addi a0, s3, 0
960 ; RV64I-NEXT: #NO_APP
961 ; RV64I-NEXT: ld s3, 8(sp)
962 ; RV64I-NEXT: addi sp, sp, 16
963 ; RV64I-NEXT: ret
964 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a)
965 ret i32 %1
966 }
968 ; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved.
969 define i32 @explicit_register_x20(i32 %a) nounwind {
970 ; RV32I-LABEL: explicit_register_x20:
971 ; RV32I: # %bb.0:
972 ; RV32I-NEXT: addi sp, sp, -16
973 ; RV32I-NEXT: sw s4, 12(sp)
974 ; RV32I-NEXT: mv s4, a0
975 ; RV32I-NEXT: #APP
976 ; RV32I-NEXT: addi a0, s4, 0
977 ; RV32I-NEXT: #NO_APP
978 ; RV32I-NEXT: lw s4, 12(sp)
979 ; RV32I-NEXT: addi sp, sp, 16
980 ; RV32I-NEXT: ret
981 ;
982 ; RV64I-LABEL: explicit_register_x20:
983 ; RV64I: # %bb.0:
984 ; RV64I-NEXT: addi sp, sp, -16
985 ; RV64I-NEXT: sd s4, 8(sp)
986 ; RV64I-NEXT: mv s4, a0
987 ; RV64I-NEXT: #APP
988 ; RV64I-NEXT: addi a0, s4, 0
989 ; RV64I-NEXT: #NO_APP
990 ; RV64I-NEXT: ld s4, 8(sp)
991 ; RV64I-NEXT: addi sp, sp, 16
992 ; RV64I-NEXT: ret
993 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a)
994 ret i32 %1
995 }
997 ; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved.
998 define i32 @explicit_register_s4(i32 %a) nounwind {
999 ; RV32I-LABEL: explicit_register_s4:
1000 ; RV32I: # %bb.0:
1001 ; RV32I-NEXT: addi sp, sp, -16
1002 ; RV32I-NEXT: sw s4, 12(sp)
1003 ; RV32I-NEXT: mv s4, a0
1004 ; RV32I-NEXT: #APP
1005 ; RV32I-NEXT: addi a0, s4, 0
1006 ; RV32I-NEXT: #NO_APP
1007 ; RV32I-NEXT: lw s4, 12(sp)
1008 ; RV32I-NEXT: addi sp, sp, 16
1009 ; RV32I-NEXT: ret
1010 ;
1011 ; RV64I-LABEL: explicit_register_s4:
1012 ; RV64I: # %bb.0:
1013 ; RV64I-NEXT: addi sp, sp, -16
1014 ; RV64I-NEXT: sd s4, 8(sp)
1015 ; RV64I-NEXT: mv s4, a0
1016 ; RV64I-NEXT: #APP
1017 ; RV64I-NEXT: addi a0, s4, 0
1018 ; RV64I-NEXT: #NO_APP
1019 ; RV64I-NEXT: ld s4, 8(sp)
1020 ; RV64I-NEXT: addi sp, sp, 16
1021 ; RV64I-NEXT: ret
1022 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a)
1023 ret i32 %1
1024 }
1026 ; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved.
1027 define i32 @explicit_register_x21(i32 %a) nounwind {
1028 ; RV32I-LABEL: explicit_register_x21:
1029 ; RV32I: # %bb.0:
1030 ; RV32I-NEXT: addi sp, sp, -16
1031 ; RV32I-NEXT: sw s5, 12(sp)
1032 ; RV32I-NEXT: mv s5, a0
1033 ; RV32I-NEXT: #APP
1034 ; RV32I-NEXT: addi a0, s5, 0
1035 ; RV32I-NEXT: #NO_APP
1036 ; RV32I-NEXT: lw s5, 12(sp)
1037 ; RV32I-NEXT: addi sp, sp, 16
1038 ; RV32I-NEXT: ret
1039 ;
1040 ; RV64I-LABEL: explicit_register_x21:
1041 ; RV64I: # %bb.0:
1042 ; RV64I-NEXT: addi sp, sp, -16
1043 ; RV64I-NEXT: sd s5, 8(sp)
1044 ; RV64I-NEXT: mv s5, a0
1045 ; RV64I-NEXT: #APP
1046 ; RV64I-NEXT: addi a0, s5, 0
1047 ; RV64I-NEXT: #NO_APP
1048 ; RV64I-NEXT: ld s5, 8(sp)
1049 ; RV64I-NEXT: addi sp, sp, 16
1050 ; RV64I-NEXT: ret
1051 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a)
1052 ret i32 %1
1053 }
1055 ; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved.
1056 define i32 @explicit_register_s5(i32 %a) nounwind {
1057 ; RV32I-LABEL: explicit_register_s5:
1058 ; RV32I: # %bb.0:
1059 ; RV32I-NEXT: addi sp, sp, -16
1060 ; RV32I-NEXT: sw s5, 12(sp)
1061 ; RV32I-NEXT: mv s5, a0
1062 ; RV32I-NEXT: #APP
1063 ; RV32I-NEXT: addi a0, s5, 0
1064 ; RV32I-NEXT: #NO_APP
1065 ; RV32I-NEXT: lw s5, 12(sp)
1066 ; RV32I-NEXT: addi sp, sp, 16
1067 ; RV32I-NEXT: ret
1068 ;
1069 ; RV64I-LABEL: explicit_register_s5:
1070 ; RV64I: # %bb.0:
1071 ; RV64I-NEXT: addi sp, sp, -16
1072 ; RV64I-NEXT: sd s5, 8(sp)
1073 ; RV64I-NEXT: mv s5, a0
1074 ; RV64I-NEXT: #APP
1075 ; RV64I-NEXT: addi a0, s5, 0
1076 ; RV64I-NEXT: #NO_APP
1077 ; RV64I-NEXT: ld s5, 8(sp)
1078 ; RV64I-NEXT: addi sp, sp, 16
1079 ; RV64I-NEXT: ret
1080 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a)
1081 ret i32 %1
1082 }
1084 ; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved.
1085 define i32 @explicit_register_x22(i32 %a) nounwind {
1086 ; RV32I-LABEL: explicit_register_x22:
1087 ; RV32I: # %bb.0:
1088 ; RV32I-NEXT: addi sp, sp, -16
1089 ; RV32I-NEXT: sw s6, 12(sp)
1090 ; RV32I-NEXT: mv s6, a0
1091 ; RV32I-NEXT: #APP
1092 ; RV32I-NEXT: addi a0, s6, 0
1093 ; RV32I-NEXT: #NO_APP
1094 ; RV32I-NEXT: lw s6, 12(sp)
1095 ; RV32I-NEXT: addi sp, sp, 16
1096 ; RV32I-NEXT: ret
1097 ;
1098 ; RV64I-LABEL: explicit_register_x22:
1099 ; RV64I: # %bb.0:
1100 ; RV64I-NEXT: addi sp, sp, -16
1101 ; RV64I-NEXT: sd s6, 8(sp)
1102 ; RV64I-NEXT: mv s6, a0
1103 ; RV64I-NEXT: #APP
1104 ; RV64I-NEXT: addi a0, s6, 0
1105 ; RV64I-NEXT: #NO_APP
1106 ; RV64I-NEXT: ld s6, 8(sp)
1107 ; RV64I-NEXT: addi sp, sp, 16
1108 ; RV64I-NEXT: ret
1109 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a)
1110 ret i32 %1
1111 }
1113 ; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved.
1114 define i32 @explicit_register_s6(i32 %a) nounwind {
1115 ; RV32I-LABEL: explicit_register_s6:
1116 ; RV32I: # %bb.0:
1117 ; RV32I-NEXT: addi sp, sp, -16
1118 ; RV32I-NEXT: sw s6, 12(sp)
1119 ; RV32I-NEXT: mv s6, a0
1120 ; RV32I-NEXT: #APP
1121 ; RV32I-NEXT: addi a0, s6, 0
1122 ; RV32I-NEXT: #NO_APP
1123 ; RV32I-NEXT: lw s6, 12(sp)
1124 ; RV32I-NEXT: addi sp, sp, 16
1125 ; RV32I-NEXT: ret
1126 ;
1127 ; RV64I-LABEL: explicit_register_s6:
1128 ; RV64I: # %bb.0:
1129 ; RV64I-NEXT: addi sp, sp, -16
1130 ; RV64I-NEXT: sd s6, 8(sp)
1131 ; RV64I-NEXT: mv s6, a0
1132 ; RV64I-NEXT: #APP
1133 ; RV64I-NEXT: addi a0, s6, 0
1134 ; RV64I-NEXT: #NO_APP
1135 ; RV64I-NEXT: ld s6, 8(sp)
1136 ; RV64I-NEXT: addi sp, sp, 16
1137 ; RV64I-NEXT: ret
1138 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a)
1139 ret i32 %1
1140 }
1142 ; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved.
1143 define i32 @explicit_register_x23(i32 %a) nounwind {
1144 ; RV32I-LABEL: explicit_register_x23:
1145 ; RV32I: # %bb.0:
1146 ; RV32I-NEXT: addi sp, sp, -16
1147 ; RV32I-NEXT: sw s7, 12(sp)
1148 ; RV32I-NEXT: mv s7, a0
1149 ; RV32I-NEXT: #APP
1150 ; RV32I-NEXT: addi a0, s7, 0
1151 ; RV32I-NEXT: #NO_APP
1152 ; RV32I-NEXT: lw s7, 12(sp)
1153 ; RV32I-NEXT: addi sp, sp, 16
1154 ; RV32I-NEXT: ret
1155 ;
1156 ; RV64I-LABEL: explicit_register_x23:
1157 ; RV64I: # %bb.0:
1158 ; RV64I-NEXT: addi sp, sp, -16
1159 ; RV64I-NEXT: sd s7, 8(sp)
1160 ; RV64I-NEXT: mv s7, a0
1161 ; RV64I-NEXT: #APP
1162 ; RV64I-NEXT: addi a0, s7, 0
1163 ; RV64I-NEXT: #NO_APP
1164 ; RV64I-NEXT: ld s7, 8(sp)
1165 ; RV64I-NEXT: addi sp, sp, 16
1166 ; RV64I-NEXT: ret
1167 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a)
1168 ret i32 %1
1169 }
1171 ; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved.
1172 define i32 @explicit_register_s7(i32 %a) nounwind {
1173 ; RV32I-LABEL: explicit_register_s7:
1174 ; RV32I: # %bb.0:
1175 ; RV32I-NEXT: addi sp, sp, -16
1176 ; RV32I-NEXT: sw s7, 12(sp)
1177 ; RV32I-NEXT: mv s7, a0
1178 ; RV32I-NEXT: #APP
1179 ; RV32I-NEXT: addi a0, s7, 0
1180 ; RV32I-NEXT: #NO_APP
1181 ; RV32I-NEXT: lw s7, 12(sp)
1182 ; RV32I-NEXT: addi sp, sp, 16
1183 ; RV32I-NEXT: ret
1184 ;
1185 ; RV64I-LABEL: explicit_register_s7:
1186 ; RV64I: # %bb.0:
1187 ; RV64I-NEXT: addi sp, sp, -16
1188 ; RV64I-NEXT: sd s7, 8(sp)
1189 ; RV64I-NEXT: mv s7, a0
1190 ; RV64I-NEXT: #APP
1191 ; RV64I-NEXT: addi a0, s7, 0
1192 ; RV64I-NEXT: #NO_APP
1193 ; RV64I-NEXT: ld s7, 8(sp)
1194 ; RV64I-NEXT: addi sp, sp, 16
1195 ; RV64I-NEXT: ret
1196 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a)
1197 ret i32 %1
1198 }
1200 ; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved.
1201 define i32 @explicit_register_x24(i32 %a) nounwind {
1202 ; RV32I-LABEL: explicit_register_x24:
1203 ; RV32I: # %bb.0:
1204 ; RV32I-NEXT: addi sp, sp, -16
1205 ; RV32I-NEXT: sw s8, 12(sp)
1206 ; RV32I-NEXT: mv s8, a0
1207 ; RV32I-NEXT: #APP
1208 ; RV32I-NEXT: addi a0, s8, 0
1209 ; RV32I-NEXT: #NO_APP
1210 ; RV32I-NEXT: lw s8, 12(sp)
1211 ; RV32I-NEXT: addi sp, sp, 16
1212 ; RV32I-NEXT: ret
1213 ;
1214 ; RV64I-LABEL: explicit_register_x24:
1215 ; RV64I: # %bb.0:
1216 ; RV64I-NEXT: addi sp, sp, -16
1217 ; RV64I-NEXT: sd s8, 8(sp)
1218 ; RV64I-NEXT: mv s8, a0
1219 ; RV64I-NEXT: #APP
1220 ; RV64I-NEXT: addi a0, s8, 0
1221 ; RV64I-NEXT: #NO_APP
1222 ; RV64I-NEXT: ld s8, 8(sp)
1223 ; RV64I-NEXT: addi sp, sp, 16
1224 ; RV64I-NEXT: ret
1225 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a)
1226 ret i32 %1
1227 }
1229 ; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved.
1230 define i32 @explicit_register_s8(i32 %a) nounwind {
1231 ; RV32I-LABEL: explicit_register_s8:
1232 ; RV32I: # %bb.0:
1233 ; RV32I-NEXT: addi sp, sp, -16
1234 ; RV32I-NEXT: sw s8, 12(sp)
1235 ; RV32I-NEXT: mv s8, a0
1236 ; RV32I-NEXT: #APP
1237 ; RV32I-NEXT: addi a0, s8, 0
1238 ; RV32I-NEXT: #NO_APP
1239 ; RV32I-NEXT: lw s8, 12(sp)
1240 ; RV32I-NEXT: addi sp, sp, 16
1241 ; RV32I-NEXT: ret
1242 ;
1243 ; RV64I-LABEL: explicit_register_s8:
1244 ; RV64I: # %bb.0:
1245 ; RV64I-NEXT: addi sp, sp, -16
1246 ; RV64I-NEXT: sd s8, 8(sp)
1247 ; RV64I-NEXT: mv s8, a0
1248 ; RV64I-NEXT: #APP
1249 ; RV64I-NEXT: addi a0, s8, 0
1250 ; RV64I-NEXT: #NO_APP
1251 ; RV64I-NEXT: ld s8, 8(sp)
1252 ; RV64I-NEXT: addi sp, sp, 16
1253 ; RV64I-NEXT: ret
1254 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a)
1255 ret i32 %1
1256 }
1258 ; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved.
1259 define i32 @explicit_register_x25(i32 %a) nounwind {
1260 ; RV32I-LABEL: explicit_register_x25:
1261 ; RV32I: # %bb.0:
1262 ; RV32I-NEXT: addi sp, sp, -16
1263 ; RV32I-NEXT: sw s9, 12(sp)
1264 ; RV32I-NEXT: mv s9, a0
1265 ; RV32I-NEXT: #APP
1266 ; RV32I-NEXT: addi a0, s9, 0
1267 ; RV32I-NEXT: #NO_APP
1268 ; RV32I-NEXT: lw s9, 12(sp)
1269 ; RV32I-NEXT: addi sp, sp, 16
1270 ; RV32I-NEXT: ret
1271 ;
1272 ; RV64I-LABEL: explicit_register_x25:
1273 ; RV64I: # %bb.0:
1274 ; RV64I-NEXT: addi sp, sp, -16
1275 ; RV64I-NEXT: sd s9, 8(sp)
1276 ; RV64I-NEXT: mv s9, a0
1277 ; RV64I-NEXT: #APP
1278 ; RV64I-NEXT: addi a0, s9, 0
1279 ; RV64I-NEXT: #NO_APP
1280 ; RV64I-NEXT: ld s9, 8(sp)
1281 ; RV64I-NEXT: addi sp, sp, 16
1282 ; RV64I-NEXT: ret
1283 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a)
1284 ret i32 %1
1285 }
1287 ; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved.
1288 define i32 @explicit_register_s9(i32 %a) nounwind {
1289 ; RV32I-LABEL: explicit_register_s9:
1290 ; RV32I: # %bb.0:
1291 ; RV32I-NEXT: addi sp, sp, -16
1292 ; RV32I-NEXT: sw s9, 12(sp)
1293 ; RV32I-NEXT: mv s9, a0
1294 ; RV32I-NEXT: #APP
1295 ; RV32I-NEXT: addi a0, s9, 0
1296 ; RV32I-NEXT: #NO_APP
1297 ; RV32I-NEXT: lw s9, 12(sp)
1298 ; RV32I-NEXT: addi sp, sp, 16
1299 ; RV32I-NEXT: ret
1300 ;
1301 ; RV64I-LABEL: explicit_register_s9:
1302 ; RV64I: # %bb.0:
1303 ; RV64I-NEXT: addi sp, sp, -16
1304 ; RV64I-NEXT: sd s9, 8(sp)
1305 ; RV64I-NEXT: mv s9, a0
1306 ; RV64I-NEXT: #APP
1307 ; RV64I-NEXT: addi a0, s9, 0
1308 ; RV64I-NEXT: #NO_APP
1309 ; RV64I-NEXT: ld s9, 8(sp)
1310 ; RV64I-NEXT: addi sp, sp, 16
1311 ; RV64I-NEXT: ret
1312 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a)
1313 ret i32 %1
1314 }
1316 ; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved.
1317 define i32 @explicit_register_x26(i32 %a) nounwind {
1318 ; RV32I-LABEL: explicit_register_x26:
1319 ; RV32I: # %bb.0:
1320 ; RV32I-NEXT: addi sp, sp, -16
1321 ; RV32I-NEXT: sw s10, 12(sp)
1322 ; RV32I-NEXT: mv s10, a0
1323 ; RV32I-NEXT: #APP
1324 ; RV32I-NEXT: addi a0, s10, 0
1325 ; RV32I-NEXT: #NO_APP
1326 ; RV32I-NEXT: lw s10, 12(sp)
1327 ; RV32I-NEXT: addi sp, sp, 16
1328 ; RV32I-NEXT: ret
1329 ;
1330 ; RV64I-LABEL: explicit_register_x26:
1331 ; RV64I: # %bb.0:
1332 ; RV64I-NEXT: addi sp, sp, -16
1333 ; RV64I-NEXT: sd s10, 8(sp)
1334 ; RV64I-NEXT: mv s10, a0
1335 ; RV64I-NEXT: #APP
1336 ; RV64I-NEXT: addi a0, s10, 0
1337 ; RV64I-NEXT: #NO_APP
1338 ; RV64I-NEXT: ld s10, 8(sp)
1339 ; RV64I-NEXT: addi sp, sp, 16
1340 ; RV64I-NEXT: ret
1341 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a)
1342 ret i32 %1
1343 }
1345 ; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved.
1346 define i32 @explicit_register_s10(i32 %a) nounwind {
1347 ; RV32I-LABEL: explicit_register_s10:
1348 ; RV32I: # %bb.0:
1349 ; RV32I-NEXT: addi sp, sp, -16
1350 ; RV32I-NEXT: sw s10, 12(sp)
1351 ; RV32I-NEXT: mv s10, a0
1352 ; RV32I-NEXT: #APP
1353 ; RV32I-NEXT: addi a0, s10, 0
1354 ; RV32I-NEXT: #NO_APP
1355 ; RV32I-NEXT: lw s10, 12(sp)
1356 ; RV32I-NEXT: addi sp, sp, 16
1357 ; RV32I-NEXT: ret
1358 ;
1359 ; RV64I-LABEL: explicit_register_s10:
1360 ; RV64I: # %bb.0:
1361 ; RV64I-NEXT: addi sp, sp, -16
1362 ; RV64I-NEXT: sd s10, 8(sp)
1363 ; RV64I-NEXT: mv s10, a0
1364 ; RV64I-NEXT: #APP
1365 ; RV64I-NEXT: addi a0, s10, 0
1366 ; RV64I-NEXT: #NO_APP
1367 ; RV64I-NEXT: ld s10, 8(sp)
1368 ; RV64I-NEXT: addi sp, sp, 16
1369 ; RV64I-NEXT: ret
1370 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a)
1371 ret i32 %1
1372 }
1374 ; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved.
1375 define i32 @explicit_register_x27(i32 %a) nounwind {
1376 ; RV32I-LABEL: explicit_register_x27:
1377 ; RV32I: # %bb.0:
1378 ; RV32I-NEXT: addi sp, sp, -16
1379 ; RV32I-NEXT: sw s11, 12(sp)
1380 ; RV32I-NEXT: mv s11, a0
1381 ; RV32I-NEXT: #APP
1382 ; RV32I-NEXT: addi a0, s11, 0
1383 ; RV32I-NEXT: #NO_APP
1384 ; RV32I-NEXT: lw s11, 12(sp)
1385 ; RV32I-NEXT: addi sp, sp, 16
1386 ; RV32I-NEXT: ret
1387 ;
1388 ; RV64I-LABEL: explicit_register_x27:
1389 ; RV64I: # %bb.0:
1390 ; RV64I-NEXT: addi sp, sp, -16
1391 ; RV64I-NEXT: sd s11, 8(sp)
1392 ; RV64I-NEXT: mv s11, a0
1393 ; RV64I-NEXT: #APP
1394 ; RV64I-NEXT: addi a0, s11, 0
1395 ; RV64I-NEXT: #NO_APP
1396 ; RV64I-NEXT: ld s11, 8(sp)
1397 ; RV64I-NEXT: addi sp, sp, 16
1398 ; RV64I-NEXT: ret
1399 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a)
1400 ret i32 %1
1401 }
1403 ; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved.
1404 define i32 @explicit_register_s11(i32 %a) nounwind {
1405 ; RV32I-LABEL: explicit_register_s11:
1406 ; RV32I: # %bb.0:
1407 ; RV32I-NEXT: addi sp, sp, -16
1408 ; RV32I-NEXT: sw s11, 12(sp)
1409 ; RV32I-NEXT: mv s11, a0
1410 ; RV32I-NEXT: #APP
1411 ; RV32I-NEXT: addi a0, s11, 0
1412 ; RV32I-NEXT: #NO_APP
1413 ; RV32I-NEXT: lw s11, 12(sp)
1414 ; RV32I-NEXT: addi sp, sp, 16
1415 ; RV32I-NEXT: ret
1416 ;
1417 ; RV64I-LABEL: explicit_register_s11:
1418 ; RV64I: # %bb.0:
1419 ; RV64I-NEXT: addi sp, sp, -16
1420 ; RV64I-NEXT: sd s11, 8(sp)
1421 ; RV64I-NEXT: mv s11, a0
1422 ; RV64I-NEXT: #APP
1423 ; RV64I-NEXT: addi a0, s11, 0
1424 ; RV64I-NEXT: #NO_APP
1425 ; RV64I-NEXT: ld s11, 8(sp)
1426 ; RV64I-NEXT: addi sp, sp, 16
1427 ; RV64I-NEXT: ret
1428 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a)
1429 ret i32 %1
1430 }
1432 define i32 @explicit_register_x28(i32 %a) nounwind {
1433 ; RV32I-LABEL: explicit_register_x28:
1434 ; RV32I: # %bb.0:
1435 ; RV32I-NEXT: mv t3, a0
1436 ; RV32I-NEXT: #APP
1437 ; RV32I-NEXT: addi a0, t3, 0
1438 ; RV32I-NEXT: #NO_APP
1439 ; RV32I-NEXT: ret
1440 ;
1441 ; RV64I-LABEL: explicit_register_x28:
1442 ; RV64I: # %bb.0:
1443 ; RV64I-NEXT: mv t3, a0
1444 ; RV64I-NEXT: #APP
1445 ; RV64I-NEXT: addi a0, t3, 0
1446 ; RV64I-NEXT: #NO_APP
1447 ; RV64I-NEXT: ret
1448 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x28}"(i32 %a)
1449 ret i32 %1
1450 }
1452 define i32 @explicit_register_t3(i32 %a) nounwind {
1453 ; RV32I-LABEL: explicit_register_t3:
1454 ; RV32I: # %bb.0:
1455 ; RV32I-NEXT: mv t3, a0
1456 ; RV32I-NEXT: #APP
1457 ; RV32I-NEXT: addi a0, t3, 0
1458 ; RV32I-NEXT: #NO_APP
1459 ; RV32I-NEXT: ret
1460 ;
1461 ; RV64I-LABEL: explicit_register_t3:
1462 ; RV64I: # %bb.0:
1463 ; RV64I-NEXT: mv t3, a0
1464 ; RV64I-NEXT: #APP
1465 ; RV64I-NEXT: addi a0, t3, 0
1466 ; RV64I-NEXT: #NO_APP
1467 ; RV64I-NEXT: ret
1468 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t3}"(i32 %a)
1469 ret i32 %1
1470 }
1472 define i32 @explicit_register_x29(i32 %a) nounwind {
1473 ; RV32I-LABEL: explicit_register_x29:
1474 ; RV32I: # %bb.0:
1475 ; RV32I-NEXT: mv t4, a0
1476 ; RV32I-NEXT: #APP
1477 ; RV32I-NEXT: addi a0, t4, 0
1478 ; RV32I-NEXT: #NO_APP
1479 ; RV32I-NEXT: ret
1480 ;
1481 ; RV64I-LABEL: explicit_register_x29:
1482 ; RV64I: # %bb.0:
1483 ; RV64I-NEXT: mv t4, a0
1484 ; RV64I-NEXT: #APP
1485 ; RV64I-NEXT: addi a0, t4, 0
1486 ; RV64I-NEXT: #NO_APP
1487 ; RV64I-NEXT: ret
1488 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x29}"(i32 %a)
1489 ret i32 %1
1490 }
1492 define i32 @explicit_register_t4(i32 %a) nounwind {
1493 ; RV32I-LABEL: explicit_register_t4:
1494 ; RV32I: # %bb.0:
1495 ; RV32I-NEXT: mv t4, a0
1496 ; RV32I-NEXT: #APP
1497 ; RV32I-NEXT: addi a0, t4, 0
1498 ; RV32I-NEXT: #NO_APP
1499 ; RV32I-NEXT: ret
1500 ;
1501 ; RV64I-LABEL: explicit_register_t4:
1502 ; RV64I: # %bb.0:
1503 ; RV64I-NEXT: mv t4, a0
1504 ; RV64I-NEXT: #APP
1505 ; RV64I-NEXT: addi a0, t4, 0
1506 ; RV64I-NEXT: #NO_APP
1507 ; RV64I-NEXT: ret
1508 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t4}"(i32 %a)
1509 ret i32 %1
1510 }
1512 define i32 @explicit_register_x30(i32 %a) nounwind {
1513 ; RV32I-LABEL: explicit_register_x30:
1514 ; RV32I: # %bb.0:
1515 ; RV32I-NEXT: mv t5, a0
1516 ; RV32I-NEXT: #APP
1517 ; RV32I-NEXT: addi a0, t5, 0
1518 ; RV32I-NEXT: #NO_APP
1519 ; RV32I-NEXT: ret
1520 ;
1521 ; RV64I-LABEL: explicit_register_x30:
1522 ; RV64I: # %bb.0:
1523 ; RV64I-NEXT: mv t5, a0
1524 ; RV64I-NEXT: #APP
1525 ; RV64I-NEXT: addi a0, t5, 0
1526 ; RV64I-NEXT: #NO_APP
1527 ; RV64I-NEXT: ret
1528 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x30}"(i32 %a)
1529 ret i32 %1
1530 }
1532 define i32 @explicit_register_t5(i32 %a) nounwind {
1533 ; RV32I-LABEL: explicit_register_t5:
1534 ; RV32I: # %bb.0:
1535 ; RV32I-NEXT: mv t5, a0
1536 ; RV32I-NEXT: #APP
1537 ; RV32I-NEXT: addi a0, t5, 0
1538 ; RV32I-NEXT: #NO_APP
1539 ; RV32I-NEXT: ret
1540 ;
1541 ; RV64I-LABEL: explicit_register_t5:
1542 ; RV64I: # %bb.0:
1543 ; RV64I-NEXT: mv t5, a0
1544 ; RV64I-NEXT: #APP
1545 ; RV64I-NEXT: addi a0, t5, 0
1546 ; RV64I-NEXT: #NO_APP
1547 ; RV64I-NEXT: ret
1548 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t5}"(i32 %a)
1549 ret i32 %1
1550 }
1552 define i32 @explicit_register_x31(i32 %a) nounwind {
1553 ; RV32I-LABEL: explicit_register_x31:
1554 ; RV32I: # %bb.0:
1555 ; RV32I-NEXT: mv t6, a0
1556 ; RV32I-NEXT: #APP
1557 ; RV32I-NEXT: addi a0, t6, 0
1558 ; RV32I-NEXT: #NO_APP
1559 ; RV32I-NEXT: ret
1560 ;
1561 ; RV64I-LABEL: explicit_register_x31:
1562 ; RV64I: # %bb.0:
1563 ; RV64I-NEXT: mv t6, a0
1564 ; RV64I-NEXT: #APP
1565 ; RV64I-NEXT: addi a0, t6, 0
1566 ; RV64I-NEXT: #NO_APP
1567 ; RV64I-NEXT: ret
1568 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x31}"(i32 %a)
1569 ret i32 %1
1570 }
1572 define i32 @explicit_register_t6(i32 %a) nounwind {
1573 ; RV32I-LABEL: explicit_register_t6:
1574 ; RV32I: # %bb.0:
1575 ; RV32I-NEXT: mv t6, a0
1576 ; RV32I-NEXT: #APP
1577 ; RV32I-NEXT: addi a0, t6, 0
1578 ; RV32I-NEXT: #NO_APP
1579 ; RV32I-NEXT: ret
1580 ;
1581 ; RV64I-LABEL: explicit_register_t6:
1582 ; RV64I: # %bb.0:
1583 ; RV64I-NEXT: mv t6, a0
1584 ; RV64I-NEXT: #APP
1585 ; RV64I-NEXT: addi a0, t6, 0
1586 ; RV64I-NEXT: #NO_APP
1587 ; RV64I-NEXT: ret
1588 %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t6}"(i32 %a)
1589 ret i32 %1
1590 }