[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / TableGen / if-empty-list-arg.td
blob39edf58ff29ac8d36c417b7449dfc2670bb06cc0
1 // RUN: llvm-tblgen %s
2 // XFAIL: vg_leak
4 class C<bit cond> {
5   list<int> X = !if(cond, [1, 2, 3], []);
6   list<int> Y = !if(cond, [], [4, 5, 6]);