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[InstCombine] Signed saturation patterns
[llvm-complete.git]
/
test
/
TableGen
/
if-empty-list-arg.td
blob
39edf58ff29ac8d36c417b7449dfc2670bb06cc0
1
// RUN: llvm-tblgen %s
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// XFAIL: vg_leak
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class C<bit cond> {
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list<int> X = !if(cond, [1, 2, 3], []);
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list<int> Y = !if(cond, [], [4, 5, 6]);
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}