1 import("//llvm/utils/TableGen/tablegen.gni")
3 tablegen("RISCVGenAsmWriter") {
4 visibility = [ ":MCTargetDesc" ]
5 args = [ "-gen-asm-writer" ]
6 td_file = "../RISCV.td"
9 tablegen("RISCVGenInstrInfo") {
10 visibility = [ ":tablegen" ]
11 args = [ "-gen-instr-info" ]
12 td_file = "../RISCV.td"
15 tablegen("RISCVGenMCCodeEmitter") {
16 visibility = [ ":MCTargetDesc" ]
17 args = [ "-gen-emitter" ]
18 td_file = "../RISCV.td"
21 tablegen("RISCVGenRegisterInfo") {
22 visibility = [ ":tablegen" ]
23 args = [ "-gen-register-info" ]
24 td_file = "../RISCV.td"
27 tablegen("RISCVGenSubtargetInfo") {
28 visibility = [ ":tablegen" ]
29 args = [ "-gen-subtarget" ]
30 td_file = "../RISCV.td"
33 # This should contain tablegen targets generating .inc files included
34 # by other targets. .inc files only used by .cpp files in this directory
35 # should be in deps on the static_library instead.
43 ":RISCVGenRegisterInfo",
44 ":RISCVGenSubtargetInfo",
48 static_library("MCTargetDesc") {
49 output_name = "LLVMRISCVDesc"
55 ":RISCVGenMCCodeEmitter",
58 "//llvm/lib/Target/RISCV:RISCVGenCompressInstEmitter",
59 "//llvm/lib/Target/RISCV/Utils",
61 include_dirs = [ ".." ]
63 "RISCVAsmBackend.cpp",
64 "RISCVELFObjectWriter.cpp",
65 "RISCVELFStreamer.cpp",
66 "RISCVInstPrinter.cpp",
68 "RISCVMCCodeEmitter.cpp",
70 "RISCVMCTargetDesc.cpp",
71 "RISCVTargetStreamer.cpp",