lib/Target/PowerPC/PPCHazardRecognizers.cpp

   1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Chris Lattner and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements hazard recognizers for scheduling on PowerPC processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "sched"
  15 #include "PPCHazardRecognizers.h"
  16 #include "PPC.h"
  17 #include "PPCInstrInfo.h"
  18 #include "llvm/Support/Debug.h"
  19 #include <iostream>
  20 using namespace llvm;
  21
  22
  23 //===----------------------------------------------------------------------===//
  24 // PowerPC 970 Hazard Recognizer
  25 //
  26 // This models the dispatch group formation of the PPC970 processor.  Dispatch
  27 // groups are bundles of up to five instructions that can contain various mixes
  28 // of instructions.  The PPC970 can dispatch a peak of 4 non-branch and one
  29 // branch instruction per-cycle.
  30 //
  31 // There are a number of restrictions to dispatch group formation: some
  32 // instructions can only be issued in the first slot of a dispatch group, & some
  33 // instructions fill an entire dispatch group.  Additionally, only branches can
  34 // issue in the 5th (last) slot.
  35 //
  36 // Finally, there are a number of "structural" hazards on the PPC970.  These
  37 // conditions cause large performance penalties due to misprediction, recovery,
  38 // and replay logic that has to happen.  These cases include setting a CTR and
  39 // branching through it in the same dispatch group, and storing to an address,
  40 // then loading from the same address within a dispatch group.  To avoid these
  41 // conditions, we insert no-op instructions when appropriate.
  42 //
  43 // FIXME: This is missing some significant cases:
  44 //   1. Modeling of microcoded instructions.
  45 //   2. Handling of serialized operations.
  46 //   3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
  47 //
  48
  49 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
  50   : TII(tii) {
  51   EndDispatchGroup();
  52 }
  53
  54 void PPCHazardRecognizer970::EndDispatchGroup() {
  55   DEBUG(std::cerr << "=== Start of dispatch group\n");
  56   NumIssued = 0;
  57
  58   // Structural hazard info.
  59   HasCTRSet = false;
  60   NumStores = 0;
  61 }
  62
  63
  64 PPCII::PPC970_Unit
  65 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
  66                                      bool &isFirst, bool &isSingle,
  67                                      bool &isCracked,
  68                                      bool &isLoad, bool &isStore) {
  69   if (Opcode < ISD::BUILTIN_OP_END) {
  70     isFirst = isSingle = isCracked = isLoad = isStore = false;
  71     return PPCII::PPC970_Pseudo;
  72   }
  73   Opcode -= ISD::BUILTIN_OP_END;
  74
  75   const TargetInstrDescriptor &TID = TII.get(Opcode);
  76
  77   isLoad  = TID.Flags & M_LOAD_FLAG;
  78   isStore = TID.Flags & M_STORE_FLAG;
  79
  80   unsigned TSFlags = TID.TSFlags;
  81
  82   isFirst   = TSFlags & PPCII::PPC970_First;
  83   isSingle  = TSFlags & PPCII::PPC970_Single;
  84   isCracked = TSFlags & PPCII::PPC970_Cracked;
  85   return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
  86 }
  87
  88 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
  89 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
  90 bool PPCHazardRecognizer970::
  91 isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
  92   for (unsigned i = 0, e = NumStores; i != e; ++i) {
  93     // Handle exact and commuted addresses.
  94     if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
  95       return true;
  96     if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i])
  97       return true;
  98
  99     // Okay, we don't have an exact match, if this is an indexed offset, see if
 100     // we have overlap (which happens during fp->int conversion for example).
 101     if (StorePtr2[i] == Ptr2) {
 102       if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i]))
 103         if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
 104           // Okay the base pointers match, so we have [c1+r] vs [c2+r].  Check
 105           // to see if the load and store actually overlap.
 106           int StoreOffs = StoreOffset->getValue();
 107           int LoadOffs  = LoadOffset->getValue();
 108           if (StoreOffs < LoadOffs) {
 109             if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true;
 110           } else {
 111             if (int(LoadOffs+LoadSize) > StoreOffs) return true;
 112           }
 113         }
 114     }
 115   }
 116   return false;
 117 }
 118
 119 /// getHazardType - We return hazard for any non-branch instruction that would
 120 /// terminate terminate the dispatch group.  We turn NoopHazard for any
 121 /// instructions that wouldn't terminate the dispatch group that would cause a
 122 /// pipeline flush.
 123 HazardRecognizer::HazardType PPCHazardRecognizer970::
 124 getHazardType(SDNode *Node) {
 125   bool isFirst, isSingle, isCracked, isLoad, isStore;
 126   PPCII::PPC970_Unit InstrType =
 127     GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
 128                  isLoad, isStore);
 129   if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
 130   unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
 131
 132   // We can only issue a PPC970_First/PPC970_Single instruction (such as
 133   // crand/mtspr/etc) if this is the first cycle of the dispatch group.
 134   if (NumIssued != 0 && (isFirst || isSingle))
 135     return Hazard;
 136
 137   // If this instruction is cracked into two ops by the decoder, we know that
 138   // it is not a branch and that it cannot issue if 3 other instructions are
 139   // already in the dispatch group.
 140   if (isCracked && NumIssued > 2)
 141     return Hazard;
 142
 143   switch (InstrType) {
 144   default: assert(0 && "Unknown instruction type!");
 145   case PPCII::PPC970_FXU:
 146   case PPCII::PPC970_LSU:
 147   case PPCII::PPC970_FPU:
 148   case PPCII::PPC970_VALU:
 149   case PPCII::PPC970_VPERM:
 150     // We can only issue a branch as the last instruction in a group.
 151     if (NumIssued == 4) return Hazard;
 152     break;
 153   case PPCII::PPC970_CRU:
 154     // We can only issue a CR instruction in the first two slots.
 155     if (NumIssued >= 2) return Hazard;
 156     break;
 157   case PPCII::PPC970_BRU:
 158     break;
 159   }
 160
 161   // Do not allow MTCTR and BCTRL to be in the same dispatch group.
 162   if (HasCTRSet && Opcode == PPC::BCTRL)
 163     return NoopHazard;
 164
 165   // If this is a load following a store, make sure it's not to the same or
 166   // overlapping address.
 167   if (isLoad && NumStores) {
 168     unsigned LoadSize;
 169     switch (Opcode) {
 170     default: assert(0 && "Unknown load!");
 171     case PPC::LBZ:
 172     case PPC::LBZX:
 173     case PPC::LVEBX:
 174       LoadSize = 1;
 175       break;
 176     case PPC::LHA:
 177     case PPC::LHAX:
 178     case PPC::LHZ:
 179     case PPC::LHZX:
 180     case PPC::LVEHX:
 181       LoadSize = 2;
 182       break;
 183     case PPC::LFS:
 184     case PPC::LFSX:
 185     case PPC::LWZ:
 186     case PPC::LWZX:
 187     case PPC::LWZU:
 188     case PPC::LWA:
 189     case PPC::LWAX:
 190     case PPC::LVEWX:
 191       LoadSize = 4;
 192       break;
 193     case PPC::LFD:
 194     case PPC::LFDX:
 195     case PPC::LD:
 196     case PPC::LDX:
 197       LoadSize = 8;
 198       break;
 199     case PPC::LVX:
 200       LoadSize = 16;
 201       break;
 202     }
 203
 204     if (isLoadOfStoredAddress(LoadSize,
 205                               Node->getOperand(0), Node->getOperand(1)))
 206       return NoopHazard;
 207   }
 208
 209   return NoHazard;
 210 }
 211
 212 void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
 213   bool isFirst, isSingle, isCracked, isLoad, isStore;
 214   PPCII::PPC970_Unit InstrType =
 215     GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
 216                  isLoad, isStore);
 217   if (InstrType == PPCII::PPC970_Pseudo) return;
 218   unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
 219
 220   // Update structural hazard information.
 221   if (Opcode == PPC::MTCTR) HasCTRSet = true;
 222
 223   // Track the address stored to.
 224   if (isStore) {
 225     unsigned ThisStoreSize;
 226     switch (Opcode) {
 227     default: assert(0 && "Unknown store instruction!");
 228     case PPC::STBX:
 229     case PPC::STB:
 230     case PPC::STVEBX:
 231       ThisStoreSize = 1;
 232       break;
 233     case PPC::STHX:
 234     case PPC::STH:
 235     case PPC::STVEHX:
 236       ThisStoreSize = 2;
 237       break;
 238     case PPC::STFS:
 239     case PPC::STFSX:
 240     case PPC::STWU:
 241     case PPC::STWX:
 242     case PPC::STWUX:
 243     case PPC::STW:
 244     case PPC::STVEWX:
 245     case PPC::STFIWX:
 246       ThisStoreSize = 4;
 247       break;
 248     case PPC::STD_32:
 249     case PPC::STDX_32:
 250     case PPC::STD:
 251     case PPC::STFD:
 252     case PPC::STFDX:
 253     case PPC::STDX:
 254     case PPC::STDUX:
 255       ThisStoreSize = 8;
 256       break;
 257     case PPC::STVX:
 258       ThisStoreSize = 16;
 259       break;
 260     }
 261
 262     StoreSize[NumStores] = ThisStoreSize;
 263     StorePtr1[NumStores] = Node->getOperand(1);
 264     StorePtr2[NumStores] = Node->getOperand(2);
 265     ++NumStores;
 266   }
 267
 268   if (InstrType == PPCII::PPC970_BRU || isSingle)
 269     NumIssued = 4;  // Terminate a d-group.
 270   ++NumIssued;
 271
 272   // If this instruction is cracked into two ops by the decoder, remember that
 273   // we issued two pieces.
 274   if (isCracked)
 275     ++NumIssued;
 276
 277   if (NumIssued == 5)
 278     EndDispatchGroup();
 279 }
 280
 281 void PPCHazardRecognizer970::AdvanceCycle() {
 282   assert(NumIssued < 5 && "Illegal dispatch group!");
 283   ++NumIssued;
 284   if (NumIssued == 5)
 285     EndDispatchGroup();
 286 }
 287
 288 void PPCHazardRecognizer970::EmitNoop() {
 289   AdvanceCycle();
 290 }