lib/Target/ARM/ARMCallLowering.cpp

   1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// This file implements the lowering of LLVM calls to machine code calls for
  11 /// GlobalISel.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "ARMCallLowering.h"
  16 #include "ARMBaseInstrInfo.h"
  17 #include "ARMISelLowering.h"
  18 #include "ARMSubtarget.h"
  19 #include "Utils/ARMBaseInfo.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/CodeGen/Analysis.h"
  22 #include "llvm/CodeGen/CallingConvLower.h"
  23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
  24 #include "llvm/CodeGen/GlobalISel/Utils.h"
  25 #include "llvm/CodeGen/LowLevelType.h"
  26 #include "llvm/CodeGen/MachineBasicBlock.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineFunction.h"
  29 #include "llvm/CodeGen/MachineInstrBuilder.h"
  30 #include "llvm/CodeGen/MachineMemOperand.h"
  31 #include "llvm/CodeGen/MachineOperand.h"
  32 #include "llvm/CodeGen/MachineRegisterInfo.h"
  33 #include "llvm/CodeGen/TargetRegisterInfo.h"
  34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  35 #include "llvm/CodeGen/ValueTypes.h"
  36 #include "llvm/IR/Attributes.h"
  37 #include "llvm/IR/DataLayout.h"
  38 #include "llvm/IR/DerivedTypes.h"
  39 #include "llvm/IR/Function.h"
  40 #include "llvm/IR/Type.h"
  41 #include "llvm/IR/Value.h"
  42 #include "llvm/Support/Casting.h"
  43 #include "llvm/Support/LowLevelTypeImpl.h"
  44 #include "llvm/Support/MachineValueType.h"
  45 #include <algorithm>
  46 #include <cassert>
  47 #include <cstdint>
  48 #include <utility>
  49
  50 using namespace llvm;
  51
  52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
  53     : CallLowering(&TLI) {}
  54
  55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
  56                             Type *T) {
  57   if (T->isArrayTy())
  58     return isSupportedType(DL, TLI, T->getArrayElementType());
  59
  60   if (T->isStructTy()) {
  61     // For now we only allow homogeneous structs that we can manipulate with
  62     // G_MERGE_VALUES and G_UNMERGE_VALUES
  63     auto StructT = cast<StructType>(T);
  64     for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
  65       if (StructT->getElementType(i) != StructT->getElementType(0))
  66         return false;
  67     return isSupportedType(DL, TLI, StructT->getElementType(0));
  68   }
  69
  70   EVT VT = TLI.getValueType(DL, T, true);
  71   if (!VT.isSimple() || VT.isVector() ||
  72       !(VT.isInteger() || VT.isFloatingPoint()))
  73     return false;
  74
  75   unsigned VTSize = VT.getSimpleVT().getSizeInBits();
  76
  77   if (VTSize == 64)
  78     // FIXME: Support i64 too
  79     return VT.isFloatingPoint();
  80
  81   return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
  82 }
  83
  84 namespace {
  85
  86 /// Helper class for values going out through an ABI boundary (used for handling
  87 /// function return values and call parameters).
  88 struct OutgoingValueHandler : public CallLowering::ValueHandler {
  89   OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
  90                        MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
  91       : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
  92
  93   Register getStackAddress(uint64_t Size, int64_t Offset,
  94                            MachinePointerInfo &MPO) override {
  95     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
  96            "Unsupported size");
  97
  98     LLT p0 = LLT::pointer(0, 32);
  99     LLT s32 = LLT::scalar(32);
 100     Register SPReg = MRI.createGenericVirtualRegister(p0);
 101     MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
 102
 103     Register OffsetReg = MRI.createGenericVirtualRegister(s32);
 104     MIRBuilder.buildConstant(OffsetReg, Offset);
 105
 106     Register AddrReg = MRI.createGenericVirtualRegister(p0);
 107     MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
 108
 109     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
 110     return AddrReg;
 111   }
 112
 113   void assignValueToReg(Register ValVReg, Register PhysReg,
 114                         CCValAssign &VA) override {
 115     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
 116     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
 117
 118     assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
 119     assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
 120
 121     Register ExtReg = extendRegister(ValVReg, VA);
 122     MIRBuilder.buildCopy(PhysReg, ExtReg);
 123     MIB.addUse(PhysReg, RegState::Implicit);
 124   }
 125
 126   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
 127                             MachinePointerInfo &MPO, CCValAssign &VA) override {
 128     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
 129            "Unsupported size");
 130
 131     Register ExtReg = extendRegister(ValVReg, VA);
 132     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
 133         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
 134         /* Alignment */ 1);
 135     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
 136   }
 137
 138   unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
 139                              ArrayRef<CCValAssign> VAs) override {
 140     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
 141
 142     CCValAssign VA = VAs[0];
 143     assert(VA.needsCustom() && "Value doesn't need custom handling");
 144     assert(VA.getValVT() == MVT::f64 && "Unsupported type");
 145
 146     CCValAssign NextVA = VAs[1];
 147     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
 148     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
 149
 150     assert(VA.getValNo() == NextVA.getValNo() &&
 151            "Values belong to different arguments");
 152
 153     assert(VA.isRegLoc() && "Value should be in reg");
 154     assert(NextVA.isRegLoc() && "Value should be in reg");
 155
 156     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
 157                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
 158     MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
 159
 160     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
 161     if (!IsLittle)
 162       std::swap(NewRegs[0], NewRegs[1]);
 163
 164     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
 165     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
 166
 167     return 1;
 168   }
 169
 170   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
 171                  CCValAssign::LocInfo LocInfo,
 172                  const CallLowering::ArgInfo &Info, CCState &State) override {
 173     if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State))
 174       return true;
 175
 176     StackSize =
 177         std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
 178     return false;
 179   }
 180
 181   MachineInstrBuilder &MIB;
 182   uint64_t StackSize = 0;
 183 };
 184
 185 } // end anonymous namespace
 186
 187 void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
 188                                         SmallVectorImpl<ArgInfo> &SplitArgs,
 189                                         MachineFunction &MF) const {
 190   const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
 191   LLVMContext &Ctx = OrigArg.Ty->getContext();
 192   const DataLayout &DL = MF.getDataLayout();
 193   const Function &F = MF.getFunction();
 194
 195   SmallVector<EVT, 4> SplitVTs;
 196   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
 197   assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
 198
 199   if (SplitVTs.size() == 1) {
 200     // Even if there is no splitting to do, we still want to replace the
 201     // original type (e.g. pointer type -> integer).
 202     auto Flags = OrigArg.Flags;
 203     unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
 204     Flags.setOrigAlign(OriginalAlignment);
 205     SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
 206                            Flags, OrigArg.IsFixed);
 207     return;
 208   }
 209
 210   // Create one ArgInfo for each virtual register.
 211   for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
 212     EVT SplitVT = SplitVTs[i];
 213     Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
 214     auto Flags = OrigArg.Flags;
 215
 216     unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
 217     Flags.setOrigAlign(OriginalAlignment);
 218
 219     bool NeedsConsecutiveRegisters =
 220         TLI.functionArgumentNeedsConsecutiveRegisters(
 221             SplitTy, F.getCallingConv(), F.isVarArg());
 222     if (NeedsConsecutiveRegisters) {
 223       Flags.setInConsecutiveRegs();
 224       if (i == e - 1)
 225         Flags.setInConsecutiveRegsLast();
 226     }
 227
 228     // FIXME: We also want to split SplitTy further.
 229     Register PartReg = OrigArg.Regs[i];
 230     SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
 231   }
 232 }
 233
 234 /// Lower the return value for the already existing \p Ret. This assumes that
 235 /// \p MIRBuilder's insertion point is correct.
 236 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
 237                                      const Value *Val, ArrayRef<Register> VRegs,
 238                                      MachineInstrBuilder &Ret) const {
 239   if (!Val)
 240     // Nothing to do here.
 241     return true;
 242
 243   auto &MF = MIRBuilder.getMF();
 244   const auto &F = MF.getFunction();
 245
 246   auto DL = MF.getDataLayout();
 247   auto &TLI = *getTLI<ARMTargetLowering>();
 248   if (!isSupportedType(DL, TLI, Val->getType()))
 249     return false;
 250
 251   ArgInfo OrigRetInfo(VRegs, Val->getType());
 252   setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
 253
 254   SmallVector<ArgInfo, 4> SplitRetInfos;
 255   splitToValueTypes(OrigRetInfo, SplitRetInfos, MF);
 256
 257   CCAssignFn *AssignFn =
 258       TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
 259
 260   OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
 261   return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
 262 }
 263
 264 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
 265                                   const Value *Val,
 266                                   ArrayRef<Register> VRegs) const {
 267   assert(!Val == VRegs.empty() && "Return value without a vreg");
 268
 269   auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
 270   unsigned Opcode = ST.getReturnOpcode();
 271   auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
 272
 273   if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
 274     return false;
 275
 276   MIRBuilder.insertInstr(Ret);
 277   return true;
 278 }
 279
 280 namespace {
 281
 282 /// Helper class for values coming in through an ABI boundary (used for handling
 283 /// formal arguments and call return values).
 284 struct IncomingValueHandler : public CallLowering::ValueHandler {
 285   IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 286                        CCAssignFn AssignFn)
 287       : ValueHandler(MIRBuilder, MRI, AssignFn) {}
 288
 289   bool isArgumentHandler() const override { return true; }
 290
 291   Register getStackAddress(uint64_t Size, int64_t Offset,
 292                            MachinePointerInfo &MPO) override {
 293     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
 294            "Unsupported size");
 295
 296     auto &MFI = MIRBuilder.getMF().getFrameInfo();
 297
 298     int FI = MFI.CreateFixedObject(Size, Offset, true);
 299     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
 300
 301     unsigned AddrReg =
 302         MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
 303     MIRBuilder.buildFrameIndex(AddrReg, FI);
 304
 305     return AddrReg;
 306   }
 307
 308   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
 309                             MachinePointerInfo &MPO, CCValAssign &VA) override {
 310     assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
 311            "Unsupported size");
 312
 313     if (VA.getLocInfo() == CCValAssign::SExt ||
 314         VA.getLocInfo() == CCValAssign::ZExt) {
 315       // If the value is zero- or sign-extended, its size becomes 4 bytes, so
 316       // that's what we should load.
 317       Size = 4;
 318       assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
 319
 320       auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
 321       buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO);
 322       MIRBuilder.buildTrunc(ValVReg, LoadVReg);
 323     } else {
 324       // If the value is not extended, a simple load will suffice.
 325       buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO);
 326     }
 327   }
 328
 329   void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
 330                  MachinePointerInfo &MPO) {
 331     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
 332         MPO, MachineMemOperand::MOLoad, Size, Alignment);
 333     MIRBuilder.buildLoad(Val, Addr, *MMO);
 334   }
 335
 336   void assignValueToReg(Register ValVReg, Register PhysReg,
 337                         CCValAssign &VA) override {
 338     assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
 339     assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
 340
 341     auto ValSize = VA.getValVT().getSizeInBits();
 342     auto LocSize = VA.getLocVT().getSizeInBits();
 343
 344     assert(ValSize <= 64 && "Unsupported value size");
 345     assert(LocSize <= 64 && "Unsupported location size");
 346
 347     markPhysRegUsed(PhysReg);
 348     if (ValSize == LocSize) {
 349       MIRBuilder.buildCopy(ValVReg, PhysReg);
 350     } else {
 351       assert(ValSize < LocSize && "Extensions not supported");
 352
 353       // We cannot create a truncating copy, nor a trunc of a physical register.
 354       // Therefore, we need to copy the content of the physical register into a
 355       // virtual one and then truncate that.
 356       auto PhysRegToVReg =
 357           MRI.createGenericVirtualRegister(LLT::scalar(LocSize));
 358       MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
 359       MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
 360     }
 361   }
 362
 363   unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
 364                              ArrayRef<CCValAssign> VAs) override {
 365     assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
 366
 367     CCValAssign VA = VAs[0];
 368     assert(VA.needsCustom() && "Value doesn't need custom handling");
 369     assert(VA.getValVT() == MVT::f64 && "Unsupported type");
 370
 371     CCValAssign NextVA = VAs[1];
 372     assert(NextVA.needsCustom() && "Value doesn't need custom handling");
 373     assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
 374
 375     assert(VA.getValNo() == NextVA.getValNo() &&
 376            "Values belong to different arguments");
 377
 378     assert(VA.isRegLoc() && "Value should be in reg");
 379     assert(NextVA.isRegLoc() && "Value should be in reg");
 380
 381     Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
 382                           MRI.createGenericVirtualRegister(LLT::scalar(32))};
 383
 384     assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
 385     assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
 386
 387     bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
 388     if (!IsLittle)
 389       std::swap(NewRegs[0], NewRegs[1]);
 390
 391     MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
 392
 393     return 1;
 394   }
 395
 396   /// Marking a physical register as used is different between formal
 397   /// parameters, where it's a basic block live-in, and call returns, where it's
 398   /// an implicit-def of the call instruction.
 399   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
 400 };
 401
 402 struct FormalArgHandler : public IncomingValueHandler {
 403   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 404                    CCAssignFn AssignFn)
 405       : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
 406
 407   void markPhysRegUsed(unsigned PhysReg) override {
 408     MIRBuilder.getMRI()->addLiveIn(PhysReg);
 409     MIRBuilder.getMBB().addLiveIn(PhysReg);
 410   }
 411 };
 412
 413 } // end anonymous namespace
 414
 415 bool ARMCallLowering::lowerFormalArguments(
 416     MachineIRBuilder &MIRBuilder, const Function &F,
 417     ArrayRef<ArrayRef<Register>> VRegs) const {
 418   auto &TLI = *getTLI<ARMTargetLowering>();
 419   auto Subtarget = TLI.getSubtarget();
 420
 421   if (Subtarget->isThumb1Only())
 422     return false;
 423
 424   // Quick exit if there aren't any args
 425   if (F.arg_empty())
 426     return true;
 427
 428   if (F.isVarArg())
 429     return false;
 430
 431   auto &MF = MIRBuilder.getMF();
 432   auto &MBB = MIRBuilder.getMBB();
 433   auto DL = MF.getDataLayout();
 434
 435   for (auto &Arg : F.args()) {
 436     if (!isSupportedType(DL, TLI, Arg.getType()))
 437       return false;
 438     if (Arg.hasByValOrInAllocaAttr())
 439       return false;
 440   }
 441
 442   CCAssignFn *AssignFn =
 443       TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
 444
 445   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
 446                               AssignFn);
 447
 448   SmallVector<ArgInfo, 8> SplitArgInfos;
 449   unsigned Idx = 0;
 450   for (auto &Arg : F.args()) {
 451     ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
 452
 453     setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
 454     splitToValueTypes(OrigArgInfo, SplitArgInfos, MF);
 455
 456     Idx++;
 457   }
 458
 459   if (!MBB.empty())
 460     MIRBuilder.setInstr(*MBB.begin());
 461
 462   if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
 463     return false;
 464
 465   // Move back to the end of the basic block.
 466   MIRBuilder.setMBB(MBB);
 467   return true;
 468 }
 469
 470 namespace {
 471
 472 struct CallReturnHandler : public IncomingValueHandler {
 473   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 474                     MachineInstrBuilder MIB, CCAssignFn *AssignFn)
 475       : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
 476
 477   void markPhysRegUsed(unsigned PhysReg) override {
 478     MIB.addDef(PhysReg, RegState::Implicit);
 479   }
 480
 481   MachineInstrBuilder MIB;
 482 };
 483
 484 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
 485 unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) {
 486   if (isDirect)
 487     return STI.isThumb() ? ARM::tBL : ARM::BL;
 488
 489   if (STI.isThumb())
 490     return ARM::tBLXr;
 491
 492   if (STI.hasV5TOps())
 493     return ARM::BLX;
 494
 495   if (STI.hasV4TOps())
 496     return ARM::BX_CALL;
 497
 498   return ARM::BMOVPCRX_CALL;
 499 }
 500 } // end anonymous namespace
 501
 502 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
 503                                 CallingConv::ID CallConv,
 504                                 const MachineOperand &Callee,
 505                                 const ArgInfo &OrigRet,
 506                                 ArrayRef<ArgInfo> OrigArgs,
 507                                 const MDNode *KnownCallees) const {
 508   MachineFunction &MF = MIRBuilder.getMF();
 509   const auto &TLI = *getTLI<ARMTargetLowering>();
 510   const auto &DL = MF.getDataLayout();
 511   const auto &STI = MF.getSubtarget<ARMSubtarget>();
 512   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 513   MachineRegisterInfo &MRI = MF.getRegInfo();
 514
 515   if (STI.genLongCalls())
 516     return false;
 517
 518   if (STI.isThumb1Only())
 519     return false;
 520
 521   auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
 522
 523   // Create the call instruction so we can add the implicit uses of arg
 524   // registers, but don't insert it yet.
 525   bool IsDirect = !Callee.isReg();
 526   auto CallOpcode = getCallOpcode(STI, IsDirect);
 527   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
 528
 529   bool IsThumb = STI.isThumb();
 530   if (IsThumb)
 531     MIB.add(predOps(ARMCC::AL));
 532
 533   MIB.add(Callee);
 534   if (!IsDirect) {
 535     auto CalleeReg = Callee.getReg();
 536     if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
 537       unsigned CalleeIdx = IsThumb ? 2 : 0;
 538       MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
 539           MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
 540           *MIB.getInstr(), MIB->getDesc(), Callee, CalleeIdx));
 541     }
 542   }
 543
 544   MIB.addRegMask(TRI->getCallPreservedMask(MF, CallConv));
 545
 546   bool IsVarArg = false;
 547   SmallVector<ArgInfo, 8> ArgInfos;
 548   for (auto Arg : OrigArgs) {
 549     if (!isSupportedType(DL, TLI, Arg.Ty))
 550       return false;
 551
 552     if (!Arg.IsFixed)
 553       IsVarArg = true;
 554
 555     if (Arg.Flags.isByVal())
 556       return false;
 557
 558     splitToValueTypes(Arg, ArgInfos, MF);
 559   }
 560
 561   auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, IsVarArg);
 562   OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
 563   if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
 564     return false;
 565
 566   // Now we can add the actual call instruction to the correct basic block.
 567   MIRBuilder.insertInstr(MIB);
 568
 569   if (!OrigRet.Ty->isVoidTy()) {
 570     if (!isSupportedType(DL, TLI, OrigRet.Ty))
 571       return false;
 572
 573     ArgInfos.clear();
 574     splitToValueTypes(OrigRet, ArgInfos, MF);
 575     auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, IsVarArg);
 576     CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
 577     if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
 578       return false;
 579   }
 580
 581   // We now know the size of the stack - update the ADJCALLSTACKDOWN
 582   // accordingly.
 583   CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
 584
 585   MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
 586       .addImm(ArgHandler.StackSize)
 587       .addImm(0)
 588       .add(predOps(ARMCC::AL));
 589
 590   return true;
 591 }