| blob | ef2814be2ce24c110d708fb1dfb1c828070ec5d5 |
1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the Thumb instruction set.
10 //
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Thumb specific DAG Nodes.
15 //
17 def imm_sr_XFORM: SDNodeXForm<imm, [{
18 unsigned Imm = N->getZExtValue();
19 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
20 }]>;
21 def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; }
22 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
23 uint64_t Imm = N->getZExtValue();
24 return Imm > 0 && Imm <= 32;
25 }], imm_sr_XFORM> {
26 let PrintMethod = "printThumbSRImm";
27 let ParserMatchClass = ThumbSRImmAsmOperand;
28 }
30 def imm0_7_neg : PatLeaf<(i32 imm), [{
31 return (uint32_t)-N->getZExtValue() < 8;
32 }], imm_neg_XFORM>;
34 def ThumbModImmNeg1_7AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg1_7"; }
35 def mod_imm1_7_neg : Operand<i32>, PatLeaf<(imm), [{
36 unsigned Value = -(unsigned)N->getZExtValue();
37 return 0 < Value && Value < 8;
38 }], imm_neg_XFORM> {
39 let ParserMatchClass = ThumbModImmNeg1_7AsmOperand;
40 }
42 def ThumbModImmNeg8_255AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg8_255"; }
43 def mod_imm8_255_neg : Operand<i32>, PatLeaf<(imm), [{
44 unsigned Value = -(unsigned)N->getZExtValue();
45 return 7 < Value && Value < 256;
46 }], imm_neg_XFORM> {
47 let ParserMatchClass = ThumbModImmNeg8_255AsmOperand;
48 }
51 def imm0_255_comp : PatLeaf<(i32 imm), [{
52 return ~((uint32_t)N->getZExtValue()) < 256;
53 }]>;
55 def imm8_255_neg : PatLeaf<(i32 imm), [{
56 unsigned Val = -N->getZExtValue();
57 return Val >= 8 && Val < 256;
58 }], imm_neg_XFORM>;
60 // Break imm's up into two pieces: an immediate + a left shift. This uses
61 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
62 // to get the val/shift pieces.
63 def thumb_immshifted : PatLeaf<(imm), [{
64 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 }]>;
67 def thumb_immshifted_val : SDNodeXForm<imm, [{
68 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
69 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
70 }]>;
72 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
73 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
74 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
75 }]>;
77 def imm256_510 : ImmLeaf<i32, [{
78 return Imm >= 256 && Imm < 511;
79 }]>;
81 def thumb_imm256_510_addend : SDNodeXForm<imm, [{
82 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);
83 }]>;
85 // Scaled 4 immediate.
86 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
87 def t_imm0_1020s4 : Operand<i32> {
88 let PrintMethod = "printThumbS4ImmOperand";
89 let ParserMatchClass = t_imm0_1020s4_asmoperand;
90 let OperandType = "OPERAND_IMMEDIATE";
91 }
93 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
94 def t_imm0_508s4 : Operand<i32> {
95 let PrintMethod = "printThumbS4ImmOperand";
96 let ParserMatchClass = t_imm0_508s4_asmoperand;
97 let OperandType = "OPERAND_IMMEDIATE";
98 }
99 // Alias use only, so no printer is necessary.
100 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
101 def t_imm0_508s4_neg : Operand<i32> {
102 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
103 let OperandType = "OPERAND_IMMEDIATE";
104 }
106 // Define Thumb specific addressing modes.
108 // unsigned 8-bit, 2-scaled memory offset
109 class OperandUnsignedOffset_b8s2 : AsmOperandClass {
110 let Name = "UnsignedOffset_b8s2";
111 let PredicateMethod = "isUnsignedOffset<8, 2>";
112 }
114 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
116 // thumb style PC relative operand. signed, 8 bits magnitude,
117 // two bits shift. can be represented as either [pc, #imm], #imm,
118 // or relocatable expression...
119 def ThumbMemPC : AsmOperandClass {
120 let Name = "ThumbMemPC";
121 }
123 let OperandType = "OPERAND_PCREL" in {
124 def t_brtarget : Operand<OtherVT> {
125 let EncoderMethod = "getThumbBRTargetOpValue";
126 let DecoderMethod = "DecodeThumbBROperand";
127 }
129 // ADR instruction labels.
130 def t_adrlabel : Operand<i32> {
131 let EncoderMethod = "getThumbAdrLabelOpValue";
132 let PrintMethod = "printAdrLabelOperand<2>";
133 let ParserMatchClass = UnsignedOffset_b8s2;
134 }
137 def thumb_br_target : Operand<OtherVT> {
138 let ParserMatchClass = ThumbBranchTarget;
139 let EncoderMethod = "getThumbBranchTargetOpValue";
140 let OperandType = "OPERAND_PCREL";
141 }
143 def thumb_bl_target : Operand<i32> {
144 let ParserMatchClass = ThumbBranchTarget;
145 let EncoderMethod = "getThumbBLTargetOpValue";
146 let DecoderMethod = "DecodeThumbBLTargetOperand";
147 }
149 // Target for BLX *from* thumb mode.
150 def thumb_blx_target : Operand<i32> {
151 let ParserMatchClass = ARMBranchTarget;
152 let EncoderMethod = "getThumbBLXTargetOpValue";
153 let DecoderMethod = "DecodeThumbBLXOffset";
154 }
156 def thumb_bcc_target : Operand<OtherVT> {
157 let ParserMatchClass = ThumbBranchTarget;
158 let EncoderMethod = "getThumbBCCTargetOpValue";
159 let DecoderMethod = "DecodeThumbBCCTargetOperand";
160 }
162 def thumb_cb_target : Operand<OtherVT> {
163 let ParserMatchClass = ThumbBranchTarget;
164 let EncoderMethod = "getThumbCBTargetOpValue";
165 let DecoderMethod = "DecodeThumbCmpBROperand";
166 }
168 // t_addrmode_pc := <label> => pc + imm8 * 4
169 //
170 def t_addrmode_pc : MemOperand {
171 let EncoderMethod = "getAddrModePCOpValue";
172 let DecoderMethod = "DecodeThumbAddrModePC";
173 let PrintMethod = "printThumbLdrLabelOperand";
174 let ParserMatchClass = ThumbMemPC;
175 }
176 }
178 // t_addrmode_rr := reg + reg
179 //
180 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
181 def t_addrmode_rr : MemOperand,
182 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
183 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
184 let PrintMethod = "printThumbAddrModeRROperand";
185 let DecoderMethod = "DecodeThumbAddrModeRR";
186 let ParserMatchClass = t_addrmode_rr_asm_operand;
187 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
188 }
190 // t_addrmode_rr_sext := reg + reg
191 //
192 // This is similar to t_addrmode_rr, but uses different heuristics for
193 // ldrsb/ldrsh.
194 def t_addrmode_rr_sext : MemOperand,
195 ComplexPattern<i32, 2, "SelectThumbAddrModeRRSext", []> {
196 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
197 let PrintMethod = "printThumbAddrModeRROperand";
198 let DecoderMethod = "DecodeThumbAddrModeRR";
199 let ParserMatchClass = t_addrmode_rr_asm_operand;
200 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
201 }
203 // t_addrmode_rrs := reg + reg
204 //
205 // We use separate scaled versions because the Select* functions need
206 // to explicitly check for a matching constant and return false here so that
207 // the reg+imm forms will match instead. This is a horrible way to do that,
208 // as it forces tight coupling between the methods, but it's how selectiondag
209 // currently works.
210 def t_addrmode_rrs1 : MemOperand,
211 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
212 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
213 let PrintMethod = "printThumbAddrModeRROperand";
214 let DecoderMethod = "DecodeThumbAddrModeRR";
215 let ParserMatchClass = t_addrmode_rr_asm_operand;
216 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
217 }
218 def t_addrmode_rrs2 : MemOperand,
219 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
220 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
221 let DecoderMethod = "DecodeThumbAddrModeRR";
222 let PrintMethod = "printThumbAddrModeRROperand";
223 let ParserMatchClass = t_addrmode_rr_asm_operand;
224 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
225 }
226 def t_addrmode_rrs4 : MemOperand,
227 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
228 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
229 let DecoderMethod = "DecodeThumbAddrModeRR";
230 let PrintMethod = "printThumbAddrModeRROperand";
231 let ParserMatchClass = t_addrmode_rr_asm_operand;
232 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
233 }
235 // t_addrmode_is4 := reg + imm5 * 4
236 //
237 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
238 def t_addrmode_is4 : MemOperand,
239 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
240 let EncoderMethod = "getAddrModeISOpValue";
241 let DecoderMethod = "DecodeThumbAddrModeIS";
242 let PrintMethod = "printThumbAddrModeImm5S4Operand";
243 let ParserMatchClass = t_addrmode_is4_asm_operand;
244 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
245 }
247 // t_addrmode_is2 := reg + imm5 * 2
248 //
249 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
250 def t_addrmode_is2 : MemOperand,
251 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
252 let EncoderMethod = "getAddrModeISOpValue";
253 let DecoderMethod = "DecodeThumbAddrModeIS";
254 let PrintMethod = "printThumbAddrModeImm5S2Operand";
255 let ParserMatchClass = t_addrmode_is2_asm_operand;
256 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
257 }
259 // t_addrmode_is1 := reg + imm5
260 //
261 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
262 def t_addrmode_is1 : MemOperand,
263 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
264 let EncoderMethod = "getAddrModeISOpValue";
265 let DecoderMethod = "DecodeThumbAddrModeIS";
266 let PrintMethod = "printThumbAddrModeImm5S1Operand";
267 let ParserMatchClass = t_addrmode_is1_asm_operand;
268 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
269 }
271 // t_addrmode_sp := sp + imm8 * 4
272 //
273 // FIXME: This really shouldn't have an explicit SP operand at all. It should
274 // be implicit, just like in the instruction encoding itself.
275 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
276 def t_addrmode_sp : MemOperand,
277 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
278 let EncoderMethod = "getAddrModeThumbSPOpValue";
279 let DecoderMethod = "DecodeThumbAddrModeSP";
280 let PrintMethod = "printThumbAddrModeSPOperand";
281 let ParserMatchClass = t_addrmode_sp_asm_operand;
282 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
283 }
285 // Inspects parent to determine whether an or instruction can be implemented as
286 // an add (i.e. whether we know overflow won't occur in the add).
287 def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr", [],
288 [SDNPWantParent]>;
290 // Pattern to exclude immediates from matching
291 def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;
293 //===----------------------------------------------------------------------===//
294 // Miscellaneous Instructions.
295 //
297 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
298 // from removing one half of the matched pairs. That breaks PEI, which assumes
299 // these will always be in pairs, and asserts if it finds otherwise. Better way?
300 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
301 def tADJCALLSTACKUP :
302 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
303 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
304 Requires<[IsThumb, IsThumb1Only]>;
306 def tADJCALLSTACKDOWN :
307 PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2), NoItinerary,
308 [(ARMcallseq_start imm:$amt, imm:$amt2)]>,
309 Requires<[IsThumb, IsThumb1Only]>;
310 }
312 class T1SystemEncoding<bits<8> opc>
313 : T1Encoding<0b101111> {
314 let Inst{9-8} = 0b11;
315 let Inst{7-0} = opc;
316 }
318 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
319 [(int_arm_hint imm0_15:$imm)]>,
320 T1SystemEncoding<0x00>,
321 Requires<[IsThumb, HasV6M]> {
322 bits<4> imm;
323 let Inst{7-4} = imm;
324 }
326 // Note: When EmitPriority == 1, the alias will be used for printing
327 class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> {
328 let Predicates = [IsThumb, HasV6M];
329 }
331 def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110
332 def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410
333 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408
334 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409
335 def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157
336 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> {
337 let Predicates = [IsThumb2, HasV8];
338 }
340 // The imm operand $val can be used by a debugger to store more information
341 // about the breakpoint.
342 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
343 []>,
344 T1Encoding<0b101111> {
345 let Inst{9-8} = 0b10;
346 // A8.6.22
347 bits<8> val;
348 let Inst{7-0} = val;
349 }
350 // default immediate for breakpoint mnemonic
351 def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>;
353 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
354 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
355 let Inst{9-6} = 0b1010;
356 bits<6> val;
357 let Inst{5-0} = val;
358 }
360 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
361 []>, T1Encoding<0b101101>, Requires<[IsThumb, IsNotMClass]>, Deprecated<HasV8Ops> {
362 bits<1> end;
363 // A8.6.156
364 let Inst{9-5} = 0b10010;
365 let Inst{4} = 1;
366 let Inst{3} = end;
367 let Inst{2-0} = 0b000;
368 }
370 // Change Processor State is a system instruction -- for disassembly only.
371 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
372 NoItinerary, "cps$imod $iflags", []>,
373 T1Misc<0b0110011> {
374 // A8.6.38 & B6.1.1
375 bit imod;
376 bits<3> iflags;
378 let Inst{4} = imod;
379 let Inst{3} = 0;
380 let Inst{2-0} = iflags;
381 let DecoderMethod = "DecodeThumbCPS";
382 }
384 // For both thumb1 and thumb2.
385 let isNotDuplicable = 1, isCodeGenOnly = 1 in
386 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
387 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
388 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
389 // A8.6.6
390 bits<3> dst;
391 let Inst{6-3} = 0b1111; // Rm = pc
392 let Inst{2-0} = dst;
393 }
395 // ADD <Rd>, sp, #<imm8>
396 // FIXME: This should not be marked as having side effects, and it should be
397 // rematerializable. Clearing the side effect bit causes miscompilations,
398 // probably because the instruction can be moved around.
399 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
400 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
401 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
402 // A6.2 & A8.6.8
403 bits<3> dst;
404 bits<8> imm;
405 let Inst{10-8} = dst;
406 let Inst{7-0} = imm;
407 let DecoderMethod = "DecodeThumbAddSpecialReg";
408 }
410 // Thumb1 frame lowering is rather fragile, we hope to be able to use
411 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
412 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),
413 NoItinerary, []>,
414 Requires<[IsThumb, IsThumb1Only]> {
415 let Defs = [CPSR];
416 }
418 // ADD sp, sp, #<imm7>
419 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
420 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
421 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
422 // A6.2.5 & A8.6.8
423 bits<7> imm;
424 let Inst{6-0} = imm;
425 let DecoderMethod = "DecodeThumbAddSPImm";
426 }
428 // SUB sp, sp, #<imm7>
429 // FIXME: The encoding and the ASM string don't match up.
430 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
431 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
432 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
433 // A6.2.5 & A8.6.214
434 bits<7> imm;
435 let Inst{6-0} = imm;
436 let DecoderMethod = "DecodeThumbAddSPImm";
437 }
439 def : tInstSubst<"add${p} sp, $imm",
440 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
441 def : tInstSubst<"add${p} sp, sp, $imm",
442 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
444 // Can optionally specify SP as a three operand instruction.
445 def : tInstAlias<"add${p} sp, sp, $imm",
446 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
447 def : tInstAlias<"sub${p} sp, sp, $imm",
448 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
450 // ADD <Rm>, sp
451 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
452 "add", "\t$Rdn, $sp, $Rn", []>,
453 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
454 // A8.6.9 Encoding T1
455 bits<4> Rdn;
456 let Inst{7} = Rdn{3};
457 let Inst{6-3} = 0b1101;
458 let Inst{2-0} = Rdn{2-0};
459 let DecoderMethod = "DecodeThumbAddSPReg";
460 }
462 // ADD sp, <Rm>
463 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
464 "add", "\t$Rdn, $Rm", []>,
465 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
466 // A8.6.9 Encoding T2
467 bits<4> Rm;
468 let Inst{7} = 1;
469 let Inst{6-3} = Rm;
470 let Inst{2-0} = 0b101;
471 let DecoderMethod = "DecodeThumbAddSPReg";
472 }
474 //===----------------------------------------------------------------------===//
475 // Control Flow Instructions.
476 //
478 // Indirect branches
479 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
480 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
481 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
482 // A6.2.3 & A8.6.25
483 bits<4> Rm;
484 let Inst{6-3} = Rm;
485 let Inst{2-0} = 0b000;
486 let Unpredictable{2-0} = 0b111;
487 }
488 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
489 Requires<[IsThumb, Has8MSecExt]>,
490 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
491 bits<4> Rm;
492 let Inst{6-3} = Rm;
493 let Inst{2-0} = 0b100;
494 let Unpredictable{1-0} = 0b11;
495 }
496 }
498 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
499 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
500 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
502 // Alternative return instruction used by vararg functions.
503 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
504 2, IIC_Br, [],
505 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
506 }
508 // All calls clobber the non-callee saved registers. SP is marked as a use to
509 // prevent stack-pointer assignments that appear immediately before calls from
510 // potentially appearing dead.
511 let isCall = 1,
512 Defs = [LR], Uses = [SP] in {
513 // Also used for Thumb2
514 def tBL : TIx2<0b11110, 0b11, 1,
515 (outs), (ins pred:$p, thumb_bl_target:$func), IIC_Br,
516 "bl${p}\t$func",
517 [(ARMcall tglobaladdr:$func)]>,
518 Requires<[IsThumb]>, Sched<[WriteBrL]> {
519 bits<24> func;
520 let Inst{26} = func{23};
521 let Inst{25-16} = func{20-11};
522 let Inst{13} = func{22};
523 let Inst{11} = func{21};
524 let Inst{10-0} = func{10-0};
525 }
527 // ARMv5T and above, also used for Thumb2
528 def tBLXi : TIx2<0b11110, 0b11, 0,
529 (outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br,
530 "blx${p}\t$func", []>,
531 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
532 bits<24> func;
533 let Inst{26} = func{23};
534 let Inst{25-16} = func{20-11};
535 let Inst{13} = func{22};
536 let Inst{11} = func{21};
537 let Inst{10-1} = func{10-1};
538 let Inst{0} = 0; // func{0} is assumed zero
539 }
541 // Also used for Thumb2
542 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
543 "blx${p}\t$func",
544 [(ARMcall GPR:$func)]>,
545 Requires<[IsThumb, HasV5T]>,
546 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
547 bits<4> func;
548 let Inst{6-3} = func;
549 let Inst{2-0} = 0b000;
550 }
552 // ARMv8-M Security Extensions
553 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br,
554 "blxns${p}\t$func", []>,
555 Requires<[IsThumb, Has8MSecExt]>,
556 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
557 bits<4> func;
558 let Inst{6-3} = func;
559 let Inst{2-0} = 0b100;
560 let Unpredictable{1-0} = 0b11;
561 }
563 // ARMv4T
564 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
565 4, IIC_Br,
566 [(ARMcall_nolink tGPR:$func)]>,
567 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
568 }
570 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
571 let isPredicable = 1 in
572 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
573 "b", "\t$target", [(br bb:$target)]>,
574 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
575 bits<11> target;
576 let Inst{10-0} = target;
577 let AsmMatchConverter = "cvtThumbBranches";
578 }
580 // Far jump
581 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
582 // the clobber of LR.
583 let Defs = [LR] in
584 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p),
585 4, IIC_Br, [],
586 (tBL pred:$p, thumb_bl_target:$target)>,
587 Sched<[WriteBrTbl]>;
589 def tBR_JTr : tPseudoInst<(outs),
590 (ins tGPR:$target, i32imm:$jt),
591 0, IIC_Br,
592 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>,
593 Sched<[WriteBrTbl]> {
594 let Size = 2;
595 let isNotDuplicable = 1;
596 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
597 }
598 }
600 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
601 // a two-value operand where a dag node expects two operands. :(
602 let isBranch = 1, isTerminator = 1 in
603 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br,
604 "b${p}\t$target",
605 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
606 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
607 bits<4> p;
608 bits<8> target;
609 let Inst{11-8} = p;
610 let Inst{7-0} = target;
611 let AsmMatchConverter = "cvtThumbBranches";
612 }
615 // Tail calls
616 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
617 // IOS versions.
618 let Uses = [SP] in {
619 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
620 4, IIC_Br, [],
621 (tBX GPR:$dst, (ops 14, zero_reg))>,
622 Requires<[IsThumb]>, Sched<[WriteBr]>;
623 }
624 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls
625 // on MachO), so it's in ARMInstrThumb2.td.
626 // Non-MachO version:
627 let Uses = [SP] in {
628 def tTAILJMPdND : tPseudoExpand<(outs),
629 (ins t_brtarget:$dst, pred:$p),
630 4, IIC_Br, [],
631 (tB t_brtarget:$dst, pred:$p)>,
632 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
633 }
634 }
637 // A8.6.218 Supervisor Call (Software Interrupt)
638 // A8.6.16 B: Encoding T1
639 // If Inst{11-8} == 0b1111 then SEE SVC
640 let isCall = 1, Uses = [SP] in
641 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
642 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
643 bits<8> imm;
644 let Inst{15-12} = 0b1101;
645 let Inst{11-8} = 0b1111;
646 let Inst{7-0} = imm;
647 }
649 // The assembler uses 0xDEFE for a trap instruction.
650 let isBarrier = 1, isTerminator = 1 in
651 def tTRAP : TI<(outs), (ins), IIC_Br,
652 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
653 let Inst = 0xdefe;
654 }
656 //===----------------------------------------------------------------------===//
657 // Load Store Instructions.
658 //
660 // PC-relative loads need to be matched first as constant pool accesses need to
661 // always be PC-relative. We do this using AddedComplexity, as the pattern is
662 // simpler than the patterns of the other load instructions.
663 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in
664 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
665 "ldr", "\t$Rt, $addr",
666 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
667 T1Encoding<{0,1,0,0,1,?}>, Sched<[WriteLd]> {
668 // A6.2 & A8.6.59
669 bits<3> Rt;
670 bits<8> addr;
671 let Inst{10-8} = Rt;
672 let Inst{7-0} = addr;
673 }
675 // SP-relative loads should be matched before standard immediate-offset loads as
676 // it means we avoid having to move SP to another register.
677 let canFoldAsLoad = 1 in
678 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
679 "ldr", "\t$Rt, $addr",
680 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
681 T1LdStSP<{1,?,?}>, Sched<[WriteLd]> {
682 bits<3> Rt;
683 bits<8> addr;
684 let Inst{10-8} = Rt;
685 let Inst{7-0} = addr;
686 }
688 // Loads: reg/reg and reg/imm5
689 let canFoldAsLoad = 1, isReMaterializable = 1 in
690 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
691 Operand AddrMode_r, Operand AddrMode_i,
692 AddrMode am, InstrItinClass itin_r,
693 InstrItinClass itin_i, string asm,
694 PatFrag opnode> {
695 // Immediate-offset loads should be matched before register-offset loads as
696 // when the offset is a constant it's simpler to first check if it fits in the
697 // immediate offset field then fall back to register-offset if it doesn't.
698 def i : // reg/imm5
699 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
700 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
701 am, itin_i, asm, "\t$Rt, $addr",
702 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
703 // Register-offset loads are matched last.
704 def r : // reg/reg
705 T1pILdStEncode<reg_opc,
706 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
707 am, itin_r, asm, "\t$Rt, $addr",
708 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
709 }
710 // Stores: reg/reg and reg/imm5
711 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
712 Operand AddrMode_r, Operand AddrMode_i,
713 AddrMode am, InstrItinClass itin_r,
714 InstrItinClass itin_i, string asm,
715 PatFrag opnode> {
716 def i : // reg/imm5
717 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
718 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
719 am, itin_i, asm, "\t$Rt, $addr",
720 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
721 def r : // reg/reg
722 T1pILdStEncode<reg_opc,
723 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
724 am, itin_r, asm, "\t$Rt, $addr",
725 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
726 }
728 // A8.6.57 & A8.6.60
729 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr,
730 t_addrmode_is4, AddrModeT1_4,
731 IIC_iLoad_r, IIC_iLoad_i, "ldr",
732 load>, Sched<[WriteLd]>;
734 // A8.6.64 & A8.6.61
735 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr,
736 t_addrmode_is1, AddrModeT1_1,
737 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
738 zextloadi8>, Sched<[WriteLd]>;
740 // A8.6.76 & A8.6.73
741 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr,
742 t_addrmode_is2, AddrModeT1_2,
743 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
744 zextloadi16>, Sched<[WriteLd]>;
746 let AddedComplexity = 10 in
747 def tLDRSB : // A8.6.80
748 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr_sext:$addr),
749 AddrModeT1_1, IIC_iLoad_bh_r,
750 "ldrsb", "\t$Rt, $addr",
751 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;
753 let AddedComplexity = 10 in
754 def tLDRSH : // A8.6.84
755 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr_sext:$addr),
756 AddrModeT1_2, IIC_iLoad_bh_r,
757 "ldrsh", "\t$Rt, $addr",
758 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;
761 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
762 "str", "\t$Rt, $addr",
763 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
764 T1LdStSP<{0,?,?}>, Sched<[WriteST]> {
765 bits<3> Rt;
766 bits<8> addr;
767 let Inst{10-8} = Rt;
768 let Inst{7-0} = addr;
769 }
771 // A8.6.194 & A8.6.192
772 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr,
773 t_addrmode_is4, AddrModeT1_4,
774 IIC_iStore_r, IIC_iStore_i, "str",
775 store>, Sched<[WriteST]>;
777 // A8.6.197 & A8.6.195
778 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr,
779 t_addrmode_is1, AddrModeT1_1,
780 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
781 truncstorei8>, Sched<[WriteST]>;
783 // A8.6.207 & A8.6.205
784 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr,
785 t_addrmode_is2, AddrModeT1_2,
786 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
787 truncstorei16>, Sched<[WriteST]>;
790 //===----------------------------------------------------------------------===//
791 // Load / store multiple Instructions.
792 //
794 // These require base address to be written back or one of the loaded regs.
795 let hasSideEffects = 0 in {
797 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
798 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
799 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
800 bits<3> Rn;
801 bits<8> regs;
802 let Inst{10-8} = Rn;
803 let Inst{7-0} = regs;
804 }
806 // Writeback version is just a pseudo, as there's no encoding difference.
807 // Writeback happens iff the base register is not in the destination register
808 // list.
809 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
810 def tLDMIA_UPD :
811 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
812 "$Rn = $wb", IIC_iLoad_mu>,
813 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
814 let Size = 2;
815 let OutOperandList = (outs tGPR:$wb);
816 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
817 let Pattern = [];
818 let isCodeGenOnly = 1;
819 let isPseudo = 1;
820 list<Predicate> Predicates = [IsThumb];
821 }
823 // There is no non-writeback version of STM for Thumb.
824 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
825 def tSTMIA_UPD : Thumb1I<(outs tGPR:$wb),
826 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
827 AddrModeNone, 2, IIC_iStore_mu,
828 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
829 T1Encoding<{1,1,0,0,0,?}> {
830 bits<3> Rn;
831 bits<8> regs;
832 let Inst{10-8} = Rn;
833 let Inst{7-0} = regs;
834 }
836 } // hasSideEffects
838 def : InstAlias<"ldm${p} $Rn!, $regs",
839 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
840 Requires<[IsThumb, IsThumb1Only]>;
842 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1,
843 variadicOpsAreDefs = 1 in
844 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
845 IIC_iPop,
846 "pop${p}\t$regs", []>,
847 T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> {
848 bits<16> regs;
849 let Inst{8} = regs{15};
850 let Inst{7-0} = regs{7-0};
851 }
853 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
854 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
855 IIC_iStore_m,
856 "push${p}\t$regs", []>,
857 T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> {
858 bits<16> regs;
859 let Inst{8} = regs{14};
860 let Inst{7-0} = regs{7-0};
861 }
863 //===----------------------------------------------------------------------===//
864 // Arithmetic Instructions.
865 //
867 // Helper classes for encoding T1pI patterns:
868 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
869 string opc, string asm, list<dag> pattern>
870 : T1pI<oops, iops, itin, opc, asm, pattern>,
871 T1DataProcessing<opA> {
872 bits<3> Rm;
873 bits<3> Rn;
874 let Inst{5-3} = Rm;
875 let Inst{2-0} = Rn;
876 }
877 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
878 string opc, string asm, list<dag> pattern>
879 : T1pI<oops, iops, itin, opc, asm, pattern>,
880 T1Misc<opA> {
881 bits<3> Rm;
882 bits<3> Rd;
883 let Inst{5-3} = Rm;
884 let Inst{2-0} = Rd;
885 }
887 // Helper classes for encoding T1sI patterns:
888 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
889 string opc, string asm, list<dag> pattern>
890 : T1sI<oops, iops, itin, opc, asm, pattern>,
891 T1DataProcessing<opA> {
892 bits<3> Rd;
893 bits<3> Rn;
894 let Inst{5-3} = Rn;
895 let Inst{2-0} = Rd;
896 }
897 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
898 string opc, string asm, list<dag> pattern>
899 : T1sI<oops, iops, itin, opc, asm, pattern>,
900 T1General<opA> {
901 bits<3> Rm;
902 bits<3> Rn;
903 bits<3> Rd;
904 let Inst{8-6} = Rm;
905 let Inst{5-3} = Rn;
906 let Inst{2-0} = Rd;
907 }
908 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
909 string opc, string asm, list<dag> pattern>
910 : T1sI<oops, iops, itin, opc, asm, pattern>,
911 T1General<opA> {
912 bits<3> Rd;
913 bits<3> Rm;
914 let Inst{5-3} = Rm;
915 let Inst{2-0} = Rd;
916 }
918 // Helper classes for encoding T1sIt patterns:
919 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
920 string opc, string asm, list<dag> pattern>
921 : T1sIt<oops, iops, itin, opc, asm, pattern>,
922 T1DataProcessing<opA> {
923 bits<3> Rdn;
924 bits<3> Rm;
925 let Inst{5-3} = Rm;
926 let Inst{2-0} = Rdn;
927 }
928 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
929 string opc, string asm, list<dag> pattern>
930 : T1sIt<oops, iops, itin, opc, asm, pattern>,
931 T1General<opA> {
932 bits<3> Rdn;
933 bits<8> imm8;
934 let Inst{10-8} = Rdn;
935 let Inst{7-0} = imm8;
936 }
938 let isAdd = 1 in {
939 // Add with carry register
940 let isCommutable = 1, Uses = [CPSR] in
941 def tADC : // A8.6.2
942 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
943 "adc", "\t$Rdn, $Rm",
944 []>, Sched<[WriteALU]>;
946 // Add immediate
947 def tADDi3 : // A8.6.4 T1
948 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
949 IIC_iALUi,
950 "add", "\t$Rd, $Rm, $imm3",
951 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
952 Sched<[WriteALU]> {
953 bits<3> imm3;
954 let Inst{8-6} = imm3;
955 }
957 def tADDi8 : // A8.6.4 T2
958 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
959 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
960 "add", "\t$Rdn, $imm8",
961 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
962 Sched<[WriteALU]>;
964 // Add register
965 let isCommutable = 1 in
966 def tADDrr : // A8.6.6 T1
967 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
968 IIC_iALUr,
969 "add", "\t$Rd, $Rn, $Rm",
970 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
972 /// Similar to the above except these set the 's' bit so the
973 /// instruction modifies the CPSR register.
974 ///
975 /// These opcodes will be converted to the real non-S opcodes by
976 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
977 let hasPostISelHook = 1, Defs = [CPSR] in {
978 let isCommutable = 1, Uses = [CPSR] in
979 def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
980 2, IIC_iALUr,
981 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
982 CPSR))]>,
983 Requires<[IsThumb1Only]>,
984 Sched<[WriteALU]>;
986 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
987 2, IIC_iALUi,
988 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
989 imm0_7:$imm3))]>,
990 Requires<[IsThumb1Only]>,
991 Sched<[WriteALU]>;
993 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
994 2, IIC_iALUi,
995 [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn,
996 imm8_255:$imm8))]>,
997 Requires<[IsThumb1Only]>,
998 Sched<[WriteALU]>;
1000 let isCommutable = 1 in
1001 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1002 2, IIC_iALUr,
1003 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,
1004 tGPR:$Rm))]>,
1005 Requires<[IsThumb1Only]>,
1006 Sched<[WriteALU]>;
1007 }
1009 let hasSideEffects = 0 in
1010 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
1011 "add", "\t$Rdn, $Rm", []>,
1012 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
1013 // A8.6.6 T2
1014 bits<4> Rdn;
1015 bits<4> Rm;
1016 let Inst{7} = Rdn{3};
1017 let Inst{6-3} = Rm;
1018 let Inst{2-0} = Rdn{2-0};
1019 }
1020 }
1022 // Thumb has more flexible short encodings for ADD than ORR, so use those where
1023 // possible.
1024 def : T1Pat<(or AddLikeOrOp:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>;
1026 def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;
1028 def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
1031 def : tInstAlias <"add${s}${p} $Rdn, $Rm",
1032 (tADDrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
1034 def : tInstSubst<"sub${s}${p} $rd, $rn, $imm",
1035 (tADDi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;
1036 def : tInstSubst<"sub${s}${p} $rdn, $imm",
1037 (tADDi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>;
1040 // AND register
1041 let isCommutable = 1 in
1042 def tAND : // A8.6.12
1043 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1044 IIC_iBITr,
1045 "and", "\t$Rdn, $Rm",
1046 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1048 // ASR immediate
1049 def tASRri : // A8.6.14
1050 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1051 IIC_iMOVsi,
1052 "asr", "\t$Rd, $Rm, $imm5",
1053 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1054 Sched<[WriteALU]> {
1055 bits<5> imm5;
1056 let Inst{10-6} = imm5;
1057 }
1059 // ASR register
1060 def tASRrr : // A8.6.15
1061 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1062 IIC_iMOVsr,
1063 "asr", "\t$Rdn, $Rm",
1064 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1066 // BIC register
1067 def tBIC : // A8.6.20
1068 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1069 IIC_iBITr,
1070 "bic", "\t$Rdn, $Rm",
1071 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
1072 Sched<[WriteALU]>;
1074 // CMN register
1075 let isCompare = 1, Defs = [CPSR] in {
1076 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
1077 // Compare-to-zero still works out, just not the relationals
1078 //def tCMN : // A8.6.33
1079 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
1080 // IIC_iCMPr,
1081 // "cmn", "\t$lhs, $rhs",
1082 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
1084 def tCMNz : // A8.6.33
1085 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1086 IIC_iCMPr,
1087 "cmn", "\t$Rn, $Rm",
1088 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1090 } // isCompare = 1, Defs = [CPSR]
1092 // CMP immediate
1093 let isCompare = 1, Defs = [CPSR] in {
1094 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
1095 "cmp", "\t$Rn, $imm8",
1096 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
1097 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
1098 // A8.6.35
1099 bits<3> Rn;
1100 bits<8> imm8;
1101 let Inst{10-8} = Rn;
1102 let Inst{7-0} = imm8;
1103 }
1105 // CMP register
1106 def tCMPr : // A8.6.36 T1
1107 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1108 IIC_iCMPr,
1109 "cmp", "\t$Rn, $Rm",
1110 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
1112 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1113 "cmp", "\t$Rn, $Rm", []>,
1114 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
1115 // A8.6.36 T2
1116 bits<4> Rm;
1117 bits<4> Rn;
1118 let Inst{7} = Rn{3};
1119 let Inst{6-3} = Rm;
1120 let Inst{2-0} = Rn{2-0};
1121 }
1122 } // isCompare = 1, Defs = [CPSR]
1125 // XOR register
1126 let isCommutable = 1 in
1127 def tEOR : // A8.6.45
1128 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1129 IIC_iBITr,
1130 "eor", "\t$Rdn, $Rm",
1131 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1133 // LSL immediate
1134 def tLSLri : // A8.6.88
1135 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1136 IIC_iMOVsi,
1137 "lsl", "\t$Rd, $Rm, $imm5",
1138 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1139 Sched<[WriteALU]> {
1140 bits<5> imm5;
1141 let Inst{10-6} = imm5;
1142 }
1144 // LSL register
1145 def tLSLrr : // A8.6.89
1146 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1147 IIC_iMOVsr,
1148 "lsl", "\t$Rdn, $Rm",
1149 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1151 // LSR immediate
1152 def tLSRri : // A8.6.90
1153 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1154 IIC_iMOVsi,
1155 "lsr", "\t$Rd, $Rm, $imm5",
1156 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1157 Sched<[WriteALU]> {
1158 bits<5> imm5;
1159 let Inst{10-6} = imm5;
1160 }
1162 // LSR register
1163 def tLSRrr : // A8.6.91
1164 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1165 IIC_iMOVsr,
1166 "lsr", "\t$Rdn, $Rm",
1167 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1169 // Move register
1170 let isMoveImm = 1 in
1171 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1172 "mov", "\t$Rd, $imm8",
1173 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1174 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1175 // A8.6.96
1176 bits<3> Rd;
1177 bits<8> imm8;
1178 let Inst{10-8} = Rd;
1179 let Inst{7-0} = imm8;
1180 }
1181 // Because we have an explicit tMOVSr below, we need an alias to handle
1182 // the immediate "movs" form here. Blech.
1183 def : tInstAlias <"movs $Rdn, $imm",
1184 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1186 // A7-73: MOV(2) - mov setting flag.
1188 let hasSideEffects = 0, isMoveReg = 1 in {
1189 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1190 2, IIC_iMOVr,
1191 "mov", "\t$Rd, $Rm", "", []>,
1192 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1193 // A8.6.97
1194 bits<4> Rd;
1195 bits<4> Rm;
1196 let Inst{7} = Rd{3};
1197 let Inst{6-3} = Rm;
1198 let Inst{2-0} = Rd{2-0};
1199 }
1200 let Defs = [CPSR] in
1201 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1202 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1203 // A8.6.97
1204 bits<3> Rd;
1205 bits<3> Rm;
1206 let Inst{15-6} = 0b0000000000;
1207 let Inst{5-3} = Rm;
1208 let Inst{2-0} = Rd;
1209 }
1210 } // hasSideEffects
1212 // Multiply register
1213 let isCommutable = 1 in
1214 def tMUL : // A8.6.105 T1
1215 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1216 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1217 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1218 T1DataProcessing<0b1101>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
1219 bits<3> Rd;
1220 bits<3> Rn;
1221 let Inst{5-3} = Rn;
1222 let Inst{2-0} = Rd;
1223 let AsmMatchConverter = "cvtThumbMultiply";
1224 }
1226 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1227 pred:$p)>;
1229 // Move inverse register
1230 def tMVN : // A8.6.107
1231 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1232 "mvn", "\t$Rd, $Rn",
1233 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1235 // Bitwise or register
1236 let isCommutable = 1 in
1237 def tORR : // A8.6.114
1238 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1239 IIC_iBITr,
1240 "orr", "\t$Rdn, $Rm",
1241 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1243 // Swaps
1244 def tREV : // A8.6.134
1245 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1246 IIC_iUNAr,
1247 "rev", "\t$Rd, $Rm",
1248 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1249 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1251 def tREV16 : // A8.6.135
1252 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1253 IIC_iUNAr,
1254 "rev16", "\t$Rd, $Rm",
1255 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1256 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1258 def tREVSH : // A8.6.136
1259 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1260 IIC_iUNAr,
1261 "revsh", "\t$Rd, $Rm",
1262 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1263 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1265 // Rotate right register
1266 def tROR : // A8.6.139
1267 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1268 IIC_iMOVsr,
1269 "ror", "\t$Rdn, $Rm",
1270 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1271 Sched<[WriteALU]>;
1273 // Negate register
1274 def tRSB : // A8.6.141
1275 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1276 IIC_iALUi,
1277 "rsb", "\t$Rd, $Rn, #0",
1278 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1280 // Subtract with carry register
1281 let Uses = [CPSR] in
1282 def tSBC : // A8.6.151
1283 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1284 IIC_iALUr,
1285 "sbc", "\t$Rdn, $Rm",
1286 []>,
1287 Sched<[WriteALU]>;
1289 // Subtract immediate
1290 def tSUBi3 : // A8.6.210 T1
1291 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1292 IIC_iALUi,
1293 "sub", "\t$Rd, $Rm, $imm3",
1294 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1295 Sched<[WriteALU]> {
1296 bits<3> imm3;
1297 let Inst{8-6} = imm3;
1298 }
1300 def tSUBi8 : // A8.6.210 T2
1301 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1302 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1303 "sub", "\t$Rdn, $imm8",
1304 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1305 Sched<[WriteALU]>;
1307 def : tInstSubst<"add${s}${p} $rd, $rn, $imm",
1308 (tSUBi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;
1311 def : tInstSubst<"add${s}${p} $rdn, $imm",
1312 (tSUBi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>;
1315 // Subtract register
1316 def tSUBrr : // A8.6.212
1317 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1318 IIC_iALUr,
1319 "sub", "\t$Rd, $Rn, $Rm",
1320 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1321 Sched<[WriteALU]>;
1323 def : tInstAlias <"sub${s}${p} $Rdn, $Rm",
1324 (tSUBrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
1326 /// Similar to the above except these set the 's' bit so the
1327 /// instruction modifies the CPSR register.
1328 ///
1329 /// These opcodes will be converted to the real non-S opcodes by
1330 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1331 let hasPostISelHook = 1, Defs = [CPSR] in {
1332 let Uses = [CPSR] in
1333 def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1334 2, IIC_iALUr,
1335 [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm,
1336 CPSR))]>,
1337 Requires<[IsThumb1Only]>,
1338 Sched<[WriteALU]>;
1340 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1341 2, IIC_iALUi,
1342 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm,
1343 imm0_7:$imm3))]>,
1344 Requires<[IsThumb1Only]>,
1345 Sched<[WriteALU]>;
1347 def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1348 2, IIC_iALUi,
1349 [(set tGPR:$Rdn, CPSR, (ARMsubc tGPR:$Rn,
1350 imm8_255:$imm8))]>,
1351 Requires<[IsThumb1Only]>,
1352 Sched<[WriteALU]>;
1354 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1355 2, IIC_iALUr,
1356 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,
1357 tGPR:$Rm))]>,
1358 Requires<[IsThumb1Only]>,
1359 Sched<[WriteALU]>;
1361 def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),
1362 2, IIC_iALUr,
1363 [(set tGPR:$Rd, CPSR, (ARMsubc 0, tGPR:$Rn))]>,
1364 Requires<[IsThumb1Only]>,
1365 Sched<[WriteALU]>;
1367 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5),
1368 2, IIC_iALUr,
1369 [(set tGPR:$Rd, CPSR, (ARMlsls tGPR:$Rn, imm0_31:$imm5))]>,
1370 Requires<[IsThumb1Only]>,
1371 Sched<[WriteALU]>;
1372 }
1375 def : T1Pat<(ARMsubs tGPR:$Rn, tGPR:$Rm), (tSUBSrr $Rn, $Rm)>;
1376 def : T1Pat<(ARMsubs tGPR:$Rn, imm0_7:$imm3), (tSUBSi3 $Rn, imm0_7:$imm3)>;
1377 def : T1Pat<(ARMsubs tGPR:$Rn, imm0_255:$imm8), (tSUBSi8 $Rn, imm0_255:$imm8)>;
1380 // Sign-extend byte
1381 def tSXTB : // A8.6.222
1382 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1383 IIC_iUNAr,
1384 "sxtb", "\t$Rd, $Rm",
1385 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1386 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1387 Sched<[WriteALU]>;
1389 // Sign-extend short
1390 def tSXTH : // A8.6.224
1391 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1392 IIC_iUNAr,
1393 "sxth", "\t$Rd, $Rm",
1394 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1395 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1396 Sched<[WriteALU]>;
1398 // Test
1399 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1400 def tTST : // A8.6.230
1401 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1402 "tst", "\t$Rn, $Rm",
1403 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1404 Sched<[WriteALU]>;
1406 // A8.8.247 UDF - Undefined (Encoding T1)
1407 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
1408 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 {
1409 bits<8> imm8;
1410 let Inst{15-12} = 0b1101;
1411 let Inst{11-8} = 0b1110;
1412 let Inst{7-0} = imm8;
1413 }
1415 def : Pat<(debugtrap), (tBKPT 0)>, Requires<[IsThumb, HasV5T]>;
1416 def : Pat<(debugtrap), (tUDF 254)>, Requires<[IsThumb, NoV5T]>;
1418 def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0",
1419 [(int_arm_undefined 249)]>, Encoding16,
1420 Requires<[IsThumb, IsWindows]> {
1421 let Inst = 0xdef9;
1422 let isTerminator = 1;
1423 }
1425 // Zero-extend byte
1426 def tUXTB : // A8.6.262
1427 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1428 IIC_iUNAr,
1429 "uxtb", "\t$Rd, $Rm",
1430 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1431 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1432 Sched<[WriteALU]>;
1434 // Zero-extend short
1435 def tUXTH : // A8.6.264
1436 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1437 IIC_iUNAr,
1438 "uxth", "\t$Rd, $Rm",
1439 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1440 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1442 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1443 // Expanded after instruction selection into a branch sequence.
1444 let usesCustomInserter = 1 in // Expanded after instruction selection.
1445 def tMOVCCr_pseudo :
1446 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p),
1447 NoItinerary,
1448 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>;
1450 // tLEApcrel - Load a pc-relative address into a register without offending the
1451 // assembler.
1453 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1454 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1455 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1456 bits<3> Rd;
1457 bits<8> addr;
1458 let Inst{10-8} = Rd;
1459 let Inst{7-0} = addr;
1460 let DecoderMethod = "DecodeThumbAddSpecialReg";
1461 }
1463 let hasSideEffects = 0, isReMaterializable = 1 in
1464 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1465 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1467 let hasSideEffects = 1 in
1468 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1469 (ins i32imm:$label, pred:$p),
1470 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1472 // Thumb-1 doesn't have the TBB or TBH instructions, but we can synthesize them
1473 // and make use of the same compressed jump table format as Thumb-2.
1474 let Size = 2, isBranch = 1, isTerminator = 1, isBarrier = 1,
1475 isIndirectBranch = 1, isNotDuplicable = 1 in {
1476 def tTBB_JT : tPseudoInst<(outs),
1477 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0,
1478 IIC_Br, []>, Sched<[WriteBr]>;
1480 def tTBH_JT : tPseudoInst<(outs),
1481 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0,
1482 IIC_Br, []>, Sched<[WriteBr]>;
1483 }
1485 //===----------------------------------------------------------------------===//
1486 // TLS Instructions
1487 //
1489 // __aeabi_read_tp preserves the registers r1-r3.
1490 // This is a pseudo inst so that we can get the encoding right,
1491 // complete with fixup for the aeabi_read_tp function.
1492 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1493 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1494 [(set R0, ARMthread_pointer)]>,
1495 Sched<[WriteBr]>;
1497 //===----------------------------------------------------------------------===//
1498 // SJLJ Exception handling intrinsics
1499 //
1501 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1502 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1503 // from some other function to get here, and we're using the stack frame for the
1504 // containing function to save/restore registers, we can't keep anything live in
1505 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1506 // tromped upon when we get here from a longjmp(). We force everything out of
1507 // registers except for our own input by listing the relevant registers in
1508 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1509 // preserve all of the callee-saved resgisters, which is exactly what we want.
1510 // $val is a scratch register for our use.
1511 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1512 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1513 usesCustomInserter = 1 in
1514 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1515 AddrModeNone, 0, NoItinerary, "","",
1516 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1518 // FIXME: Non-IOS version(s)
1519 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1520 Defs = [ R7, LR, SP ] in
1521 def tInt_eh_sjlj_longjmp : XI<(outs), (ins tGPR:$src, tGPR:$scratch),
1522 AddrModeNone, 0, IndexModeNone,
1523 Pseudo, NoItinerary, "", "",
1524 [(ARMeh_sjlj_longjmp tGPR:$src, tGPR:$scratch)]>,
1525 Requires<[IsThumb,IsNotWindows]>;
1527 // (Windows is Thumb2-only)
1528 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1529 Defs = [ R11, LR, SP ] in
1530 def tInt_WIN_eh_sjlj_longjmp
1531 : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone,
1532 Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1533 Requires<[IsThumb,IsWindows]>;
1535 //===----------------------------------------------------------------------===//
1536 // Non-Instruction Patterns
1537 //
1539 // Comparisons
1540 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1541 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1542 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1543 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1545 // Bswap 16 with load/store
1546 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
1547 (tREV16 (tLDRHi t_addrmode_is2:$addr))>;
1548 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)),
1549 (tREV16 (tLDRHr t_addrmode_rr:$addr))>;
1550 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1551 t_addrmode_is2:$addr),
1552 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;
1553 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1554 t_addrmode_rr:$addr),
1555 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>;
1557 // ConstantPool
1558 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1560 // GlobalAddress
1561 def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),
1562 IIC_iLoadiALU,
1563 [(set tGPR:$dst,
1564 (ARMWrapperPIC tglobaladdr:$addr))]>,
1565 Requires<[IsThumb, DontUseMovtInPic]>;
1567 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
1568 IIC_iLoad_i,
1569 [(set tGPR:$dst,
1570 (ARMWrapper tglobaladdr:$src))]>,
1571 Requires<[IsThumb, DontUseMovt]>;
1573 // TLS globals
1574 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
1575 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
1576 Requires<[IsThumb, DontUseMovtInPic]>;
1577 def : Pat<(ARMWrapper tglobaltlsaddr:$addr),
1578 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>,
1579 Requires<[IsThumb, DontUseMovt]>;
1582 // JumpTable
1583 def : T1Pat<(ARMWrapperJT tjumptable:$dst),
1584 (tLEApcrelJT tjumptable:$dst)>;
1586 // Direct calls
1587 def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>,
1588 Requires<[IsThumb]>;
1590 // zextload i1 -> zextload i8
1591 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1592 (tLDRBi t_addrmode_is1:$addr)>;
1593 def : T1Pat<(zextloadi1 t_addrmode_rr:$addr),
1594 (tLDRBr t_addrmode_rr:$addr)>;
1596 // extload from the stack -> word load from the stack, as it avoids having to
1597 // materialize the base in a separate register. This only works when a word
1598 // load puts the byte/halfword value in the same place in the register that the
1599 // byte/halfword load would, i.e. when little-endian.
1600 def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1601 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1602 def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1603 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1604 def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1605 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1607 // extload -> zextload
1608 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1609 def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1610 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1611 def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1612 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1613 def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>;
1615 // post-inc loads and stores
1617 // post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is
1618 // different to how ISel expects them for a post-inc load, so use a pseudo
1619 // and expand it just after ISel.
1620 let usesCustomInserter = 1, mayLoad =1,
1621 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in
1622 def tLDR_postidx: tPseudoInst<(outs tGPR:$Rt, tGPR:$Rn_wb),
1623 (ins tGPR:$Rn, pred:$p),
1624 4, IIC_iStore_ru,
1625 []>;
1627 // post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def
1628 // multiple registers) is the same in ISel as MachineInstr, so there's no need
1629 // for a pseudo.
1630 def : T1Pat<(post_store tGPR:$Rt, tGPR:$Rn, 4),
1631 (tSTMIA_UPD tGPR:$Rn, tGPR:$Rt)>;
1633 // If it's impossible to use [r,r] address mode for sextload, select to
1634 // ldr{b|h} + sxt{b|h} instead.
1635 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1636 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1637 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1638 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1639 (tSXTB (tLDRBr t_addrmode_rr:$addr))>,
1640 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1641 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1642 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1643 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1644 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1645 (tSXTH (tLDRHr t_addrmode_rr:$addr))>,
1646 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1648 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1649 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1650 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1651 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>;
1652 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1653 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1654 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1655 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>;
1657 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1658 (tLDRBi t_addrmode_is1:$src)>;
1659 def : T1Pat<(atomic_load_8 t_addrmode_rr:$src),
1660 (tLDRBr t_addrmode_rr:$src)>;
1661 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1662 (tLDRHi t_addrmode_is2:$src)>;
1663 def : T1Pat<(atomic_load_16 t_addrmode_rr:$src),
1664 (tLDRHr t_addrmode_rr:$src)>;
1665 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1666 (tLDRi t_addrmode_is4:$src)>;
1667 def : T1Pat<(atomic_load_32 t_addrmode_rr:$src),
1668 (tLDRr t_addrmode_rr:$src)>;
1669 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1670 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1671 def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val),
1672 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>;
1673 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1674 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1675 def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val),
1676 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>;
1677 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1678 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1679 def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val),
1680 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>;
1682 // Large immediate handling.
1684 // Two piece imms.
1685 def : T1Pat<(i32 thumb_immshifted:$src),
1686 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1687 (thumb_immshifted_shamt imm:$src))>;
1689 def : T1Pat<(i32 imm0_255_comp:$src),
1690 (tMVN (tMOVi8 (imm_not_XFORM imm:$src)))>;
1692 def : T1Pat<(i32 imm256_510:$src),
1693 (tADDi8 (tMOVi8 255),
1694 (thumb_imm256_510_addend imm:$src))>;
1696 // Pseudo instruction that combines ldr from constpool and add pc. This should
1697 // be expanded into two instructions late to allow if-conversion and
1698 // scheduling.
1699 let isReMaterializable = 1 in
1700 def tLDRpci_pic : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1701 NoItinerary,
1702 [(set tGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1703 imm:$cp))]>,
1704 Requires<[IsThumb, IsThumb1Only]>;
1706 // Pseudo-instruction for merged POP and return.
1707 // FIXME: remove when we have a way to marking a MI with these properties.
1708 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1709 hasExtraDefRegAllocReq = 1 in
1710 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1711 2, IIC_iPop_Br, [],
1712 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1714 // Indirect branch using "mov pc, $Rm"
1715 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1716 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1717 2, IIC_Br, [(brind GPR:$Rm)],
1718 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1719 }
1722 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1723 // encoding is available on ARMv6K, but we don't differentiate that finely.
1724 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>;
1727 // "neg" is and alias for "rsb rd, rn, #0"
1728 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1729 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1732 // Implied destination operand forms for shifts.
1733 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1734 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1735 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1736 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1737 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1738 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1740 // Pseudo instruction ldr Rt, =immediate
1741 def tLDRConstPool
1742 : tAsmPseudo<"ldr${p} $Rt, $immediate",
1743 (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;