[ARM] Split large truncating MVE stores

[llvm-complete.git] / test / CodeGen / MIR / AMDGPU / machine-function-info-register-parse-error1.mir

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :7:27: incorrect register class for field
# CHECK: scratchRSrcReg:  '$noreg'
---
name: noreg_rsrc_reg
machineFunctionInfo:
  scratchRSrcReg:  '$noreg'
body:             |
  bb.0:

    S_ENDPGM
...