| blob | 54c49f3f3ef66990919dc08120f4c812f58ea33d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV32I
4 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefix=RV64I
7 ; Basic shift support is tested as part of ALU.ll. This file ensures that
8 ; shifts which may not be supported natively are lowered properly.
10 define i64 @lshr64(i64 %a, i64 %b) nounwind {
11 ; RV32I-LABEL: lshr64:
12 ; RV32I: # %bb.0:
13 ; RV32I-NEXT: addi a3, a2, -32
14 ; RV32I-NEXT: bltz a3, .LBB0_2
15 ; RV32I-NEXT: # %bb.1:
16 ; RV32I-NEXT: srl a0, a1, a3
17 ; RV32I-NEXT: mv a1, zero
18 ; RV32I-NEXT: ret
19 ; RV32I-NEXT: .LBB0_2:
20 ; RV32I-NEXT: srl a0, a0, a2
21 ; RV32I-NEXT: addi a3, zero, 31
22 ; RV32I-NEXT: sub a3, a3, a2
23 ; RV32I-NEXT: slli a4, a1, 1
24 ; RV32I-NEXT: sll a3, a4, a3
25 ; RV32I-NEXT: or a0, a0, a3
26 ; RV32I-NEXT: srl a2, a1, a2
27 ; RV32I-NEXT: mv a1, a2
28 ; RV32I-NEXT: ret
29 ;
30 ; RV64I-LABEL: lshr64:
31 ; RV64I: # %bb.0:
32 ; RV64I-NEXT: srl a0, a0, a1
33 ; RV64I-NEXT: ret
34 %1 = lshr i64 %a, %b
35 ret i64 %1
36 }
38 define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {
39 ; RV32I-LABEL: lshr64_minsize:
40 ; RV32I: # %bb.0:
41 ; RV32I-NEXT: addi sp, sp, -16
42 ; RV32I-NEXT: sw ra, 12(sp)
43 ; RV32I-NEXT: call __lshrdi3
44 ; RV32I-NEXT: lw ra, 12(sp)
45 ; RV32I-NEXT: addi sp, sp, 16
46 ; RV32I-NEXT: ret
47 ;
48 ; RV64I-LABEL: lshr64_minsize:
49 ; RV64I: # %bb.0:
50 ; RV64I-NEXT: srl a0, a0, a1
51 ; RV64I-NEXT: ret
52 %1 = lshr i64 %a, %b
53 ret i64 %1
54 }
56 define i64 @ashr64(i64 %a, i64 %b) nounwind {
57 ; RV32I-LABEL: ashr64:
58 ; RV32I: # %bb.0:
59 ; RV32I-NEXT: addi a3, a2, -32
60 ; RV32I-NEXT: bltz a3, .LBB2_2
61 ; RV32I-NEXT: # %bb.1:
62 ; RV32I-NEXT: sra a0, a1, a3
63 ; RV32I-NEXT: srai a1, a1, 31
64 ; RV32I-NEXT: ret
65 ; RV32I-NEXT: .LBB2_2:
66 ; RV32I-NEXT: srl a0, a0, a2
67 ; RV32I-NEXT: addi a3, zero, 31
68 ; RV32I-NEXT: sub a3, a3, a2
69 ; RV32I-NEXT: slli a4, a1, 1
70 ; RV32I-NEXT: sll a3, a4, a3
71 ; RV32I-NEXT: or a0, a0, a3
72 ; RV32I-NEXT: sra a1, a1, a2
73 ; RV32I-NEXT: ret
74 ;
75 ; RV64I-LABEL: ashr64:
76 ; RV64I: # %bb.0:
77 ; RV64I-NEXT: sra a0, a0, a1
78 ; RV64I-NEXT: ret
79 %1 = ashr i64 %a, %b
80 ret i64 %1
81 }
83 define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {
84 ; RV32I-LABEL: ashr64_minsize:
85 ; RV32I: # %bb.0:
86 ; RV32I-NEXT: addi sp, sp, -16
87 ; RV32I-NEXT: sw ra, 12(sp)
88 ; RV32I-NEXT: call __ashrdi3
89 ; RV32I-NEXT: lw ra, 12(sp)
90 ; RV32I-NEXT: addi sp, sp, 16
91 ; RV32I-NEXT: ret
92 ;
93 ; RV64I-LABEL: ashr64_minsize:
94 ; RV64I: # %bb.0:
95 ; RV64I-NEXT: sra a0, a0, a1
96 ; RV64I-NEXT: ret
97 %1 = ashr i64 %a, %b
98 ret i64 %1
99 }
101 define i64 @shl64(i64 %a, i64 %b) nounwind {
102 ; RV32I-LABEL: shl64:
103 ; RV32I: # %bb.0:
104 ; RV32I-NEXT: addi a3, a2, -32
105 ; RV32I-NEXT: bltz a3, .LBB4_2
106 ; RV32I-NEXT: # %bb.1:
107 ; RV32I-NEXT: sll a1, a0, a3
108 ; RV32I-NEXT: mv a0, zero
109 ; RV32I-NEXT: ret
110 ; RV32I-NEXT: .LBB4_2:
111 ; RV32I-NEXT: sll a1, a1, a2
112 ; RV32I-NEXT: addi a3, zero, 31
113 ; RV32I-NEXT: sub a3, a3, a2
114 ; RV32I-NEXT: srli a4, a0, 1
115 ; RV32I-NEXT: srl a3, a4, a3
116 ; RV32I-NEXT: or a1, a1, a3
117 ; RV32I-NEXT: sll a2, a0, a2
118 ; RV32I-NEXT: mv a0, a2
119 ; RV32I-NEXT: ret
120 ;
121 ; RV64I-LABEL: shl64:
122 ; RV64I: # %bb.0:
123 ; RV64I-NEXT: sll a0, a0, a1
124 ; RV64I-NEXT: ret
125 %1 = shl i64 %a, %b
126 ret i64 %1
127 }
129 define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
130 ; RV32I-LABEL: shl64_minsize:
131 ; RV32I: # %bb.0:
132 ; RV32I-NEXT: addi sp, sp, -16
133 ; RV32I-NEXT: sw ra, 12(sp)
134 ; RV32I-NEXT: call __ashldi3
135 ; RV32I-NEXT: lw ra, 12(sp)
136 ; RV32I-NEXT: addi sp, sp, 16
137 ; RV32I-NEXT: ret
138 ;
139 ; RV64I-LABEL: shl64_minsize:
140 ; RV64I: # %bb.0:
141 ; RV64I-NEXT: sll a0, a0, a1
142 ; RV64I-NEXT: ret
143 %1 = shl i64 %a, %b
144 ret i64 %1
145 }
147 define i128 @lshr128(i128 %a, i128 %b) nounwind {
148 ; RV32I-LABEL: lshr128:
149 ; RV32I: # %bb.0:
150 ; RV32I-NEXT: addi sp, sp, -48
151 ; RV32I-NEXT: sw ra, 44(sp)
152 ; RV32I-NEXT: sw s0, 40(sp)
153 ; RV32I-NEXT: lw a2, 0(a2)
154 ; RV32I-NEXT: lw a3, 0(a1)
155 ; RV32I-NEXT: lw a4, 4(a1)
156 ; RV32I-NEXT: lw a5, 8(a1)
157 ; RV32I-NEXT: lw a1, 12(a1)
158 ; RV32I-NEXT: mv s0, a0
159 ; RV32I-NEXT: sw a1, 20(sp)
160 ; RV32I-NEXT: sw a5, 16(sp)
161 ; RV32I-NEXT: sw a4, 12(sp)
162 ; RV32I-NEXT: addi a0, sp, 24
163 ; RV32I-NEXT: addi a1, sp, 8
164 ; RV32I-NEXT: sw a3, 8(sp)
165 ; RV32I-NEXT: call __lshrti3
166 ; RV32I-NEXT: lw a0, 36(sp)
167 ; RV32I-NEXT: lw a1, 32(sp)
168 ; RV32I-NEXT: lw a2, 28(sp)
169 ; RV32I-NEXT: lw a3, 24(sp)
170 ; RV32I-NEXT: sw a0, 12(s0)
171 ; RV32I-NEXT: sw a1, 8(s0)
172 ; RV32I-NEXT: sw a2, 4(s0)
173 ; RV32I-NEXT: sw a3, 0(s0)
174 ; RV32I-NEXT: lw s0, 40(sp)
175 ; RV32I-NEXT: lw ra, 44(sp)
176 ; RV32I-NEXT: addi sp, sp, 48
177 ; RV32I-NEXT: ret
178 ;
179 ; RV64I-LABEL: lshr128:
180 ; RV64I: # %bb.0:
181 ; RV64I-NEXT: addi a3, a2, -64
182 ; RV64I-NEXT: bltz a3, .LBB6_2
183 ; RV64I-NEXT: # %bb.1:
184 ; RV64I-NEXT: srl a0, a1, a3
185 ; RV64I-NEXT: mv a1, zero
186 ; RV64I-NEXT: ret
187 ; RV64I-NEXT: .LBB6_2:
188 ; RV64I-NEXT: srl a0, a0, a2
189 ; RV64I-NEXT: addi a3, zero, 63
190 ; RV64I-NEXT: sub a3, a3, a2
191 ; RV64I-NEXT: slli a4, a1, 1
192 ; RV64I-NEXT: sll a3, a4, a3
193 ; RV64I-NEXT: or a0, a0, a3
194 ; RV64I-NEXT: srl a2, a1, a2
195 ; RV64I-NEXT: mv a1, a2
196 ; RV64I-NEXT: ret
197 %1 = lshr i128 %a, %b
198 ret i128 %1
199 }
201 define i128 @ashr128(i128 %a, i128 %b) nounwind {
202 ; RV32I-LABEL: ashr128:
203 ; RV32I: # %bb.0:
204 ; RV32I-NEXT: addi sp, sp, -48
205 ; RV32I-NEXT: sw ra, 44(sp)
206 ; RV32I-NEXT: sw s0, 40(sp)
207 ; RV32I-NEXT: lw a2, 0(a2)
208 ; RV32I-NEXT: lw a3, 0(a1)
209 ; RV32I-NEXT: lw a4, 4(a1)
210 ; RV32I-NEXT: lw a5, 8(a1)
211 ; RV32I-NEXT: lw a1, 12(a1)
212 ; RV32I-NEXT: mv s0, a0
213 ; RV32I-NEXT: sw a1, 20(sp)
214 ; RV32I-NEXT: sw a5, 16(sp)
215 ; RV32I-NEXT: sw a4, 12(sp)
216 ; RV32I-NEXT: addi a0, sp, 24
217 ; RV32I-NEXT: addi a1, sp, 8
218 ; RV32I-NEXT: sw a3, 8(sp)
219 ; RV32I-NEXT: call __ashrti3
220 ; RV32I-NEXT: lw a0, 36(sp)
221 ; RV32I-NEXT: lw a1, 32(sp)
222 ; RV32I-NEXT: lw a2, 28(sp)
223 ; RV32I-NEXT: lw a3, 24(sp)
224 ; RV32I-NEXT: sw a0, 12(s0)
225 ; RV32I-NEXT: sw a1, 8(s0)
226 ; RV32I-NEXT: sw a2, 4(s0)
227 ; RV32I-NEXT: sw a3, 0(s0)
228 ; RV32I-NEXT: lw s0, 40(sp)
229 ; RV32I-NEXT: lw ra, 44(sp)
230 ; RV32I-NEXT: addi sp, sp, 48
231 ; RV32I-NEXT: ret
232 ;
233 ; RV64I-LABEL: ashr128:
234 ; RV64I: # %bb.0:
235 ; RV64I-NEXT: addi a3, a2, -64
236 ; RV64I-NEXT: bltz a3, .LBB7_2
237 ; RV64I-NEXT: # %bb.1:
238 ; RV64I-NEXT: sra a0, a1, a3
239 ; RV64I-NEXT: srai a1, a1, 63
240 ; RV64I-NEXT: ret
241 ; RV64I-NEXT: .LBB7_2:
242 ; RV64I-NEXT: srl a0, a0, a2
243 ; RV64I-NEXT: addi a3, zero, 63
244 ; RV64I-NEXT: sub a3, a3, a2
245 ; RV64I-NEXT: slli a4, a1, 1
246 ; RV64I-NEXT: sll a3, a4, a3
247 ; RV64I-NEXT: or a0, a0, a3
248 ; RV64I-NEXT: sra a1, a1, a2
249 ; RV64I-NEXT: ret
250 %1 = ashr i128 %a, %b
251 ret i128 %1
252 }
254 define i128 @shl128(i128 %a, i128 %b) nounwind {
255 ; RV32I-LABEL: shl128:
256 ; RV32I: # %bb.0:
257 ; RV32I-NEXT: addi sp, sp, -48
258 ; RV32I-NEXT: sw ra, 44(sp)
259 ; RV32I-NEXT: sw s0, 40(sp)
260 ; RV32I-NEXT: lw a2, 0(a2)
261 ; RV32I-NEXT: lw a3, 0(a1)
262 ; RV32I-NEXT: lw a4, 4(a1)
263 ; RV32I-NEXT: lw a5, 8(a1)
264 ; RV32I-NEXT: lw a1, 12(a1)
265 ; RV32I-NEXT: mv s0, a0
266 ; RV32I-NEXT: sw a1, 20(sp)
267 ; RV32I-NEXT: sw a5, 16(sp)
268 ; RV32I-NEXT: sw a4, 12(sp)
269 ; RV32I-NEXT: addi a0, sp, 24
270 ; RV32I-NEXT: addi a1, sp, 8
271 ; RV32I-NEXT: sw a3, 8(sp)
272 ; RV32I-NEXT: call __ashlti3
273 ; RV32I-NEXT: lw a0, 36(sp)
274 ; RV32I-NEXT: lw a1, 32(sp)
275 ; RV32I-NEXT: lw a2, 28(sp)
276 ; RV32I-NEXT: lw a3, 24(sp)
277 ; RV32I-NEXT: sw a0, 12(s0)
278 ; RV32I-NEXT: sw a1, 8(s0)
279 ; RV32I-NEXT: sw a2, 4(s0)
280 ; RV32I-NEXT: sw a3, 0(s0)
281 ; RV32I-NEXT: lw s0, 40(sp)
282 ; RV32I-NEXT: lw ra, 44(sp)
283 ; RV32I-NEXT: addi sp, sp, 48
284 ; RV32I-NEXT: ret
285 ;
286 ; RV64I-LABEL: shl128:
287 ; RV64I: # %bb.0:
288 ; RV64I-NEXT: addi a3, a2, -64
289 ; RV64I-NEXT: bltz a3, .LBB8_2
290 ; RV64I-NEXT: # %bb.1:
291 ; RV64I-NEXT: sll a1, a0, a3
292 ; RV64I-NEXT: mv a0, zero
293 ; RV64I-NEXT: ret
294 ; RV64I-NEXT: .LBB8_2:
295 ; RV64I-NEXT: sll a1, a1, a2
296 ; RV64I-NEXT: addi a3, zero, 63
297 ; RV64I-NEXT: sub a3, a3, a2
298 ; RV64I-NEXT: srli a4, a0, 1
299 ; RV64I-NEXT: srl a3, a4, a3
300 ; RV64I-NEXT: or a1, a1, a3
301 ; RV64I-NEXT: sll a2, a0, a2
302 ; RV64I-NEXT: mv a0, a2
303 ; RV64I-NEXT: ret
304 %1 = shl i128 %a, %b
305 ret i128 %1
306 }