1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
4 define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
5 ; CHECK-LABEL: cmpeqz_v4i1:
6 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: vpt.i32 ne, q0, zr
8 ; CHECK-NEXT: vcmpt.i32 ne, q1, zr
10 ; CHECK-NEXT: vpsel q0, q0, q1
13 %c1 = icmp eq <4 x i32> %a, zeroinitializer
14 %c2 = icmp eq <4 x i32> %b, zeroinitializer
15 %o = or <4 x i1> %c1, %c2
16 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
20 define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
21 ; CHECK-LABEL: cmpnez_v4i1:
22 ; CHECK: @ %bb.0: @ %entry
23 ; CHECK-NEXT: vpt.i32 ne, q0, zr
24 ; CHECK-NEXT: vcmpt.i32 eq, q1, zr
26 ; CHECK-NEXT: vpsel q0, q0, q1
29 %c1 = icmp eq <4 x i32> %a, zeroinitializer
30 %c2 = icmp ne <4 x i32> %b, zeroinitializer
31 %o = or <4 x i1> %c1, %c2
32 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
36 define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
37 ; CHECK-LABEL: cmpsltz_v4i1:
38 ; CHECK: @ %bb.0: @ %entry
39 ; CHECK-NEXT: vpt.i32 ne, q0, zr
40 ; CHECK-NEXT: vcmpt.s32 ge, q1, zr
42 ; CHECK-NEXT: vpsel q0, q0, q1
45 %c1 = icmp eq <4 x i32> %a, zeroinitializer
46 %c2 = icmp slt <4 x i32> %b, zeroinitializer
47 %o = or <4 x i1> %c1, %c2
48 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
52 define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
53 ; CHECK-LABEL: cmpsgtz_v4i1:
54 ; CHECK: @ %bb.0: @ %entry
55 ; CHECK-NEXT: vpt.i32 ne, q0, zr
56 ; CHECK-NEXT: vcmpt.s32 le, q1, zr
58 ; CHECK-NEXT: vpsel q0, q0, q1
61 %c1 = icmp eq <4 x i32> %a, zeroinitializer
62 %c2 = icmp sgt <4 x i32> %b, zeroinitializer
63 %o = or <4 x i1> %c1, %c2
64 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
68 define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
69 ; CHECK-LABEL: cmpslez_v4i1:
70 ; CHECK: @ %bb.0: @ %entry
71 ; CHECK-NEXT: vpt.i32 ne, q0, zr
72 ; CHECK-NEXT: vcmpt.s32 gt, q1, zr
74 ; CHECK-NEXT: vpsel q0, q0, q1
77 %c1 = icmp eq <4 x i32> %a, zeroinitializer
78 %c2 = icmp sle <4 x i32> %b, zeroinitializer
79 %o = or <4 x i1> %c1, %c2
80 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
84 define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
85 ; CHECK-LABEL: cmpsgez_v4i1:
86 ; CHECK: @ %bb.0: @ %entry
87 ; CHECK-NEXT: vpt.i32 ne, q0, zr
88 ; CHECK-NEXT: vcmpt.s32 lt, q1, zr
90 ; CHECK-NEXT: vpsel q0, q0, q1
93 %c1 = icmp eq <4 x i32> %a, zeroinitializer
94 %c2 = icmp sge <4 x i32> %b, zeroinitializer
95 %o = or <4 x i1> %c1, %c2
96 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
100 define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {
101 ; CHECK-LABEL: cmpultz_v4i1:
102 ; CHECK: @ %bb.0: @ %entry
103 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
104 ; CHECK-NEXT: vpsel q0, q0, q1
107 %c1 = icmp eq <4 x i32> %a, zeroinitializer
108 %c2 = icmp ult <4 x i32> %b, zeroinitializer
109 %o = or <4 x i1> %c1, %c2
110 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
114 define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
115 ; CHECK-LABEL: cmpugtz_v4i1:
116 ; CHECK: @ %bb.0: @ %entry
117 ; CHECK-NEXT: vpt.i32 ne, q0, zr
118 ; CHECK-NEXT: vcmpt.i32 eq, q1, zr
120 ; CHECK-NEXT: vpsel q0, q0, q1
123 %c1 = icmp eq <4 x i32> %a, zeroinitializer
124 %c2 = icmp ugt <4 x i32> %b, zeroinitializer
125 %o = or <4 x i1> %c1, %c2
126 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
130 define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
131 ; CHECK-LABEL: cmpulez_v4i1:
132 ; CHECK: @ %bb.0: @ %entry
133 ; CHECK-NEXT: vcmp.u32 cs, q1, zr
134 ; CHECK-NEXT: vmrs r0, p0
135 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
136 ; CHECK-NEXT: vmrs r1, p0
137 ; CHECK-NEXT: orrs r0, r1
138 ; CHECK-NEXT: vmsr p0, r0
139 ; CHECK-NEXT: vpsel q0, q0, q1
142 %c1 = icmp eq <4 x i32> %a, zeroinitializer
143 %c2 = icmp ule <4 x i32> %b, zeroinitializer
144 %o = or <4 x i1> %c1, %c2
145 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
149 define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {
150 ; CHECK-LABEL: cmpugez_v4i1:
151 ; CHECK: @ %bb.0: @ %entry
154 %c1 = icmp eq <4 x i32> %a, zeroinitializer
155 %c2 = icmp uge <4 x i32> %b, zeroinitializer
156 %o = or <4 x i1> %c1, %c2
157 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
163 define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164 ; CHECK-LABEL: cmpeq_v4i1:
165 ; CHECK: @ %bb.0: @ %entry
166 ; CHECK-NEXT: vpt.i32 ne, q0, zr
167 ; CHECK-NEXT: vcmpt.i32 ne, q1, q2
169 ; CHECK-NEXT: vpsel q0, q0, q1
172 %c1 = icmp eq <4 x i32> %a, zeroinitializer
173 %c2 = icmp eq <4 x i32> %b, %c
174 %o = or <4 x i1> %c1, %c2
175 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
179 define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
180 ; CHECK-LABEL: cmpne_v4i1:
181 ; CHECK: @ %bb.0: @ %entry
182 ; CHECK-NEXT: vpt.i32 ne, q0, zr
183 ; CHECK-NEXT: vcmpt.i32 eq, q1, q2
185 ; CHECK-NEXT: vpsel q0, q0, q1
188 %c1 = icmp eq <4 x i32> %a, zeroinitializer
189 %c2 = icmp ne <4 x i32> %b, %c
190 %o = or <4 x i1> %c1, %c2
191 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
195 define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
196 ; CHECK-LABEL: cmpslt_v4i1:
197 ; CHECK: @ %bb.0: @ %entry
198 ; CHECK-NEXT: vpt.i32 ne, q0, zr
199 ; CHECK-NEXT: vcmpt.s32 le, q2, q1
201 ; CHECK-NEXT: vpsel q0, q0, q1
204 %c1 = icmp eq <4 x i32> %a, zeroinitializer
205 %c2 = icmp slt <4 x i32> %b, %c
206 %o = or <4 x i1> %c1, %c2
207 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
211 define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
212 ; CHECK-LABEL: cmpsgt_v4i1:
213 ; CHECK: @ %bb.0: @ %entry
214 ; CHECK-NEXT: vpt.i32 ne, q0, zr
215 ; CHECK-NEXT: vcmpt.s32 le, q1, q2
217 ; CHECK-NEXT: vpsel q0, q0, q1
220 %c1 = icmp eq <4 x i32> %a, zeroinitializer
221 %c2 = icmp sgt <4 x i32> %b, %c
222 %o = or <4 x i1> %c1, %c2
223 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
227 define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
228 ; CHECK-LABEL: cmpsle_v4i1:
229 ; CHECK: @ %bb.0: @ %entry
230 ; CHECK-NEXT: vpt.i32 ne, q0, zr
231 ; CHECK-NEXT: vcmpt.s32 lt, q2, q1
233 ; CHECK-NEXT: vpsel q0, q0, q1
236 %c1 = icmp eq <4 x i32> %a, zeroinitializer
237 %c2 = icmp sle <4 x i32> %b, %c
238 %o = or <4 x i1> %c1, %c2
239 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
243 define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
244 ; CHECK-LABEL: cmpsge_v4i1:
245 ; CHECK: @ %bb.0: @ %entry
246 ; CHECK-NEXT: vpt.i32 ne, q0, zr
247 ; CHECK-NEXT: vcmpt.s32 lt, q1, q2
249 ; CHECK-NEXT: vpsel q0, q0, q1
252 %c1 = icmp eq <4 x i32> %a, zeroinitializer
253 %c2 = icmp sge <4 x i32> %b, %c
254 %o = or <4 x i1> %c1, %c2
255 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
259 define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
260 ; CHECK-LABEL: cmpult_v4i1:
261 ; CHECK: @ %bb.0: @ %entry
262 ; CHECK-NEXT: vcmp.u32 hi, q2, q1
263 ; CHECK-NEXT: vmrs r0, p0
264 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
265 ; CHECK-NEXT: vmrs r1, p0
266 ; CHECK-NEXT: orrs r0, r1
267 ; CHECK-NEXT: vmsr p0, r0
268 ; CHECK-NEXT: vpsel q0, q0, q1
271 %c1 = icmp eq <4 x i32> %a, zeroinitializer
272 %c2 = icmp ult <4 x i32> %b, %c
273 %o = or <4 x i1> %c1, %c2
274 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
278 define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
279 ; CHECK-LABEL: cmpugt_v4i1:
280 ; CHECK: @ %bb.0: @ %entry
281 ; CHECK-NEXT: vcmp.u32 hi, q1, q2
282 ; CHECK-NEXT: vmrs r0, p0
283 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
284 ; CHECK-NEXT: vmrs r1, p0
285 ; CHECK-NEXT: orrs r0, r1
286 ; CHECK-NEXT: vmsr p0, r0
287 ; CHECK-NEXT: vpsel q0, q0, q1
290 %c1 = icmp eq <4 x i32> %a, zeroinitializer
291 %c2 = icmp ugt <4 x i32> %b, %c
292 %o = or <4 x i1> %c1, %c2
293 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
297 define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
298 ; CHECK-LABEL: cmpule_v4i1:
299 ; CHECK: @ %bb.0: @ %entry
300 ; CHECK-NEXT: vcmp.u32 cs, q2, q1
301 ; CHECK-NEXT: vmrs r0, p0
302 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
303 ; CHECK-NEXT: vmrs r1, p0
304 ; CHECK-NEXT: orrs r0, r1
305 ; CHECK-NEXT: vmsr p0, r0
306 ; CHECK-NEXT: vpsel q0, q0, q1
309 %c1 = icmp eq <4 x i32> %a, zeroinitializer
310 %c2 = icmp ule <4 x i32> %b, %c
311 %o = or <4 x i1> %c1, %c2
312 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
316 define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
317 ; CHECK-LABEL: cmpuge_v4i1:
318 ; CHECK: @ %bb.0: @ %entry
319 ; CHECK-NEXT: vcmp.u32 cs, q1, q2
320 ; CHECK-NEXT: vmrs r0, p0
321 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
322 ; CHECK-NEXT: vmrs r1, p0
323 ; CHECK-NEXT: orrs r0, r1
324 ; CHECK-NEXT: vmsr p0, r0
325 ; CHECK-NEXT: vpsel q0, q0, q1
328 %c1 = icmp eq <4 x i32> %a, zeroinitializer
329 %c2 = icmp uge <4 x i32> %b, %c
330 %o = or <4 x i1> %c1, %c2
331 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
338 define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
339 ; CHECK-LABEL: cmpeqz_v8i1:
340 ; CHECK: @ %bb.0: @ %entry
341 ; CHECK-NEXT: vpt.i16 ne, q0, zr
342 ; CHECK-NEXT: vcmpt.i16 ne, q1, zr
344 ; CHECK-NEXT: vpsel q0, q0, q1
347 %c1 = icmp eq <8 x i16> %a, zeroinitializer
348 %c2 = icmp eq <8 x i16> %b, zeroinitializer
349 %o = or <8 x i1> %c1, %c2
350 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
354 define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
355 ; CHECK-LABEL: cmpeq_v8i1:
356 ; CHECK: @ %bb.0: @ %entry
357 ; CHECK-NEXT: vpt.i16 ne, q0, zr
358 ; CHECK-NEXT: vcmpt.i16 ne, q1, q2
360 ; CHECK-NEXT: vpsel q0, q0, q1
363 %c1 = icmp eq <8 x i16> %a, zeroinitializer
364 %c2 = icmp eq <8 x i16> %b, %c
365 %o = or <8 x i1> %c1, %c2
366 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
371 define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
372 ; CHECK-LABEL: cmpeqz_v16i1:
373 ; CHECK: @ %bb.0: @ %entry
374 ; CHECK-NEXT: vpt.i8 ne, q0, zr
375 ; CHECK-NEXT: vcmpt.i8 ne, q1, zr
377 ; CHECK-NEXT: vpsel q0, q0, q1
380 %c1 = icmp eq <16 x i8> %a, zeroinitializer
381 %c2 = icmp eq <16 x i8> %b, zeroinitializer
382 %o = or <16 x i1> %c1, %c2
383 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
387 define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
388 ; CHECK-LABEL: cmpeq_v16i1:
389 ; CHECK: @ %bb.0: @ %entry
390 ; CHECK-NEXT: vpt.i8 ne, q0, zr
391 ; CHECK-NEXT: vcmpt.i8 ne, q1, q2
393 ; CHECK-NEXT: vpsel q0, q0, q1
396 %c1 = icmp eq <16 x i8> %a, zeroinitializer
397 %c2 = icmp eq <16 x i8> %b, %c
398 %o = or <16 x i1> %c1, %c2
399 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
404 define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
405 ; CHECK-LABEL: cmpeqz_v2i1:
406 ; CHECK: @ %bb.0: @ %entry
407 ; CHECK-NEXT: vmov r0, s5
408 ; CHECK-NEXT: vmov r1, s4
409 ; CHECK-NEXT: orrs r0, r1
410 ; CHECK-NEXT: vmov r1, s6
411 ; CHECK-NEXT: cset r0, eq
412 ; CHECK-NEXT: tst.w r0, #1
413 ; CHECK-NEXT: csetm r0, ne
414 ; CHECK-NEXT: vmov.32 q2[0], r0
415 ; CHECK-NEXT: vmov.32 q2[1], r0
416 ; CHECK-NEXT: vmov r0, s7
417 ; CHECK-NEXT: orrs r0, r1
418 ; CHECK-NEXT: vmov r1, s0
419 ; CHECK-NEXT: cset r0, eq
420 ; CHECK-NEXT: tst.w r0, #1
421 ; CHECK-NEXT: csetm r0, ne
422 ; CHECK-NEXT: vmov.32 q2[2], r0
423 ; CHECK-NEXT: vmov.32 q2[3], r0
424 ; CHECK-NEXT: vmov r0, s1
425 ; CHECK-NEXT: orrs r0, r1
426 ; CHECK-NEXT: vmov r1, s2
427 ; CHECK-NEXT: cset r0, eq
428 ; CHECK-NEXT: tst.w r0, #1
429 ; CHECK-NEXT: csetm r0, ne
430 ; CHECK-NEXT: vmov.32 q3[0], r0
431 ; CHECK-NEXT: vmov.32 q3[1], r0
432 ; CHECK-NEXT: vmov r0, s3
433 ; CHECK-NEXT: orrs r0, r1
434 ; CHECK-NEXT: cset r0, eq
435 ; CHECK-NEXT: tst.w r0, #1
436 ; CHECK-NEXT: csetm r0, ne
437 ; CHECK-NEXT: vmov.32 q3[2], r0
438 ; CHECK-NEXT: vmov.32 q3[3], r0
439 ; CHECK-NEXT: vorr q2, q3, q2
440 ; CHECK-NEXT: vbic q1, q1, q2
441 ; CHECK-NEXT: vand q0, q0, q2
442 ; CHECK-NEXT: vorr q0, q0, q1
445 %c1 = icmp eq <2 x i64> %a, zeroinitializer
446 %c2 = icmp eq <2 x i64> %b, zeroinitializer
447 %o = or <2 x i1> %c1, %c2
448 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
452 define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
453 ; CHECK-LABEL: cmpeq_v2i1:
454 ; CHECK: @ %bb.0: @ %entry
455 ; CHECK-NEXT: vmov r0, s9
456 ; CHECK-NEXT: vmov r1, s5
457 ; CHECK-NEXT: vmov r2, s4
458 ; CHECK-NEXT: eors r0, r1
459 ; CHECK-NEXT: vmov r1, s8
460 ; CHECK-NEXT: eors r1, r2
461 ; CHECK-NEXT: vmov r2, s6
462 ; CHECK-NEXT: orrs r0, r1
463 ; CHECK-NEXT: vmov r1, s7
464 ; CHECK-NEXT: cset r0, eq
465 ; CHECK-NEXT: tst.w r0, #1
466 ; CHECK-NEXT: csetm r0, ne
467 ; CHECK-NEXT: vmov.32 q3[0], r0
468 ; CHECK-NEXT: vmov.32 q3[1], r0
469 ; CHECK-NEXT: vmov r0, s11
470 ; CHECK-NEXT: eors r0, r1
471 ; CHECK-NEXT: vmov r1, s10
472 ; CHECK-NEXT: eors r1, r2
473 ; CHECK-NEXT: orrs r0, r1
474 ; CHECK-NEXT: vmov r1, s0
475 ; CHECK-NEXT: cset r0, eq
476 ; CHECK-NEXT: tst.w r0, #1
477 ; CHECK-NEXT: csetm r0, ne
478 ; CHECK-NEXT: vmov.32 q3[2], r0
479 ; CHECK-NEXT: vmov.32 q3[3], r0
480 ; CHECK-NEXT: vmov r0, s1
481 ; CHECK-NEXT: orrs r0, r1
482 ; CHECK-NEXT: vmov r1, s2
483 ; CHECK-NEXT: cset r0, eq
484 ; CHECK-NEXT: tst.w r0, #1
485 ; CHECK-NEXT: csetm r0, ne
486 ; CHECK-NEXT: vmov.32 q2[0], r0
487 ; CHECK-NEXT: vmov.32 q2[1], r0
488 ; CHECK-NEXT: vmov r0, s3
489 ; CHECK-NEXT: orrs r0, r1
490 ; CHECK-NEXT: cset r0, eq
491 ; CHECK-NEXT: tst.w r0, #1
492 ; CHECK-NEXT: csetm r0, ne
493 ; CHECK-NEXT: vmov.32 q2[2], r0
494 ; CHECK-NEXT: vmov.32 q2[3], r0
495 ; CHECK-NEXT: vorr q2, q2, q3
496 ; CHECK-NEXT: vbic q1, q1, q2
497 ; CHECK-NEXT: vand q0, q0, q2
498 ; CHECK-NEXT: vorr q0, q0, q1
501 %c1 = icmp eq <2 x i64> %a, zeroinitializer
502 %c2 = icmp eq <2 x i64> %b, %c
503 %o = or <2 x i1> %c1, %c2
504 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b