1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
4 declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>)
5 declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
6 declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
7 declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>)
8 declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>)
9 declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
10 declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>)
11 declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>)
12 declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
13 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
14 declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>)
15 declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
17 define arm_aapcs_vfpcc i8 @vmaxv_s_v16i8_i32(<16 x i8> %s1) {
18 ; CHECK-LABEL: vmaxv_s_v16i8_i32:
20 ; CHECK-NEXT: mvn r0, #127
21 ; CHECK-NEXT: vmaxv.s8 r0, q0
23 %r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %s1)
27 define arm_aapcs_vfpcc i16 @vmaxv_s_v8i16_i32(<8 x i16> %s1) {
28 ; CHECK-LABEL: vmaxv_s_v8i16_i32:
30 ; CHECK-NEXT: movw r0, #32768
31 ; CHECK-NEXT: movt r0, #65535
32 ; CHECK-NEXT: vmaxv.s16 r0, q0
34 %r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %s1)
38 define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32_i32(<4 x i32> %s1) {
39 ; CHECK-LABEL: vmaxv_s_v4i32_i32:
41 ; CHECK-NEXT: mov.w r0, #-2147483648
42 ; CHECK-NEXT: vmaxv.s32 r0, q0
44 %r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %s1)
48 define arm_aapcs_vfpcc i8 @vmaxv_u_v16i8_i32(<16 x i8> %s1) {
49 ; CHECK-LABEL: vmaxv_u_v16i8_i32:
51 ; CHECK-NEXT: movs r0, #0
52 ; CHECK-NEXT: vmaxv.u8 r0, q0
54 %r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %s1)
58 define arm_aapcs_vfpcc i16 @vmaxv_u_v8i16_i32(<8 x i16> %s1) {
59 ; CHECK-LABEL: vmaxv_u_v8i16_i32:
61 ; CHECK-NEXT: movs r0, #0
62 ; CHECK-NEXT: vmaxv.u16 r0, q0
64 %r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %s1)
68 define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32_i32(<4 x i32> %s1) {
69 ; CHECK-LABEL: vmaxv_u_v4i32_i32:
71 ; CHECK-NEXT: movs r0, #0
72 ; CHECK-NEXT: vmaxv.u32 r0, q0
74 %r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %s1)
78 define arm_aapcs_vfpcc i8 @vminv_s_v16i8_i32(<16 x i8> %s1) {
79 ; CHECK-LABEL: vminv_s_v16i8_i32:
81 ; CHECK-NEXT: movs r0, #127
82 ; CHECK-NEXT: vminv.s8 r0, q0
84 %r = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> %s1)
88 define arm_aapcs_vfpcc i16 @vminv_s_v8i16_i32(<8 x i16> %s1) {
89 ; CHECK-LABEL: vminv_s_v8i16_i32:
91 ; CHECK-NEXT: movw r0, #32767
92 ; CHECK-NEXT: vminv.s16 r0, q0
94 %r = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> %s1)
98 define arm_aapcs_vfpcc i32 @vminv_s_v4i32_i32(<4 x i32> %s1) {
99 ; CHECK-LABEL: vminv_s_v4i32_i32:
101 ; CHECK-NEXT: mvn r0, #-2147483648
102 ; CHECK-NEXT: vminv.s32 r0, q0
104 %r = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %s1)
108 define arm_aapcs_vfpcc i8 @vminv_u_v16i8_i32(<16 x i8> %s1) {
109 ; CHECK-LABEL: vminv_u_v16i8_i32:
111 ; CHECK-NEXT: movs r0, #255
112 ; CHECK-NEXT: vminv.u8 r0, q0
114 %r = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> %s1)
118 define arm_aapcs_vfpcc i16 @vminv_u_v8i16_i32(<8 x i16> %s1) {
119 ; CHECK-LABEL: vminv_u_v8i16_i32:
121 ; CHECK-NEXT: movw r0, #65535
122 ; CHECK-NEXT: vminv.u16 r0, q0
124 %r = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> %s1)
128 define arm_aapcs_vfpcc i32 @vminv_u_v4i32_i32(<4 x i32> %s1) {
129 ; CHECK-LABEL: vminv_u_v4i32_i32:
131 ; CHECK-NEXT: mov.w r0, #-1
132 ; CHECK-NEXT: vminv.u32 r0, q0
134 %r = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %s1)