lib/Target/Hexagon/HexagonTargetMachine.cpp

   1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implements the info about Hexagon target spec.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "HexagonTargetMachine.h"
  14 #include "Hexagon.h"
  15 #include "HexagonISelLowering.h"
  16 #include "HexagonMachineScheduler.h"
  17 #include "HexagonTargetObjectFile.h"
  18 #include "HexagonTargetTransformInfo.h"
  19 #include "TargetInfo/HexagonTargetInfo.h"
  20 #include "llvm/CodeGen/Passes.h"
  21 #include "llvm/CodeGen/TargetPassConfig.h"
  22 #include "llvm/IR/LegacyPassManager.h"
  23 #include "llvm/IR/Module.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/TargetRegistry.h"
  26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
  27 #include "llvm/Transforms/Scalar.h"
  28
  29 using namespace llvm;
  30
  31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
  32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
  33
  34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
  35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
  36
  37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
  38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
  39
  40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
  41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
  43
  44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
  45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  46   cl::desc("Disable Hexagon CFG Optimization"));
  47
  48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
  49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
  50
  51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
  52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
  53
  54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
  55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
  56   cl::desc("Early expansion of MUX"));
  57
  58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
  59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
  60
  61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
  62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
  63
  64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
  65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
  66
  67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
  68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
  69
  70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
  71   cl::desc("Enable converting conditional transfers into MUX instructions"));
  72
  73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
  74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
  75   "predicate instructions"));
  76
  77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
  78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
  79   cl::desc("Enable loop data prefetch on Hexagon"));
  80
  81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
  82   cl::desc("Disable splitting double registers"));
  83
  84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
  85   cl::Hidden, cl::desc("Bit simplification"));
  86
  87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
  88   cl::Hidden, cl::desc("Loop rescheduling"));
  89
  90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
  91   cl::Hidden, cl::desc("Disable backend optimizations"));
  92
  93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
  94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  95   cl::desc("Enable Hexagon Vector print instr pass"));
  96
  97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
  98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
  99
 100 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
 101   cl::Hidden, cl::ZeroOrMore, cl::init(true),
 102   cl::desc("Simplify the CFG after atomic expansion pass"));
 103
 104 /// HexagonTargetMachineModule - Note that this is used on hosts that
 105 /// cannot link in a library unless there are references into the
 106 /// library.  In particular, it seems that it is not possible to get
 107 /// things to work on Win32 without this.  Though it is unused, do not
 108 /// remove it.
 109 extern "C" int HexagonTargetMachineModule;
 110 int HexagonTargetMachineModule = 0;
 111
 112 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
 113   ScheduleDAGMILive *DAG =
 114     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
 115   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
 116   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
 117   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
 118   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
 119   return DAG;
 120 }
 121
 122 static MachineSchedRegistry
 123 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
 124                     createVLIWMachineSched);
 125
 126 namespace llvm {
 127   extern char &HexagonExpandCondsetsID;
 128   void initializeHexagonBitSimplifyPass(PassRegistry&);
 129   void initializeHexagonConstExtendersPass(PassRegistry&);
 130   void initializeHexagonConstPropagationPass(PassRegistry&);
 131   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
 132   void initializeHexagonExpandCondsetsPass(PassRegistry&);
 133   void initializeHexagonGenMuxPass(PassRegistry&);
 134   void initializeHexagonHardwareLoopsPass(PassRegistry&);
 135   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
 136   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
 137   void initializeHexagonNewValueJumpPass(PassRegistry&);
 138   void initializeHexagonOptAddrModePass(PassRegistry&);
 139   void initializeHexagonPacketizerPass(PassRegistry&);
 140   void initializeHexagonRDFOptPass(PassRegistry&);
 141   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
 142   void initializeHexagonVExtractPass(PassRegistry&);
 143   Pass *createHexagonLoopIdiomPass();
 144   Pass *createHexagonVectorLoopCarriedReusePass();
 145
 146   FunctionPass *createHexagonBitSimplify();
 147   FunctionPass *createHexagonBranchRelaxation();
 148   FunctionPass *createHexagonCallFrameInformation();
 149   FunctionPass *createHexagonCFGOptimizer();
 150   FunctionPass *createHexagonCommonGEP();
 151   FunctionPass *createHexagonConstExtenders();
 152   FunctionPass *createHexagonConstPropagationPass();
 153   FunctionPass *createHexagonCopyToCombine();
 154   FunctionPass *createHexagonEarlyIfConversion();
 155   FunctionPass *createHexagonFixupHwLoops();
 156   FunctionPass *createHexagonGenExtract();
 157   FunctionPass *createHexagonGenInsert();
 158   FunctionPass *createHexagonGenMux();
 159   FunctionPass *createHexagonGenPredicate();
 160   FunctionPass *createHexagonHardwareLoops();
 161   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
 162                                      CodeGenOpt::Level OptLevel);
 163   FunctionPass *createHexagonLoopRescheduling();
 164   FunctionPass *createHexagonNewValueJump();
 165   FunctionPass *createHexagonOptimizeSZextends();
 166   FunctionPass *createHexagonOptAddrMode();
 167   FunctionPass *createHexagonPacketizer(bool Minimal);
 168   FunctionPass *createHexagonPeephole();
 169   FunctionPass *createHexagonRDFOpt();
 170   FunctionPass *createHexagonSplitConst32AndConst64();
 171   FunctionPass *createHexagonSplitDoubleRegs();
 172   FunctionPass *createHexagonStoreWidening();
 173   FunctionPass *createHexagonVectorPrint();
 174   FunctionPass *createHexagonVExtract();
 175 } // end namespace llvm;
 176
 177 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
 178   if (!RM.hasValue())
 179     return Reloc::Static;
 180   return *RM;
 181 }
 182
 183 extern "C" void LLVMInitializeHexagonTarget() {
 184   // Register the target.
 185   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
 186
 187   PassRegistry &PR = *PassRegistry::getPassRegistry();
 188   initializeHexagonBitSimplifyPass(PR);
 189   initializeHexagonConstExtendersPass(PR);
 190   initializeHexagonConstPropagationPass(PR);
 191   initializeHexagonEarlyIfConversionPass(PR);
 192   initializeHexagonGenMuxPass(PR);
 193   initializeHexagonHardwareLoopsPass(PR);
 194   initializeHexagonLoopIdiomRecognizePass(PR);
 195   initializeHexagonVectorLoopCarriedReusePass(PR);
 196   initializeHexagonNewValueJumpPass(PR);
 197   initializeHexagonOptAddrModePass(PR);
 198   initializeHexagonPacketizerPass(PR);
 199   initializeHexagonRDFOptPass(PR);
 200   initializeHexagonSplitDoubleRegsPass(PR);
 201   initializeHexagonVExtractPass(PR);
 202 }
 203
 204 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
 205                                            StringRef CPU, StringRef FS,
 206                                            const TargetOptions &Options,
 207                                            Optional<Reloc::Model> RM,
 208                                            Optional<CodeModel::Model> CM,
 209                                            CodeGenOpt::Level OL, bool JIT)
 210     // Specify the vector alignment explicitly. For v512x1, the calculated
 211     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
 212     // the required minimum of 64 bytes.
 213     : LLVMTargetMachine(
 214           T,
 215           "e-m:e-p:32:32:32-a:0-n16:32-"
 216           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
 217           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
 218           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
 219           getEffectiveCodeModel(CM, CodeModel::Small),
 220           (HexagonNoOpt ? CodeGenOpt::None : OL)),
 221       TLOF(make_unique<HexagonTargetObjectFile>()) {
 222   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
 223   initAsmInfo();
 224 }
 225
 226 const HexagonSubtarget *
 227 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
 228   AttributeList FnAttrs = F.getAttributes();
 229   Attribute CPUAttr =
 230       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
 231   Attribute FSAttr =
 232       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
 233
 234   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
 235                         ? CPUAttr.getValueAsString().str()
 236                         : TargetCPU;
 237   std::string FS = !FSAttr.hasAttribute(Attribute::None)
 238                        ? FSAttr.getValueAsString().str()
 239                        : TargetFS;
 240
 241   auto &I = SubtargetMap[CPU + FS];
 242   if (!I) {
 243     // This needs to be done before we create a new subtarget since any
 244     // creation will depend on the TM and the code generation flags on the
 245     // function that reside in TargetOptions.
 246     resetTargetOptions(F);
 247     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
 248   }
 249   return I.get();
 250 }
 251
 252 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
 253   PMB.addExtension(
 254     PassManagerBuilder::EP_LateLoopOptimizations,
 255     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
 256       PM.add(createHexagonLoopIdiomPass());
 257     });
 258   PMB.addExtension(
 259     PassManagerBuilder::EP_LoopOptimizerEnd,
 260     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
 261       PM.add(createHexagonVectorLoopCarriedReusePass());
 262     });
 263 }
 264
 265 TargetTransformInfo
 266 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
 267   return TargetTransformInfo(HexagonTTIImpl(this, F));
 268 }
 269
 270
 271 HexagonTargetMachine::~HexagonTargetMachine() {}
 272
 273 namespace {
 274 /// Hexagon Code Generator Pass Configuration Options.
 275 class HexagonPassConfig : public TargetPassConfig {
 276 public:
 277   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
 278     : TargetPassConfig(TM, PM) {}
 279
 280   HexagonTargetMachine &getHexagonTargetMachine() const {
 281     return getTM<HexagonTargetMachine>();
 282   }
 283
 284   ScheduleDAGInstrs *
 285   createMachineScheduler(MachineSchedContext *C) const override {
 286     return createVLIWMachineSched(C);
 287   }
 288
 289   void addIRPasses() override;
 290   bool addInstSelector() override;
 291   void addPreRegAlloc() override;
 292   void addPostRegAlloc() override;
 293   void addPreSched2() override;
 294   void addPreEmitPass() override;
 295 };
 296 } // namespace
 297
 298 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
 299   return new HexagonPassConfig(*this, PM);
 300 }
 301
 302 void HexagonPassConfig::addIRPasses() {
 303   TargetPassConfig::addIRPasses();
 304   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
 305
 306   if (!NoOpt) {
 307     addPass(createConstantPropagationPass());
 308     addPass(createDeadCodeEliminationPass());
 309   }
 310
 311   addPass(createAtomicExpandPass());
 312
 313   if (!NoOpt) {
 314     if (EnableInitialCFGCleanup)
 315       addPass(createCFGSimplificationPass(1, true, true, false, true));
 316     if (EnableLoopPrefetch)
 317       addPass(createLoopDataPrefetchPass());
 318     if (EnableCommGEP)
 319       addPass(createHexagonCommonGEP());
 320     // Replace certain combinations of shifts and ands with extracts.
 321     if (EnableGenExtract)
 322       addPass(createHexagonGenExtract());
 323   }
 324 }
 325
 326 bool HexagonPassConfig::addInstSelector() {
 327   HexagonTargetMachine &TM = getHexagonTargetMachine();
 328   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
 329
 330   if (!NoOpt)
 331     addPass(createHexagonOptimizeSZextends());
 332
 333   addPass(createHexagonISelDag(TM, getOptLevel()));
 334
 335   if (!NoOpt) {
 336     if (EnableVExtractOpt)
 337       addPass(createHexagonVExtract());
 338     // Create logical operations on predicate registers.
 339     if (EnableGenPred)
 340       addPass(createHexagonGenPredicate());
 341     // Rotate loops to expose bit-simplification opportunities.
 342     if (EnableLoopResched)
 343       addPass(createHexagonLoopRescheduling());
 344     // Split double registers.
 345     if (!DisableHSDR)
 346       addPass(createHexagonSplitDoubleRegs());
 347     // Bit simplification.
 348     if (EnableBitSimplify)
 349       addPass(createHexagonBitSimplify());
 350     addPass(createHexagonPeephole());
 351     // Constant propagation.
 352     if (!DisableHCP) {
 353       addPass(createHexagonConstPropagationPass());
 354       addPass(&UnreachableMachineBlockElimID);
 355     }
 356     if (EnableGenInsert)
 357       addPass(createHexagonGenInsert());
 358     if (EnableEarlyIf)
 359       addPass(createHexagonEarlyIfConversion());
 360   }
 361
 362   return false;
 363 }
 364
 365 void HexagonPassConfig::addPreRegAlloc() {
 366   if (getOptLevel() != CodeGenOpt::None) {
 367     if (EnableCExtOpt)
 368       addPass(createHexagonConstExtenders());
 369     if (EnableExpandCondsets)
 370       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
 371     if (!DisableStoreWidening)
 372       addPass(createHexagonStoreWidening());
 373     if (!DisableHardwareLoops)
 374       addPass(createHexagonHardwareLoops());
 375   }
 376   if (TM->getOptLevel() >= CodeGenOpt::Default)
 377     addPass(&MachinePipelinerID);
 378 }
 379
 380 void HexagonPassConfig::addPostRegAlloc() {
 381   if (getOptLevel() != CodeGenOpt::None) {
 382     if (EnableRDFOpt)
 383       addPass(createHexagonRDFOpt());
 384     if (!DisableHexagonCFGOpt)
 385       addPass(createHexagonCFGOptimizer());
 386     if (!DisableAModeOpt)
 387       addPass(createHexagonOptAddrMode());
 388   }
 389 }
 390
 391 void HexagonPassConfig::addPreSched2() {
 392   addPass(createHexagonCopyToCombine());
 393   if (getOptLevel() != CodeGenOpt::None)
 394     addPass(&IfConverterID);
 395   addPass(createHexagonSplitConst32AndConst64());
 396 }
 397
 398 void HexagonPassConfig::addPreEmitPass() {
 399   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
 400
 401   if (!NoOpt)
 402     addPass(createHexagonNewValueJump());
 403
 404   addPass(createHexagonBranchRelaxation());
 405
 406   if (!NoOpt) {
 407     if (!DisableHardwareLoops)
 408       addPass(createHexagonFixupHwLoops());
 409     // Generate MUX from pairs of conditional transfers.
 410     if (EnableGenMux)
 411       addPass(createHexagonGenMux());
 412   }
 413
 414   // Packetization is mandatory: it handles gather/scatter at all opt levels.
 415   addPass(createHexagonPacketizer(NoOpt), false);
 416
 417   if (EnableVectorPrint)
 418     addPass(createHexagonVectorPrint(), false);
 419
 420   // Add CFI instructions if necessary.
 421   addPass(createHexagonCallFrameInformation(), false);
 422 }