lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This is the top level entry point for the PowerPC target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // Get the target-independent interfaces which we are implementing.
  14 //
  15 include "llvm/Target/Target.td"
  16
  17 //===----------------------------------------------------------------------===//
  18 // PowerPC Subtarget features.
  19 //
  20
  21 //===----------------------------------------------------------------------===//
  22 // CPU Directives                                                             //
  23 //===----------------------------------------------------------------------===//
  24
  25 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  26 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  27 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  28 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  29 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  32 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  33 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  34 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  35 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  36 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  37 def DirectiveE500   : SubtargetFeature<"", "DarwinDirective",
  38                                        "PPC::DIR_E500", "">;
  39 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  40                                        "PPC::DIR_E500mc", "">;
  41 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  42                                        "PPC::DIR_E5500", "">;
  43 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  44 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  45 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  46 def DirectivePwr5x
  47     : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  48 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  49 def DirectivePwr6x
  50     : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  51 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  52 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  53 def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">;
  54
  55 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  56                                         "Enable 64-bit instructions">;
  57 def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
  58                               "Enable floating-point instructions">;
  59 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  60                               "Enable 64-bit registers usage for ppc32 [beta]">;
  61 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  62                               "Use condition-register bits individually">;
  63 def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
  64                                         "Enable classic FPU instructions",
  65                                         [FeatureHardFloat]>;
  66 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  67                                         "Enable Altivec instructions",
  68                                         [FeatureFPU]>;
  69 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  70                                         "Enable SPE instructions",
  71                                         [FeatureHardFloat]>;
  72 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  73                                         "Enable the MFOCRF instruction">;
  74 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  75                                         "Enable the fsqrt instruction",
  76                                         [FeatureFPU]>;
  77 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  78                                         "Enable the fcpsgn instruction",
  79                                         [FeatureFPU]>;
  80 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  81                                         "Enable the fre instruction",
  82                                         [FeatureFPU]>;
  83 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  84                                         "Enable the fres instruction",
  85                                         [FeatureFPU]>;
  86 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  87                                         "Enable the frsqrte instruction",
  88                                         [FeatureFPU]>;
  89 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  90                                         "Enable the frsqrtes instruction",
  91                                         [FeatureFPU]>;
  92 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  93                               "Assume higher precision reciprocal estimates">;
  94 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  95                                         "Enable the stfiwx instruction",
  96                                         [FeatureFPU]>;
  97 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  98                                         "Enable the lfiwax instruction",
  99                                         [FeatureFPU]>;
 100 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
 101                                         "Enable the fri[mnpz] instructions",
 102                                         [FeatureFPU]>;
 103 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
 104   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
 105                                         [FeatureFPU]>;
 106 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
 107                                         "Enable the isel instruction">;
 108 def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
 109                                         "Enable the bpermd instruction">;
 110 def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
 111                                         "Enable extended divide instructions">;
 112 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
 113                                         "Enable the ldbrx instruction">;
 114 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
 115                                         "Enable the cmpb instruction">;
 116 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
 117                                         "Enable icbt instruction">;
 118 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
 119                                         "Enable Book E instructions",
 120                                         [FeatureICBT]>;
 121 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
 122                               "Has only the msync instruction instead of sync",
 123                               [FeatureBookE]>;
 124 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 125                                         "Enable E500/E500mc instructions">;
 126 def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
 127                                         "Enable secure plt mode">;
 128 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 129                                         "Enable PPC 4xx instructions">;
 130 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 131                                         "Enable PPC 6xx instructions">;
 132 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 133                                         "Enable QPX instructions",
 134                                         [FeatureFPU]>;
 135 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 136                                         "Enable VSX instructions",
 137                                         [FeatureAltivec]>;
 138 def FeatureTwoConstNR :
 139   SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
 140                    "Requires two constant Newton-Raphson computation">;
 141 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 142                                         "Enable POWER8 Altivec instructions",
 143                                         [FeatureAltivec]>;
 144 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 145                                        "Enable POWER8 Crypto instructions",
 146                                        [FeatureP8Altivec]>;
 147 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 148                                         "Enable POWER8 vector instructions",
 149                                         [FeatureVSX, FeatureP8Altivec]>;
 150 def FeatureDirectMove :
 151   SubtargetFeature<"direct-move", "HasDirectMove", "true",
 152                    "Enable Power8 direct move instructions",
 153                    [FeatureVSX]>;
 154 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
 155                                              "HasPartwordAtomics", "true",
 156                                              "Enable l[bh]arx and st[bh]cx.">;
 157 def FeatureInvariantFunctionDescriptors :
 158   SubtargetFeature<"invariant-function-descriptors",
 159                    "HasInvariantFunctionDescriptors", "true",
 160                    "Assume function descriptors are invariant">;
 161 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
 162                                        "Always use indirect calls">;
 163 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
 164                                   "Enable Hardware Transactional Memory instructions">;
 165 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
 166                                         "Implement mftb using the mfspr instruction">;
 167 def FeaturePPCPreRASched:
 168   SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
 169                    "Use PowerPC pre-RA scheduling strategy">;
 170 def FeaturePPCPostRASched:
 171   SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
 172                    "Use PowerPC post-RA scheduling strategy">;
 173 def FeatureFloat128 :
 174   SubtargetFeature<"float128", "HasFloat128", "true",
 175                    "Enable the __float128 data type for IEEE-754R Binary128.",
 176                    [FeatureVSX]>;
 177 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
 178                                         "POPCNTD_Fast",
 179                                         "Enable the popcnt[dw] instructions">;
 180 // Note that for the a2/a2q processor models we should not use popcnt[dw] by
 181 // default. These processors do support the instructions, but they're
 182 // microcoded, and the software emulation is about twice as fast.
 183 def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
 184                                           "POPCNTD_Slow",
 185                                           "Has slow popcnt[dw] instructions">;
 186
 187 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 188   "Treat vector data stream cache control instructions as deprecated">;
 189
 190 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
 191                                      "true",
 192                                      "Enable instructions added in ISA 3.0.">;
 193 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
 194                                         "Enable POWER9 Altivec instructions",
 195                                         [FeatureISA3_0, FeatureP8Altivec]>;
 196 def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
 197                                         "Enable POWER9 vector instructions",
 198                                         [FeatureISA3_0, FeatureP8Vector,
 199                                          FeatureP9Altivec]>;
 200 // A separate feature for this even though it is equivalent to P9Vector
 201 // because this is a feature of the implementation rather than the architecture
 202 // and may go away with future CPU's.
 203 def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
 204                                                  "VectorsUseTwoUnits",
 205                                                  "true",
 206                                                  "Vectors use two units">;
 207
 208 // Since new processors generally contain a superset of features of those that
 209 // came before them, the idea is to make implementations of new processors
 210 // less error prone and easier to read.
 211 // Namely:
 212 //     list<SubtargetFeature> Power8FeatureList = ...
 213 //     list<SubtargetFeature> FutureProcessorSpecificFeatureList =
 214 //         [ features that Power8 does not support ]
 215 //     list<SubtargetFeature> FutureProcessorFeatureList =
 216 //         !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
 217
 218 // Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
 219 // well as providing a single point of definition if the feature set will be
 220 // used elsewhere.
 221 def ProcessorFeatures {
 222   list<SubtargetFeature> Power7FeatureList =
 223       [DirectivePwr7, FeatureAltivec, FeatureVSX,
 224        FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 225        FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 226        FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 227        FeatureFPRND, FeatureFPCVT, FeatureISEL,
 228        FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
 229        Feature64Bit /*, Feature64BitRegs */,
 230        FeatureBPERMD, FeatureExtDiv,
 231        FeatureMFTB, DeprecatedDST, FeatureTwoConstNR];
 232   list<SubtargetFeature> Power8SpecificFeatures =
 233       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
 234        FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];
 235   list<SubtargetFeature> Power8FeatureList =
 236       !listconcat(Power7FeatureList, Power8SpecificFeatures);
 237   list<SubtargetFeature> Power9SpecificFeatures =
 238       [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0,
 239        FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
 240   list<SubtargetFeature> Power9FeatureList =
 241       !listconcat(Power8FeatureList, Power9SpecificFeatures);
 242 }
 243
 244 // Note: Future features to add when support is extended to more
 245 // recent ISA levels:
 246 //
 247 // DFP          p6, p6x, p7        decimal floating-point instructions
 248 // POPCNTB      p5 through p7      popcntb and related instructions
 249
 250 //===----------------------------------------------------------------------===//
 251 // Classes used for relation maps.
 252 //===----------------------------------------------------------------------===//
 253 // RecFormRel - Filter class used to relate non-record-form instructions with
 254 // their record-form variants.
 255 class RecFormRel;
 256
 257 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 258 // FMA instruction forms with their corresponding factor-killing forms.
 259 class AltVSXFMARel {
 260   bit IsVSXFMAAlt = 0;
 261 }
 262
 263 //===----------------------------------------------------------------------===//
 264 // Relation Map Definitions.
 265 //===----------------------------------------------------------------------===//
 266
 267 def getRecordFormOpcode : InstrMapping {
 268   let FilterClass = "RecFormRel";
 269   // Instructions with the same BaseName and Interpretation64Bit values
 270   // form a row.
 271   let RowFields = ["BaseName", "Interpretation64Bit"];
 272   // Instructions with the same RC value form a column.
 273   let ColFields = ["RC"];
 274   // The key column are the non-record-form instructions.
 275   let KeyCol = ["0"];
 276   // Value columns RC=1
 277   let ValueCols = [["1"]];
 278 }
 279
 280 def getNonRecordFormOpcode : InstrMapping {
 281   let FilterClass = "RecFormRel";
 282   // Instructions with the same BaseName and Interpretation64Bit values
 283   // form a row.
 284   let RowFields = ["BaseName", "Interpretation64Bit"];
 285   // Instructions with the same RC value form a column.
 286   let ColFields = ["RC"];
 287   // The key column are the record-form instructions.
 288   let KeyCol = ["1"];
 289   // Value columns are RC=0
 290   let ValueCols = [["0"]];
 291 }
 292
 293 def getAltVSXFMAOpcode : InstrMapping {
 294   let FilterClass = "AltVSXFMARel";
 295   // Instructions with the same BaseName value form a row.
 296   let RowFields = ["BaseName"];
 297   // Instructions with the same IsVSXFMAAlt value form a column.
 298   let ColFields = ["IsVSXFMAAlt"];
 299   // The key column are the (default) addend-killing instructions.
 300   let KeyCol = ["0"];
 301   // Value columns IsVSXFMAAlt=1
 302   let ValueCols = [["1"]];
 303 }
 304
 305 //===----------------------------------------------------------------------===//
 306 // Register File Description
 307 //===----------------------------------------------------------------------===//
 308
 309 include "PPCRegisterInfo.td"
 310 include "PPCSchedule.td"
 311
 312 //===----------------------------------------------------------------------===//
 313 // PowerPC processors supported.
 314 //
 315
 316 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
 317                                            FeatureMFTB]>;
 318 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 319                                           FeatureFRES, FeatureFRSQRTE,
 320                                           FeatureICBT, FeatureBookE,
 321                                           FeatureMSYNC, FeatureMFTB]>;
 322 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 323                                           FeatureFRES, FeatureFRSQRTE,
 324                                           FeatureICBT, FeatureBookE,
 325                                           FeatureMSYNC, FeatureMFTB]>;
 326 def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
 327 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
 328                                        FeatureMFTB]>;
 329 def : Processor<"603", G3Itineraries, [Directive603,
 330                                        FeatureFRES, FeatureFRSQRTE,
 331                                        FeatureMFTB]>;
 332 def : Processor<"603e", G3Itineraries, [Directive603,
 333                                         FeatureFRES, FeatureFRSQRTE,
 334                                         FeatureMFTB]>;
 335 def : Processor<"603ev", G3Itineraries, [Directive603,
 336                                          FeatureFRES, FeatureFRSQRTE,
 337                                          FeatureMFTB]>;
 338 def : Processor<"604", G3Itineraries, [Directive604,
 339                                        FeatureFRES, FeatureFRSQRTE,
 340                                        FeatureMFTB]>;
 341 def : Processor<"604e", G3Itineraries, [Directive604,
 342                                         FeatureFRES, FeatureFRSQRTE,
 343                                         FeatureMFTB]>;
 344 def : Processor<"620", G3Itineraries, [Directive620,
 345                                        FeatureFRES, FeatureFRSQRTE,
 346                                        FeatureMFTB]>;
 347 def : Processor<"750", G4Itineraries, [Directive750,
 348                                        FeatureFRES, FeatureFRSQRTE,
 349                                        FeatureMFTB]>;
 350 def : Processor<"g3", G3Itineraries, [Directive750,
 351                                       FeatureFRES, FeatureFRSQRTE,
 352                                       FeatureMFTB]>;
 353 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 354                                         FeatureFRES, FeatureFRSQRTE,
 355                                         FeatureMFTB]>;
 356 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 357                                       FeatureFRES, FeatureFRSQRTE,
 358                                       FeatureMFTB]>;
 359 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 360                                             FeatureFRES, FeatureFRSQRTE,
 361                                             FeatureMFTB]>;
 362 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 363                                            FeatureFRES, FeatureFRSQRTE,
 364                                            FeatureMFTB]>;
 365
 366 def : ProcessorModel<"970", G5Model,
 367                   [Directive970, FeatureAltivec,
 368                    FeatureMFOCRF, FeatureFSqrt,
 369                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 370                    Feature64Bit /*, Feature64BitRegs */,
 371                    FeatureMFTB]>;
 372 def : ProcessorModel<"g5", G5Model,
 373                   [Directive970, FeatureAltivec,
 374                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 375                    FeatureFRES, FeatureFRSQRTE,
 376                    Feature64Bit /*, Feature64BitRegs */,
 377                    FeatureMFTB, DeprecatedDST]>;
 378 def : ProcessorModel<"e500", PPCE500Model,
 379                   [DirectiveE500,
 380                    FeatureICBT, FeatureBookE,
 381                    FeatureISEL, FeatureMFTB]>;
 382 def : ProcessorModel<"e500mc", PPCE500mcModel,
 383                   [DirectiveE500mc,
 384                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 385                    FeatureISEL, FeatureMFTB]>;
 386 def : ProcessorModel<"e5500", PPCE5500Model,
 387                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 388                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 389                    FeatureISEL, FeatureMFTB]>;
 390 def : ProcessorModel<"a2", PPCA2Model,
 391                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 392                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 393                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 394                    FeatureSTFIWX, FeatureLFIWAX,
 395                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 396                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 397                    Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
 398 def : ProcessorModel<"a2q", PPCA2Model,
 399                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 400                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 401                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 402                    FeatureSTFIWX, FeatureLFIWAX,
 403                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 404                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 405                    Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
 406                    FeatureMFTB]>;
 407 def : ProcessorModel<"pwr3", G5Model,
 408                   [DirectivePwr3, FeatureAltivec,
 409                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 410                    FeatureSTFIWX, Feature64Bit]>;
 411 def : ProcessorModel<"pwr4", G5Model,
 412                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 413                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 414                    FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 415 def : ProcessorModel<"pwr5", G5Model,
 416                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 417                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 418                    FeatureFRSQRTE, FeatureFRSQRTES,
 419                    FeatureSTFIWX, Feature64Bit,
 420                    FeatureMFTB, DeprecatedDST]>;
 421 def : ProcessorModel<"pwr5x", G5Model,
 422                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 423                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 424                    FeatureFRSQRTE, FeatureFRSQRTES,
 425                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 426                    FeatureMFTB, DeprecatedDST]>;
 427 def : ProcessorModel<"pwr6", G5Model,
 428                   [DirectivePwr6, FeatureAltivec,
 429                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 430                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 431                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 432                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 433                    FeatureMFTB, DeprecatedDST]>;
 434 def : ProcessorModel<"pwr6x", G5Model,
 435                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 436                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 437                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 438                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 439                    FeatureFPRND, Feature64Bit,
 440                    FeatureMFTB, DeprecatedDST]>;
 441 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 442 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
 443 def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
 444 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
 445                                        FeatureMFTB]>;
 446 def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
 447                                          FeatureMFTB]>;
 448 def : ProcessorModel<"ppc64", G5Model,
 449                   [Directive64, FeatureAltivec,
 450                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 451                    FeatureFRSQRTE, FeatureSTFIWX,
 452                    Feature64Bit /*, Feature64BitRegs */,
 453                    FeatureMFTB]>;
 454 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
 455
 456 //===----------------------------------------------------------------------===//
 457 // Calling Conventions
 458 //===----------------------------------------------------------------------===//
 459
 460 include "PPCCallingConv.td"
 461
 462 def PPCInstrInfo : InstrInfo {
 463   let isLittleEndianEncoding = 1;
 464
 465   // FIXME: Unset this when no longer needed!
 466   let decodePositionallyEncodedOperands = 1;
 467
 468   let noNamedPositionallyEncodedOperands = 1;
 469 }
 470
 471 def PPCAsmParser : AsmParser {
 472   let ShouldEmitMatchRegisterName = 0;
 473 }
 474
 475 def PPCAsmParserVariant : AsmParserVariant {
 476   int Variant = 0;
 477
 478   // We do not use hard coded registers in asm strings.  However, some
 479   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 480   // so that those are not misinterpreted as registers.
 481   string RegisterPrefix = "%";
 482   string BreakCharacters = ".";
 483 }
 484
 485 def PPC : Target {
 486   // Information about the instructions.
 487   let InstructionSet = PPCInstrInfo;
 488
 489   let AssemblyParsers = [PPCAsmParser];
 490   let AssemblyParserVariants = [PPCAsmParserVariant];
 491   let AllowRegisterRenaming = 1;
 492 }
 493
 494 //===----------------------------------------------------------------------===//
 495 // Pfm Counters
 496 //===----------------------------------------------------------------------===//
 497
 498 include "PPCPfmCounters.td"