lib/Target/PowerPC/PPCISelLowering.h

   1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that PPC uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  16
  17 #include "PPCInstrInfo.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/MachineFunction.h"
  20 #include "llvm/CodeGen/MachineMemOperand.h"
  21 #include "llvm/CodeGen/SelectionDAG.h"
  22 #include "llvm/CodeGen/SelectionDAGNodes.h"
  23 #include "llvm/CodeGen/TargetLowering.h"
  24 #include "llvm/CodeGen/ValueTypes.h"
  25 #include "llvm/IR/Attributes.h"
  26 #include "llvm/IR/CallingConv.h"
  27 #include "llvm/IR/Function.h"
  28 #include "llvm/IR/InlineAsm.h"
  29 #include "llvm/IR/Metadata.h"
  30 #include "llvm/IR/Type.h"
  31 #include "llvm/Support/MachineValueType.h"
  32 #include <utility>
  33
  34 namespace llvm {
  35
  36   namespace PPCISD {
  37
  38     // When adding a NEW PPCISD node please add it to the correct position in
  39     // the enum. The order of elements in this enum matters!
  40     // Values that are added after this entry:
  41     //     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
  42     // are considered memory opcodes and are treated differently than entries
  43     // that come before it. For example, ADD or MUL should be placed before
  44     // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
  45     // after it.
  46     enum NodeType : unsigned {
  47       // Start the numbering where the builtin ops and target ops leave off.
  48       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  49
  50       /// FSEL - Traditional three-operand fsel node.
  51       ///
  52       FSEL,
  53
  54       /// FCFID - The FCFID instruction, taking an f64 operand and producing
  55       /// and f64 value containing the FP representation of the integer that
  56       /// was temporarily in the f64 operand.
  57       FCFID,
  58
  59       /// Newer FCFID[US] integer-to-floating-point conversion instructions for
  60       /// unsigned integers and single-precision outputs.
  61       FCFIDU, FCFIDS, FCFIDUS,
  62
  63       /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
  64       /// operand, producing an f64 value containing the integer representation
  65       /// of that FP value.
  66       FCTIDZ, FCTIWZ,
  67
  68       /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
  69       /// unsigned integers with round toward zero.
  70       FCTIDUZ, FCTIWUZ,
  71
  72       /// Floating-point-to-interger conversion instructions
  73       FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR,
  74
  75       /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
  76       /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
  77       VEXTS,
  78
  79       /// SExtVElems, takes an input vector of a smaller type and sign
  80       /// extends to an output vector of a larger type.
  81       SExtVElems,
  82
  83       /// Reciprocal estimate instructions (unary FP ops).
  84       FRE, FRSQRTE,
  85
  86       // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
  87       // three v4f32 operands and producing a v4f32 result.
  88       VMADDFP, VNMSUBFP,
  89
  90       /// VPERM - The PPC VPERM Instruction.
  91       ///
  92       VPERM,
  93
  94       /// XXSPLT - The PPC VSX splat instructions
  95       ///
  96       XXSPLT,
  97
  98       /// VECINSERT - The PPC vector insert instruction
  99       ///
 100       VECINSERT,
 101
 102       /// XXREVERSE - The PPC VSX reverse instruction
 103       ///
 104       XXREVERSE,
 105
 106       /// VECSHL - The PPC vector shift left instruction
 107       ///
 108       VECSHL,
 109
 110       /// XXPERMDI - The PPC XXPERMDI instruction
 111       ///
 112       XXPERMDI,
 113
 114       /// The CMPB instruction (takes two operands of i32 or i64).
 115       CMPB,
 116
 117       /// Hi/Lo - These represent the high and low 16-bit parts of a global
 118       /// address respectively.  These nodes have two operands, the first of
 119       /// which must be a TargetGlobalAddress, and the second of which must be a
 120       /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
 121       /// though these are usually folded into other nodes.
 122       Hi, Lo,
 123
 124       /// The following two target-specific nodes are used for calls through
 125       /// function pointers in the 64-bit SVR4 ABI.
 126
 127       /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
 128       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 129       /// compute an allocation on the stack.
 130       DYNALLOC,
 131
 132       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 133       /// compute an offset from native SP to the address  of the most recent
 134       /// dynamic alloca.
 135       DYNAREAOFFSET,
 136
 137       /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
 138       /// at function entry, used for PIC code.
 139       GlobalBaseReg,
 140
 141       /// These nodes represent PPC shifts.
 142       ///
 143       /// For scalar types, only the last `n + 1` bits of the shift amounts
 144       /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
 145       /// for exact behaviors.
 146       ///
 147       /// For vector types, only the last n bits are used. See vsld.
 148       SRL, SRA, SHL,
 149
 150       /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
 151       /// word and shift left immediate.
 152       EXTSWSLI,
 153
 154       /// The combination of sra[wd]i and addze used to implemented signed
 155       /// integer division by a power of 2. The first operand is the dividend,
 156       /// and the second is the constant shift amount (representing the
 157       /// divisor).
 158       SRA_ADDZE,
 159
 160       /// CALL - A direct function call.
 161       /// CALL_NOP is a call with the special NOP which follows 64-bit
 162       /// SVR4 calls and 32-bit/64-bit AIX calls.
 163       CALL, CALL_NOP,
 164
 165       /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
 166       /// MTCTR instruction.
 167       MTCTR,
 168
 169       /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
 170       /// BCTRL instruction.
 171       BCTRL,
 172
 173       /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
 174       /// instruction and the TOC reload required on SVR4 PPC64.
 175       BCTRL_LOAD_TOC,
 176
 177       /// Return with a flag operand, matched by 'blr'
 178       RET_FLAG,
 179
 180       /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
 181       /// This copies the bits corresponding to the specified CRREG into the
 182       /// resultant GPR.  Bits corresponding to other CR regs are undefined.
 183       MFOCRF,
 184
 185       /// Direct move from a VSX register to a GPR
 186       MFVSR,
 187
 188       /// Direct move from a GPR to a VSX register (algebraic)
 189       MTVSRA,
 190
 191       /// Direct move from a GPR to a VSX register (zero)
 192       MTVSRZ,
 193
 194       /// Direct move of 2 consecutive GPR to a VSX register.
 195       BUILD_FP128,
 196
 197       /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
 198       /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
 199       /// unsupported for this target.
 200       /// Merge 2 GPRs to a single SPE register.
 201       BUILD_SPE64,
 202
 203       /// Extract SPE register component, second argument is high or low.
 204       EXTRACT_SPE,
 205
 206       /// Extract a subvector from signed integer vector and convert to FP.
 207       /// It is primarily used to convert a (widened) illegal integer vector
 208       /// type to a legal floating point vector type.
 209       /// For example v2i32 -> widened to v4i32 -> v2f64
 210       SINT_VEC_TO_FP,
 211
 212       /// Extract a subvector from unsigned integer vector and convert to FP.
 213       /// As with SINT_VEC_TO_FP, used for converting illegal types.
 214       UINT_VEC_TO_FP,
 215
 216       // FIXME: Remove these once the ANDI glue bug is fixed:
 217       /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
 218       /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
 219       /// implement truncation of i32 or i64 to i1.
 220       ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
 221
 222       // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
 223       // target (returns (Lo, Hi)). It takes a chain operand.
 224       READ_TIME_BASE,
 225
 226       // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
 227       EH_SJLJ_SETJMP,
 228
 229       // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
 230       EH_SJLJ_LONGJMP,
 231
 232       /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
 233       /// instructions.  For lack of better number, we use the opcode number
 234       /// encoding for the OPC field to identify the compare.  For example, 838
 235       /// is VCMPGTSH.
 236       VCMP,
 237
 238       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
 239       /// altivec VCMP*o instructions.  For lack of better number, we use the
 240       /// opcode number encoding for the OPC field to identify the compare.  For
 241       /// example, 838 is VCMPGTSH.
 242       VCMPo,
 243
 244       /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
 245       /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
 246       /// condition register to branch on, OPC is the branch opcode to use (e.g.
 247       /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
 248       /// an optional input flag argument.
 249       COND_BRANCH,
 250
 251       /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
 252       /// loops.
 253       BDNZ, BDZ,
 254
 255       /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
 256       /// towards zero.  Used only as part of the long double-to-int
 257       /// conversion sequence.
 258       FADDRTZ,
 259
 260       /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
 261       MFFS,
 262
 263       /// TC_RETURN - A tail call return.
 264       ///   operand #0 chain
 265       ///   operand #1 callee (register or absolute)
 266       ///   operand #2 stack adjustment
 267       ///   operand #3 optional in flag
 268       TC_RETURN,
 269
 270       /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
 271       CR6SET,
 272       CR6UNSET,
 273
 274       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
 275       /// for non-position independent code on PPC32.
 276       PPC32_GOT,
 277
 278       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
 279       /// local dynamic TLS and position indendepent code on PPC32.
 280       PPC32_PICGOT,
 281
 282       /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
 283       /// TLS model, produces an ADDIS8 instruction that adds the GOT
 284       /// base to sym\@got\@tprel\@ha.
 285       ADDIS_GOT_TPREL_HA,
 286
 287       /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
 288       /// TLS model, produces a LD instruction with base register G8RReg
 289       /// and offset sym\@got\@tprel\@l.  This completes the addition that
 290       /// finds the offset of "sym" relative to the thread pointer.
 291       LD_GOT_TPREL_L,
 292
 293       /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
 294       /// model, produces an ADD instruction that adds the contents of
 295       /// G8RReg to the thread pointer.  Symbol contains a relocation
 296       /// sym\@tls which is to be replaced by the thread pointer and
 297       /// identifies to the linker that the instruction is part of a
 298       /// TLS sequence.
 299       ADD_TLS,
 300
 301       /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
 302       /// model, produces an ADDIS8 instruction that adds the GOT base
 303       /// register to sym\@got\@tlsgd\@ha.
 304       ADDIS_TLSGD_HA,
 305
 306       /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
 307       /// model, produces an ADDI8 instruction that adds G8RReg to
 308       /// sym\@got\@tlsgd\@l and stores the result in X3.  Hidden by
 309       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 310       ADDI_TLSGD_L,
 311
 312       /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
 313       /// model, produces a call to __tls_get_addr(sym\@tlsgd).  Hidden by
 314       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 315       GET_TLS_ADDR,
 316
 317       /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
 318       /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
 319       /// register assignment.
 320       ADDI_TLSGD_L_ADDR,
 321
 322       /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
 323       /// model, produces an ADDIS8 instruction that adds the GOT base
 324       /// register to sym\@got\@tlsld\@ha.
 325       ADDIS_TLSLD_HA,
 326
 327       /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
 328       /// model, produces an ADDI8 instruction that adds G8RReg to
 329       /// sym\@got\@tlsld\@l and stores the result in X3.  Hidden by
 330       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 331       ADDI_TLSLD_L,
 332
 333       /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
 334       /// model, produces a call to __tls_get_addr(sym\@tlsld).  Hidden by
 335       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 336       GET_TLSLD_ADDR,
 337
 338       /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
 339       /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
 340       /// following register assignment.
 341       ADDI_TLSLD_L_ADDR,
 342
 343       /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
 344       /// model, produces an ADDIS8 instruction that adds X3 to
 345       /// sym\@dtprel\@ha.
 346       ADDIS_DTPREL_HA,
 347
 348       /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
 349       /// model, produces an ADDI8 instruction that adds G8RReg to
 350       /// sym\@got\@dtprel\@l.
 351       ADDI_DTPREL_L,
 352
 353       /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
 354       /// during instruction selection to optimize a BUILD_VECTOR into
 355       /// operations on splats.  This is necessary to avoid losing these
 356       /// optimizations due to constant folding.
 357       VADD_SPLAT,
 358
 359       /// CHAIN = SC CHAIN, Imm128 - System call.  The 7-bit unsigned
 360       /// operand identifies the operating system entry point.
 361       SC,
 362
 363       /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
 364       CLRBHRB,
 365
 366       /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
 367       /// history rolling buffer entry.
 368       MFBHRBE,
 369
 370       /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
 371       RFEBB,
 372
 373       /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
 374       /// endian.  Maps to an xxswapd instruction that corrects an lxvd2x
 375       /// or stxvd2x instruction.  The chain is necessary because the
 376       /// sequence replaces a load and needs to provide the same number
 377       /// of outputs.
 378       XXSWAPD,
 379
 380       /// An SDNode for swaps that are not associated with any loads/stores
 381       /// and thereby have no chain.
 382       SWAP_NO_CHAIN,
 383
 384       /// An SDNode for Power9 vector absolute value difference.
 385       /// operand #0 vector
 386       /// operand #1 vector
 387       /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
 388       /// the most significant bit for signed i32
 389       ///
 390       /// Power9 VABSD* instructions are designed to support unsigned integer
 391       /// vectors (byte/halfword/word), if we want to make use of them for signed
 392       /// integer vectors, we have to flip their sign bits first. To flip sign bit
 393       /// for byte/halfword integer vector would become inefficient, but for word
 394       /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
 395       /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
 396       ///               => VABSDUW((XVNEGSP a), (XVNEGSP b))
 397       VABSD,
 398
 399       /// QVFPERM = This corresponds to the QPX qvfperm instruction.
 400       QVFPERM,
 401
 402       /// QVGPCI = This corresponds to the QPX qvgpci instruction.
 403       QVGPCI,
 404
 405       /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
 406       QVALIGNI,
 407
 408       /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
 409       QVESPLATI,
 410
 411       /// QBFLT = Access the underlying QPX floating-point boolean
 412       /// representation.
 413       QBFLT,
 414
 415       /// Custom extend v4f32 to v2f64.
 416       FP_EXTEND_LH,
 417
 418       /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
 419       /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
 420       /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
 421       /// i32.
 422       STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
 423
 424       /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
 425       /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
 426       /// then puts it in the bottom bits of the GPRC.  TYPE can be either i16
 427       /// or i32.
 428       LBRX,
 429
 430       /// STFIWX - The STFIWX instruction.  The first operand is an input token
 431       /// chain, then an f64 value to store, then an address to store it to.
 432       STFIWX,
 433
 434       /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
 435       /// load which sign-extends from a 32-bit integer value into the
 436       /// destination 64-bit register.
 437       LFIWAX,
 438
 439       /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
 440       /// load which zero-extends from a 32-bit integer value into the
 441       /// destination 64-bit register.
 442       LFIWZX,
 443
 444       /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
 445       /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
 446       /// This can be used for converting loaded integers to floating point.
 447       LXSIZX,
 448
 449       /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
 450       /// chain, then an f64 value to store, then an address to store it to,
 451       /// followed by a byte-width for the store.
 452       STXSIX,
 453
 454       /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
 455       /// Maps directly to an lxvd2x instruction that will be followed by
 456       /// an xxswapd.
 457       LXVD2X,
 458
 459       /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
 460       /// v2f32 value into the lower half of a VSR register.
 461       LD_VSX_LH,
 462
 463       /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
 464       /// Maps directly to an stxvd2x instruction that will be preceded by
 465       /// an xxswapd.
 466       STXVD2X,
 467
 468       /// Store scalar integers from VSR.
 469       ST_VSR_SCAL_INT,
 470
 471       /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
 472       /// The 4xf32 load used for v4i1 constants.
 473       QVLFSb,
 474
 475       /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
 476       /// except they ensure that the compare input is zero-extended for
 477       /// sub-word versions because the atomic loads zero-extend.
 478       ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
 479
 480       /// GPRC = TOC_ENTRY GA, TOC
 481       /// Loads the entry for GA from the TOC, where the TOC base is given by
 482       /// the last operand.
 483       TOC_ENTRY
 484     };
 485
 486   } // end namespace PPCISD
 487
 488   /// Define some predicates that are used for node matching.
 489   namespace PPC {
 490
 491     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
 492     /// VPKUHUM instruction.
 493     bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 494                               SelectionDAG &DAG);
 495
 496     /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
 497     /// VPKUWUM instruction.
 498     bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 499                               SelectionDAG &DAG);
 500
 501     /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
 502     /// VPKUDUM instruction.
 503     bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 504                               SelectionDAG &DAG);
 505
 506     /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
 507     /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
 508     bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 509                             unsigned ShuffleKind, SelectionDAG &DAG);
 510
 511     /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
 512     /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
 513     bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 514                             unsigned ShuffleKind, SelectionDAG &DAG);
 515
 516     /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
 517     /// a VMRGEW or VMRGOW instruction
 518     bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
 519                              unsigned ShuffleKind, SelectionDAG &DAG);
 520     /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
 521     /// for a XXSLDWI instruction.
 522     bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 523                               bool &Swap, bool IsLE);
 524
 525     /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
 526     /// for a XXBRH instruction.
 527     bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
 528
 529     /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
 530     /// for a XXBRW instruction.
 531     bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
 532
 533     /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
 534     /// for a XXBRD instruction.
 535     bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
 536
 537     /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
 538     /// for a XXBRQ instruction.
 539     bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
 540
 541     /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
 542     /// for a XXPERMDI instruction.
 543     bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 544                               bool &Swap, bool IsLE);
 545
 546     /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
 547     /// shift amount, otherwise return -1.
 548     int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
 549                             SelectionDAG &DAG);
 550
 551     /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
 552     /// specifies a splat of a single element that is suitable for input to
 553     /// VSPLTB/VSPLTH/VSPLTW.
 554     bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
 555
 556     /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
 557     /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
 558     /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
 559     /// vector into the other. This function will also set a couple of
 560     /// output parameters for how much the source vector needs to be shifted and
 561     /// what byte number needs to be specified for the instruction to put the
 562     /// element in the desired location of the target vector.
 563     bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 564                          unsigned &InsertAtByte, bool &Swap, bool IsLE);
 565
 566     /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
 567     /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
 568     unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
 569
 570     /// get_VSPLTI_elt - If this is a build_vector of constants which can be
 571     /// formed by using a vspltis[bhw] instruction of the specified element
 572     /// size, return the constant being splatted.  The ByteSize field indicates
 573     /// the number of bytes of each element [124] -> [bhw].
 574     SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
 575
 576     /// If this is a qvaligni shuffle mask, return the shift
 577     /// amount, otherwise return -1.
 578     int isQVALIGNIShuffleMask(SDNode *N);
 579
 580   } // end namespace PPC
 581
 582   class PPCTargetLowering : public TargetLowering {
 583     const PPCSubtarget &Subtarget;
 584
 585   public:
 586     explicit PPCTargetLowering(const PPCTargetMachine &TM,
 587                                const PPCSubtarget &STI);
 588
 589     /// getTargetNodeName() - This method returns the name of a target specific
 590     /// DAG node.
 591     const char *getTargetNodeName(unsigned Opcode) const override;
 592
 593     bool isSelectSupported(SelectSupportKind Kind) const override {
 594       // PowerPC does not support scalar condition selects on vectors.
 595       return (Kind != SelectSupportKind::ScalarCondVectorVal);
 596     }
 597
 598     /// getPreferredVectorAction - The code we generate when vector types are
 599     /// legalized by promoting the integer element type is often much worse
 600     /// than code we generate if we widen the type for applicable vector types.
 601     /// The issue with promoting is that the vector is scalaraized, individual
 602     /// elements promoted and then the vector is rebuilt. So say we load a pair
 603     /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
 604     /// loads, moves back into VSR's (or memory ops if we don't have moves) and
 605     /// then the VPERM for the shuffle. All in all a very slow sequence.
 606     TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
 607       const override {
 608       if (VT.getScalarSizeInBits() % 8 == 0)
 609         return TypeWidenVector;
 610       return TargetLoweringBase::getPreferredVectorAction(VT);
 611     }
 612
 613     bool useSoftFloat() const override;
 614
 615     bool hasSPE() const;
 616
 617     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
 618       return MVT::i32;
 619     }
 620
 621     bool isCheapToSpeculateCttz() const override {
 622       return true;
 623     }
 624
 625     bool isCheapToSpeculateCtlz() const override {
 626       return true;
 627     }
 628
 629     bool isCtlzFast() const override {
 630       return true;
 631     }
 632
 633     bool hasAndNotCompare(SDValue) const override {
 634       return true;
 635     }
 636
 637     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 638
 639     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 640       return VT.isScalarInteger();
 641     }
 642
 643     bool supportSplitCSR(MachineFunction *MF) const override {
 644       return
 645         MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 646         MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
 647     }
 648
 649     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 650
 651     void insertCopiesSplitCSR(
 652       MachineBasicBlock *Entry,
 653       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 654
 655     /// getSetCCResultType - Return the ISD::SETCC ValueType
 656     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 657                            EVT VT) const override;
 658
 659     /// Return true if target always beneficiates from combining into FMA for a
 660     /// given value type. This must typically return false on targets where FMA
 661     /// takes more cycles to execute than FADD.
 662     bool enableAggressiveFMAFusion(EVT VT) const override;
 663
 664     /// getPreIndexedAddressParts - returns true by value, base pointer and
 665     /// offset pointer and addressing mode by reference if the node's address
 666     /// can be legally represented as pre-indexed load / store address.
 667     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
 668                                    SDValue &Offset,
 669                                    ISD::MemIndexedMode &AM,
 670                                    SelectionDAG &DAG) const override;
 671
 672     /// SelectAddressRegReg - Given the specified addressed, check to see if it
 673     /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
 674     /// is non-zero, only accept displacement which is not suitable for [r+imm].
 675     /// Returns false if it can be represented by [r+imm], which are preferred.
 676     bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
 677                              SelectionDAG &DAG,
 678                              unsigned EncodingAlignment = 0) const;
 679
 680     /// SelectAddressRegImm - Returns true if the address N can be represented
 681     /// by a base register plus a signed 16-bit displacement [r+imm], and if it
 682     /// is not better represented as reg+reg. If \p EncodingAlignment is
 683     /// non-zero, only accept displacements suitable for instruction encoding
 684     /// requirement, i.e. multiples of 4 for DS form.
 685     bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
 686                              SelectionDAG &DAG,
 687                              unsigned EncodingAlignment) const;
 688
 689     /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
 690     /// represented as an indexed [r+r] operation.
 691     bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
 692                                  SelectionDAG &DAG) const;
 693
 694     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 695
 696     /// LowerOperation - Provide custom lowering hooks for some operations.
 697     ///
 698     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 699
 700     /// ReplaceNodeResults - Replace the results of node with an illegal result
 701     /// type with new values built out of custom code.
 702     ///
 703     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 704                             SelectionDAG &DAG) const override;
 705
 706     SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 707     SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 708
 709     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 710
 711     SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
 712                           SmallVectorImpl<SDNode *> &Created) const override;
 713
 714     unsigned getRegisterByName(const char* RegName, EVT VT,
 715                                SelectionDAG &DAG) const override;
 716
 717     void computeKnownBitsForTargetNode(const SDValue Op,
 718                                        KnownBits &Known,
 719                                        const APInt &DemandedElts,
 720                                        const SelectionDAG &DAG,
 721                                        unsigned Depth = 0) const override;
 722
 723     unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
 724
 725     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
 726       return true;
 727     }
 728
 729     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
 730                                   AtomicOrdering Ord) const override;
 731     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
 732                                    AtomicOrdering Ord) const override;
 733
 734     MachineBasicBlock *
 735     EmitInstrWithCustomInserter(MachineInstr &MI,
 736                                 MachineBasicBlock *MBB) const override;
 737     MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
 738                                         MachineBasicBlock *MBB,
 739                                         unsigned AtomicSize,
 740                                         unsigned BinOpcode,
 741                                         unsigned CmpOpcode = 0,
 742                                         unsigned CmpPred = 0) const;
 743     MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
 744                                                 MachineBasicBlock *MBB,
 745                                                 bool is8bit,
 746                                                 unsigned Opcode,
 747                                                 unsigned CmpOpcode = 0,
 748                                                 unsigned CmpPred = 0) const;
 749
 750     MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
 751                                         MachineBasicBlock *MBB) const;
 752
 753     MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
 754                                          MachineBasicBlock *MBB) const;
 755
 756     ConstraintType getConstraintType(StringRef Constraint) const override;
 757
 758     /// Examine constraint string and operand type and determine a weight value.
 759     /// The operand object must already have been set up with the operand type.
 760     ConstraintWeight getSingleConstraintMatchWeight(
 761       AsmOperandInfo &info, const char *constraint) const override;
 762
 763     std::pair<unsigned, const TargetRegisterClass *>
 764     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 765                                  StringRef Constraint, MVT VT) const override;
 766
 767     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
 768     /// function arguments in the caller parameter area.  This is the actual
 769     /// alignment, not its logarithm.
 770     unsigned getByValTypeAlignment(Type *Ty,
 771                                    const DataLayout &DL) const override;
 772
 773     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 774     /// vector.  If it is invalid, don't add anything to Ops.
 775     void LowerAsmOperandForConstraint(SDValue Op,
 776                                       std::string &Constraint,
 777                                       std::vector<SDValue> &Ops,
 778                                       SelectionDAG &DAG) const override;
 779
 780     unsigned
 781     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 782       if (ConstraintCode == "es")
 783         return InlineAsm::Constraint_es;
 784       else if (ConstraintCode == "o")
 785         return InlineAsm::Constraint_o;
 786       else if (ConstraintCode == "Q")
 787         return InlineAsm::Constraint_Q;
 788       else if (ConstraintCode == "Z")
 789         return InlineAsm::Constraint_Z;
 790       else if (ConstraintCode == "Zy")
 791         return InlineAsm::Constraint_Zy;
 792       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 793     }
 794
 795     /// isLegalAddressingMode - Return true if the addressing mode represented
 796     /// by AM is legal for this target, for a load/store of the specified type.
 797     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 798                                Type *Ty, unsigned AS,
 799                                Instruction *I = nullptr) const override;
 800
 801     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 802     /// icmp immediate, that is the target has icmp instructions which can
 803     /// compare a register against the immediate without having to materialize
 804     /// the immediate into a register.
 805     bool isLegalICmpImmediate(int64_t Imm) const override;
 806
 807     /// isLegalAddImmediate - Return true if the specified immediate is legal
 808     /// add immediate, that is the target has add instructions which can
 809     /// add a register and the immediate without having to materialize
 810     /// the immediate into a register.
 811     bool isLegalAddImmediate(int64_t Imm) const override;
 812
 813     /// isTruncateFree - Return true if it's free to truncate a value of
 814     /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
 815     /// register X1 to i32 by referencing its sub-register R1.
 816     bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
 817     bool isTruncateFree(EVT VT1, EVT VT2) const override;
 818
 819     bool isZExtFree(SDValue Val, EVT VT2) const override;
 820
 821     bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
 822
 823     /// Returns true if it is beneficial to convert a load of a constant
 824     /// to just the constant itself.
 825     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 826                                            Type *Ty) const override;
 827
 828     bool convertSelectOfConstantsToMath(EVT VT) const override {
 829       return true;
 830     }
 831
 832     // Returns true if the address of the global is stored in TOC entry.
 833     bool isAccessedAsGotIndirect(SDValue N) const;
 834
 835     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 836
 837     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
 838                             const CallInst &I,
 839                             MachineFunction &MF,
 840                             unsigned Intrinsic) const override;
 841
 842     /// getOptimalMemOpType - Returns the target specific optimal type for load
 843     /// and store operations as a result of memset, memcpy, and memmove
 844     /// lowering. If DstAlign is zero that means it's safe to destination
 845     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
 846     /// means there isn't a need to check it against alignment requirement,
 847     /// probably because the source does not need to be loaded. If 'IsMemset' is
 848     /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
 849     /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
 850     /// source is constant so it does not need to be loaded.
 851     /// It returns EVT::Other if the type should be determined using generic
 852     /// target-independent logic.
 853     EVT
 854     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
 855                         bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
 856                         const AttributeList &FuncAttributes) const override;
 857
 858     /// Is unaligned memory access allowed for the given type, and is it fast
 859     /// relative to software emulation.
 860     bool allowsMisalignedMemoryAccesses(
 861         EVT VT, unsigned AddrSpace, unsigned Align = 1,
 862         MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
 863         bool *Fast = nullptr) const override;
 864
 865     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
 866     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
 867     /// expanded to FMAs when this method returns true, otherwise fmuladd is
 868     /// expanded to fmul + fadd.
 869     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 870
 871     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 872
 873     // Should we expand the build vector with shuffles?
 874     bool
 875     shouldExpandBuildVectorWithShuffles(EVT VT,
 876                                         unsigned DefinedValues) const override;
 877
 878     /// createFastISel - This method returns a target-specific FastISel object,
 879     /// or null if the target does not support "fast" instruction selection.
 880     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
 881                              const TargetLibraryInfo *LibInfo) const override;
 882
 883     /// Returns true if an argument of type Ty needs to be passed in a
 884     /// contiguous block of registers in calling convention CallConv.
 885     bool functionArgumentNeedsConsecutiveRegisters(
 886       Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
 887       // We support any array type as "consecutive" block in the parameter
 888       // save area.  The element type defines the alignment requirement and
 889       // whether the argument should go in GPRs, FPRs, or VRs if available.
 890       //
 891       // Note that clang uses this capability both to implement the ELFv2
 892       // homogeneous float/vector aggregate ABI, and to avoid having to use
 893       // "byval" when passing aggregates that might fully fit in registers.
 894       return Ty->isArrayTy();
 895     }
 896
 897     /// If a physical register, this returns the register that receives the
 898     /// exception address on entry to an EH pad.
 899     unsigned
 900     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 901
 902     /// If a physical register, this returns the register that receives the
 903     /// exception typeid on entry to a landing pad.
 904     unsigned
 905     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 906
 907     /// Override to support customized stack guard loading.
 908     bool useLoadStackGuardNode() const override;
 909     void insertSSPDeclarations(Module &M) const override;
 910
 911     bool isFPImmLegal(const APFloat &Imm, EVT VT,
 912                       bool ForCodeSize) const override;
 913
 914     unsigned getJumpTableEncoding() const override;
 915     bool isJumpTableRelative() const override;
 916     SDValue getPICJumpTableRelocBase(SDValue Table,
 917                                      SelectionDAG &DAG) const override;
 918     const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
 919                                                unsigned JTI,
 920                                                MCContext &Ctx) const override;
 921
 922   private:
 923     struct ReuseLoadInfo {
 924       SDValue Ptr;
 925       SDValue Chain;
 926       SDValue ResChain;
 927       MachinePointerInfo MPI;
 928       bool IsDereferenceable = false;
 929       bool IsInvariant = false;
 930       unsigned Alignment = 0;
 931       AAMDNodes AAInfo;
 932       const MDNode *Ranges = nullptr;
 933
 934       ReuseLoadInfo() = default;
 935
 936       MachineMemOperand::Flags MMOFlags() const {
 937         MachineMemOperand::Flags F = MachineMemOperand::MONone;
 938         if (IsDereferenceable)
 939           F |= MachineMemOperand::MODereferenceable;
 940         if (IsInvariant)
 941           F |= MachineMemOperand::MOInvariant;
 942         return F;
 943       }
 944     };
 945
 946     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
 947       // Addrspacecasts are always noops.
 948       return true;
 949     }
 950
 951     bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
 952                              SelectionDAG &DAG,
 953                              ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
 954     void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
 955                          SelectionDAG &DAG) const;
 956
 957     void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
 958                                 SelectionDAG &DAG, const SDLoc &dl) const;
 959     SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
 960                                      const SDLoc &dl) const;
 961
 962     bool directMoveIsProfitable(const SDValue &Op) const;
 963     SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
 964                                      const SDLoc &dl) const;
 965
 966     SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
 967                                  const SDLoc &dl) const;
 968
 969     SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
 970
 971     SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
 972     SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
 973
 974     bool
 975     IsEligibleForTailCallOptimization(SDValue Callee,
 976                                       CallingConv::ID CalleeCC,
 977                                       bool isVarArg,
 978                                       const SmallVectorImpl<ISD::InputArg> &Ins,
 979                                       SelectionDAG& DAG) const;
 980
 981     bool
 982     IsEligibleForTailCallOptimization_64SVR4(
 983                                     SDValue Callee,
 984                                     CallingConv::ID CalleeCC,
 985                                     ImmutableCallSite CS,
 986                                     bool isVarArg,
 987                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 988                                     const SmallVectorImpl<ISD::InputArg> &Ins,
 989                                     SelectionDAG& DAG) const;
 990
 991     SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
 992                                          SDValue Chain, SDValue &LROpOut,
 993                                          SDValue &FPOpOut,
 994                                          const SDLoc &dl) const;
 995
 996     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 997     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 998     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 999     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1000     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1001     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1002     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1003     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1004     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1005     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1006     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1007     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1008     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1009     SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1010     SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1011     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1012     SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1013     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1014     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1015     SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1016     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1017     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1018                            const SDLoc &dl) const;
1019     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1020     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1021     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1022     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1023     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1024     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1025     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1026     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1027     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1028     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1029     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1030     SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
1031     SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1032     SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1033     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1034     SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
1035     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1036     SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1037     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1038
1039     SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1040     SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1041
1042     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1043                             CallingConv::ID CallConv, bool isVarArg,
1044                             const SmallVectorImpl<ISD::InputArg> &Ins,
1045                             const SDLoc &dl, SelectionDAG &DAG,
1046                             SmallVectorImpl<SDValue> &InVals) const;
1047     SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
1048                        bool isTailCall, bool isVarArg, bool isPatchPoint,
1049                        bool hasNest, SelectionDAG &DAG,
1050                        SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1051                        SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1052                        SDValue &Callee, int SPDiff, unsigned NumBytes,
1053                        const SmallVectorImpl<ISD::InputArg> &Ins,
1054                        SmallVectorImpl<SDValue> &InVals,
1055                        ImmutableCallSite CS) const;
1056
1057     SDValue
1058     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1059                          const SmallVectorImpl<ISD::InputArg> &Ins,
1060                          const SDLoc &dl, SelectionDAG &DAG,
1061                          SmallVectorImpl<SDValue> &InVals) const override;
1062
1063     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1064                       SmallVectorImpl<SDValue> &InVals) const override;
1065
1066     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1067                         bool isVarArg,
1068                         const SmallVectorImpl<ISD::OutputArg> &Outs,
1069                         LLVMContext &Context) const override;
1070
1071     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1072                         const SmallVectorImpl<ISD::OutputArg> &Outs,
1073                         const SmallVectorImpl<SDValue> &OutVals,
1074                         const SDLoc &dl, SelectionDAG &DAG) const override;
1075
1076     SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1077                               SelectionDAG &DAG, SDValue ArgVal,
1078                               const SDLoc &dl) const;
1079
1080     SDValue LowerFormalArguments_Darwin(
1081         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1082         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1083         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1084     SDValue LowerFormalArguments_64SVR4(
1085         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1086         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1087         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1088     SDValue LowerFormalArguments_32SVR4(
1089         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1090         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1091         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1092
1093     SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1094                                        SDValue CallSeqStart,
1095                                        ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1096                                        const SDLoc &dl) const;
1097
1098     SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
1099                              CallingConv::ID CallConv, bool isVarArg,
1100                              bool isTailCall, bool isPatchPoint,
1101                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1102                              const SmallVectorImpl<SDValue> &OutVals,
1103                              const SmallVectorImpl<ISD::InputArg> &Ins,
1104                              const SDLoc &dl, SelectionDAG &DAG,
1105                              SmallVectorImpl<SDValue> &InVals,
1106                              ImmutableCallSite CS) const;
1107     SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
1108                              CallingConv::ID CallConv, bool isVarArg,
1109                              bool isTailCall, bool isPatchPoint,
1110                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1111                              const SmallVectorImpl<SDValue> &OutVals,
1112                              const SmallVectorImpl<ISD::InputArg> &Ins,
1113                              const SDLoc &dl, SelectionDAG &DAG,
1114                              SmallVectorImpl<SDValue> &InVals,
1115                              ImmutableCallSite CS) const;
1116     SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
1117                              CallingConv::ID CallConv, bool isVarArg,
1118                              bool isTailCall, bool isPatchPoint,
1119                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1120                              const SmallVectorImpl<SDValue> &OutVals,
1121                              const SmallVectorImpl<ISD::InputArg> &Ins,
1122                              const SDLoc &dl, SelectionDAG &DAG,
1123                              SmallVectorImpl<SDValue> &InVals,
1124                              ImmutableCallSite CS) const;
1125     SDValue LowerCall_AIX(SDValue Chain, SDValue Callee,
1126                           CallingConv::ID CallConv, bool isVarArg,
1127                           bool isTailCall, bool isPatchPoint,
1128                           const SmallVectorImpl<ISD::OutputArg> &Outs,
1129                           const SmallVectorImpl<SDValue> &OutVals,
1130                           const SmallVectorImpl<ISD::InputArg> &Ins,
1131                           const SDLoc &dl, SelectionDAG &DAG,
1132                           SmallVectorImpl<SDValue> &InVals,
1133                           ImmutableCallSite CS) const;
1134
1135     SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1136     SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1137     SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1138
1139     SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1140     SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1141     SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1142     SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1143     SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1144     SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1145     SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1146     SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1147     SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1148     SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1149     SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1150     SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1151     SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1152     SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1153
1154     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1155     /// SETCC with integer subtraction when (1) there is a legal way of doing it
1156     /// (2) keeping the result of comparison in GPR has performance benefit.
1157     SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1158
1159     SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1160                             int &RefinementSteps, bool &UseOneConstNR,
1161                             bool Reciprocal) const override;
1162     SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1163                              int &RefinementSteps) const override;
1164     unsigned combineRepeatedFPDivisors() const override;
1165
1166     SDValue
1167     combineElementTruncationToVectorTruncation(SDNode *N,
1168                                                DAGCombinerInfo &DCI) const;
1169
1170     /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1171     /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1172     /// essentially any shuffle of v8i16 vectors that just inserts one element
1173     /// from one vector into the other.
1174     SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1175
1176     /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1177     /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1178     /// essentially v16i8 vector version of VINSERTH.
1179     SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1180
1181     // Return whether the call instruction can potentially be optimized to a
1182     // tail call. This will cause the optimizers to attempt to move, or
1183     // duplicate return instructions to help enable tail call optimizations.
1184     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1185     bool hasBitPreservingFPLogic(EVT VT) const override;
1186     bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1187   }; // end class PPCTargetLowering
1188
1189   namespace PPC {
1190
1191     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1192                              const TargetLibraryInfo *LibInfo);
1193
1194   } // end namespace PPC
1195
1196   bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1197   bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1198
1199 } // end namespace llvm
1200
1201 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H