[ARM] MVE integer min and max
[llvm-complete.git] / lib / Target / WebAssembly / WebAssemblyTargetTransformInfo.cpp
blob46ef765ce0f4b382d91b3d3237a372daad4c5741
1 //===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific TargetTransformInfo
11 /// implementation.
12 ///
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyTargetTransformInfo.h"
16 #include "llvm/CodeGen/CostTable.h"
17 #include "llvm/Support/Debug.h"
18 using namespace llvm;
20 #define DEBUG_TYPE "wasmtti"
22 TargetTransformInfo::PopcntSupportKind
23 WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
24 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
25 return TargetTransformInfo::PSK_FastHardware;
28 unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) {
29 unsigned Result = BaseT::getNumberOfRegisters(Vector);
31 // For SIMD, use at least 16 registers, as a rough guess.
32 if (Vector)
33 Result = std::max(Result, 16u);
35 return Result;
38 unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
39 if (Vector && getST()->hasSIMD128())
40 return 128;
42 return 64;
45 unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
46 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
47 TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
48 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
50 unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
51 Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
53 if (auto *VTy = dyn_cast<VectorType>(Ty)) {
54 switch (Opcode) {
55 case Instruction::LShr:
56 case Instruction::AShr:
57 case Instruction::Shl:
58 // SIMD128's shifts currently only accept a scalar shift count. For each
59 // element, we'll need to extract, op, insert. The following is a rough
60 // approxmation.
61 if (Opd2Info != TTI::OK_UniformValue &&
62 Opd2Info != TTI::OK_UniformConstantValue)
63 Cost = VTy->getNumElements() *
64 (TargetTransformInfo::TCC_Basic +
65 getArithmeticInstrCost(Opcode, VTy->getElementType()) +
66 TargetTransformInfo::TCC_Basic);
67 break;
70 return Cost;
73 unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
74 unsigned Index) {
75 unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
77 // SIMD128's insert/extract currently only take constant indices.
78 if (Index == -1u)
79 return Cost + 25 * TargetTransformInfo::TCC_Expensive;
81 return Cost;