lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h

   1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file provides X86 specific target descriptions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
  14 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
  15
  16 #include "llvm/MC/MCStreamer.h"
  17 #include "llvm/Support/DataTypes.h"
  18 #include <string>
  19
  20 namespace llvm {
  21 class MCAsmBackend;
  22 class MCCodeEmitter;
  23 class MCContext;
  24 class MCInstrInfo;
  25 class MCObjectTargetWriter;
  26 class MCObjectWriter;
  27 class MCRegisterInfo;
  28 class MCSubtargetInfo;
  29 class MCRelocationInfo;
  30 class MCTargetOptions;
  31 class Target;
  32 class Triple;
  33 class StringRef;
  34 class raw_ostream;
  35 class raw_pwrite_stream;
  36
  37 /// Flavour of dwarf regnumbers
  38 ///
  39 namespace DWARFFlavour {
  40   enum {
  41     X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
  42   };
  43 }
  44
  45 ///  Native X86 register numbers
  46 ///
  47 namespace N86 {
  48   enum {
  49     EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
  50   };
  51 }
  52
  53 namespace X86_MC {
  54 std::string ParseX86Triple(const Triple &TT);
  55
  56 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
  57
  58 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI);
  59
  60 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
  61 /// do not need to go through TargetRegistry.
  62 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
  63                                           StringRef FS);
  64 }
  65
  66 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
  67                                       const MCRegisterInfo &MRI,
  68                                       MCContext &Ctx);
  69
  70 MCAsmBackend *createX86_32AsmBackend(const Target &T,
  71                                      const MCSubtargetInfo &STI,
  72                                      const MCRegisterInfo &MRI,
  73                                      const MCTargetOptions &Options);
  74 MCAsmBackend *createX86_64AsmBackend(const Target &T,
  75                                      const MCSubtargetInfo &STI,
  76                                      const MCRegisterInfo &MRI,
  77                                      const MCTargetOptions &Options);
  78
  79 /// Implements X86-only directives for assembly emission.
  80 MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S,
  81                                              formatted_raw_ostream &OS,
  82                                              MCInstPrinter *InstPrint,
  83                                              bool isVerboseAsm);
  84
  85 /// Implements X86-only directives for object files.
  86 MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &OS,
  87                                                 const MCSubtargetInfo &STI);
  88
  89 /// Construct an X86 Windows COFF machine code streamer which will generate
  90 /// PE/COFF format object files.
  91 ///
  92 /// Takes ownership of \p AB and \p CE.
  93 MCStreamer *createX86WinCOFFStreamer(MCContext &C,
  94                                      std::unique_ptr<MCAsmBackend> &&AB,
  95                                      std::unique_ptr<MCObjectWriter> &&OW,
  96                                      std::unique_ptr<MCCodeEmitter> &&CE,
  97                                      bool RelaxAll,
  98                                      bool IncrementalLinkerCompatible);
  99
 100 /// Construct an X86 Mach-O object writer.
 101 std::unique_ptr<MCObjectTargetWriter>
 102 createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
 103
 104 /// Construct an X86 ELF object writer.
 105 std::unique_ptr<MCObjectTargetWriter>
 106 createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine);
 107 /// Construct an X86 Win COFF object writer.
 108 std::unique_ptr<MCObjectTargetWriter>
 109 createX86WinCOFFObjectWriter(bool Is64Bit);
 110
 111 /// Returns the sub or super register of a specific X86 register.
 112 /// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
 113 /// Aborts on error.
 114 unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false);
 115
 116 /// Returns the sub or super register of a specific X86 register.
 117 /// Like getX86SubSuperRegister() but returns 0 on error.
 118 unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned,
 119                                       bool High = false);
 120
 121 } // End llvm namespace
 122
 123
 124 // Defines symbolic names for X86 registers.  This defines a mapping from
 125 // register name to register number.
 126 //
 127 #define GET_REGINFO_ENUM
 128 #include "X86GenRegisterInfo.inc"
 129
 130 // Defines symbolic names for the X86 instructions.
 131 //
 132 #define GET_INSTRINFO_ENUM
 133 #define GET_INSTRINFO_MC_HELPER_DECLS
 134 #include "X86GenInstrInfo.inc"
 135
 136 #define GET_SUBTARGETINFO_ENUM
 137 #include "X86GenSubtargetInfo.inc"
 138
 139 #endif