| commit | 7adf960acfc4b646749ae904227f1159d71ce263 | |
| author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | |
| Thu, 24 Jan 2019 10:27:21 +0000 (24 10:27 +0000) | ||
| committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | |
| Thu, 24 Jan 2019 10:27:21 +0000 (24 10:27 +0000) | ||
| tree | 55c5ff45480cad27ead3f4228b1875e5e15801f1 | treesnapshot (tar.gz zip) |
| parent | 2e46a962e82297f2966c813c282d0c7ae7566792 | commitdiff |
[MIPS GlobalISel] Select zero extending and sign extending load
Select zero extending and sign extending load for MIPS32.
Use size from MachineMemOperand to determine number of bytes to load.
Differential Revision: https://reviews.llvm.org/D57099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352038 91177308-0d34-0410-b5e6-96231b3b80d8
Select zero extending and sign extending load for MIPS32.
Use size from MachineMemOperand to determine number of bytes to load.
Differential Revision: https://reviews.llvm.org/D57099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352038 91177308-0d34-0410-b5e6-96231b3b80d8
| lib/Target/Mips/MipsInstructionSelector.cpp | diffblobblamehistory | |
| lib/Target/Mips/MipsLegalizerInfo.cpp | diffblobblamehistory | |
| lib/Target/Mips/MipsRegisterBankInfo.cpp | diffblobblamehistory | |
| test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir | [new file with mode: 0644] | blob |
| test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir | [new file with mode: 0644] | blob |
| test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll | [new file with mode: 0644] | blob |
| test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir | [new file with mode: 0644] | blob |