| commit | 98cc6ec20506ef49d49952ae2a5ab1c4ecd8282a | |
| author | David Green <david.green@arm.com> | |
| Sat, 13 Jul 2019 15:43:00 +0000 (13 15:43 +0000) | ||
| committer | David Green <david.green@arm.com> | |
| Sat, 13 Jul 2019 15:43:00 +0000 (13 15:43 +0000) | ||
| tree | 31ff2c4f5c4eaf6f842d808bba21452836a20c85 | treesnapshot (tar.gz zip) |
| parent | dacf15e29c498aafc996c95f83b87a672fd0562e | commitdiff |
[ARM] Add sign and zero extend patterns for MVE
The vmovlb instructions can be uses to sign or zero extend vector registers
between types. This adds some patterns for them and relevant testing. The
VBICIMM generation is also put behind a hasNEON check (as is already done for
VORRIMM).
Code originally by David Sherwood.
Differential Revision: https://reviews.llvm.org/D64069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366008 91177308-0d34-0410-b5e6-96231b3b80d8
The vmovlb instructions can be uses to sign or zero extend vector registers
between types. This adds some patterns for them and relevant testing. The
VBICIMM generation is also put behind a hasNEON check (as is already done for
VORRIMM).
Code originally by David Sherwood.
Differential Revision: https://reviews.llvm.org/D64069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366008 91177308-0d34-0410-b5e6-96231b3b80d8
| lib/Target/ARM/ARMISelLowering.cpp | diffblobblamehistory | |
| lib/Target/ARM/ARMInstrMVE.td | diffblobblamehistory | |
| test/CodeGen/Thumb2/mve-sext.ll | [new file with mode: 0644] | blob |