[MIPS GlobalISel] Select MSA vector generic and builtin add
commitceef272d87d584993012ef8e7f321664f3a7aecb
authorPetar Avramovic <Petar.Avramovic@rt-rk.com>
Tue, 22 Oct 2019 13:51:57 +0000 (22 13:51 +0000)
committerPetar Avramovic <Petar.Avramovic@rt-rk.com>
Tue, 22 Oct 2019 13:51:57 +0000 (22 13:51 +0000)
treeb8303681706acf70021efcdd4031e2d292315541
parent9bea9fd3d8755d57505986afe349d2e777456e1a
[MIPS GlobalISel] Select MSA vector generic and builtin add

Select vector G_ADD for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
__builtin_msa_addv_<format> will be transformed into G_ADD
in legalizeIntrinsic and selected in the same way.
__builtin_msa_addvi_<format> will be directly selected into
ADDVI_<format> in legalizeIntrinsic. MIR tests for it have
unnecessary additional copies. Capture current state of tests
with run-pass=legalizer with a test in test/CodeGen/MIR/Mips.

Differential Revision: https://reviews.llvm.org/D68984

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375501 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MipsLegalizerInfo.cpp
lib/Target/Mips/MipsRegisterBankInfo.cpp
test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll [new file with mode: 0644]
test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir [new file with mode: 0644]