| commit | df97452aedd36c390637713adefcd0880e514b47 | |
| author | Craig Topper <craig.topper@intel.com> | |
| Fri, 31 May 2019 07:38:26 +0000 (31 07:38 +0000) | ||
| committer | Craig Topper <craig.topper@intel.com> | |
| Fri, 31 May 2019 07:38:26 +0000 (31 07:38 +0000) | ||
| tree | f6ee29b65cda91010cd3f3c0ae40babc10693779 | treesnapshot (tar.gz zip) |
| parent | e7fb3032fe540d701e6e218d5f257abc8ebd2a9d | commitdiff |
[X86] Remove patterns for X86VSintToFP/X86VUintToFP+loadv4f32 to v2f64.
These patterns can incorrectly narrow a volatile load from 128-bits to 64-bits.
Similar to PR42079.
Switch to using (v4i32 (bitcast (v2i64 (scalar_to_vector (loadi64))))) as the
load pattern used in the instructions.
This probably still has issues in 32-bit mode where loadi64 isn't legal. Maybe
we should use VZMOVL for widened loads even when we don't need the upper bits
as zeroes?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362203 91177308-0d34-0410-b5e6-96231b3b80d8
These patterns can incorrectly narrow a volatile load from 128-bits to 64-bits.
Similar to PR42079.
Switch to using (v4i32 (bitcast (v2i64 (scalar_to_vector (loadi64))))) as the
load pattern used in the instructions.
This probably still has issues in 32-bit mode where loadi64 isn't legal. Maybe
we should use VZMOVL for widened loads even when we don't need the upper bits
as zeroes?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362203 91177308-0d34-0410-b5e6-96231b3b80d8