[ARM] Tighten up VLDRH.32 with low alignments
commite75e8a8ed8da8b30474f58066c3b79030d85017b
authorDavid Green <david.green@arm.com>
Thu, 8 Aug 2019 06:22:03 +0000 (8 06:22 +0000)
committerDavid Green <david.green@arm.com>
Thu, 8 Aug 2019 06:22:03 +0000 (8 06:22 +0000)
tree4999ede1f6dd5fa54b3b40d81bab01df54ade2b6
parent6adbd0b0e6c0e028afdd038a4b65ae29143bf0ab
[ARM] Tighten up VLDRH.32 with low alignments

VLDRH needs to have an alignment of at least 2, including the
widening/narrowing versions. This tightens up the ISel patterns for it and
alters allowsMisalignedMemoryAccesses so that unaligned accesses are expanded
through the stack. It also fixed some incorrect shift amounts, which seemed to
be passing a multiple not a shift.

Differential Revision: https://reviews.llvm.org/D65580

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368256 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMInstrMVE.td
test/CodeGen/Thumb2/mve-ldst-offset.ll
test/CodeGen/Thumb2/mve-ldst-postinc.ll
test/CodeGen/Thumb2/mve-ldst-preinc.ll
test/CodeGen/Thumb2/mve-widen-narrow.ll