| blob | 387850c831ff8ff62bd15d0b86d233b84b433d74 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
7 declare i4 @llvm.sadd.sat.i4(i4, i4)
8 declare i8 @llvm.sadd.sat.i8(i8, i8)
9 declare i16 @llvm.sadd.sat.i16(i16, i16)
10 declare i32 @llvm.sadd.sat.i32(i32, i32)
11 declare i64 @llvm.sadd.sat.i64(i64, i64)
13 define i32 @func(i32 %x, i32 %y) nounwind {
14 ; CHECK-T1-LABEL: func:
15 ; CHECK-T1: @ %bb.0:
16 ; CHECK-T1-NEXT: mov r2, r0
17 ; CHECK-T1-NEXT: movs r3, #1
18 ; CHECK-T1-NEXT: adds r0, r0, r1
19 ; CHECK-T1-NEXT: mov r1, r3
20 ; CHECK-T1-NEXT: bmi .LBB0_2
21 ; CHECK-T1-NEXT: @ %bb.1:
22 ; CHECK-T1-NEXT: movs r1, #0
23 ; CHECK-T1-NEXT: .LBB0_2:
24 ; CHECK-T1-NEXT: cmp r1, #0
25 ; CHECK-T1-NEXT: bne .LBB0_4
26 ; CHECK-T1-NEXT: @ %bb.3:
27 ; CHECK-T1-NEXT: lsls r1, r3, #31
28 ; CHECK-T1-NEXT: cmp r0, r2
29 ; CHECK-T1-NEXT: bvs .LBB0_5
30 ; CHECK-T1-NEXT: b .LBB0_6
31 ; CHECK-T1-NEXT: .LBB0_4:
32 ; CHECK-T1-NEXT: ldr r1, .LCPI0_0
33 ; CHECK-T1-NEXT: cmp r0, r2
34 ; CHECK-T1-NEXT: bvc .LBB0_6
35 ; CHECK-T1-NEXT: .LBB0_5:
36 ; CHECK-T1-NEXT: mov r0, r1
37 ; CHECK-T1-NEXT: .LBB0_6:
38 ; CHECK-T1-NEXT: bx lr
39 ; CHECK-T1-NEXT: .p2align 2
40 ; CHECK-T1-NEXT: @ %bb.7:
41 ; CHECK-T1-NEXT: .LCPI0_0:
42 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
43 ;
44 ; CHECK-T2-LABEL: func:
45 ; CHECK-T2: @ %bb.0:
46 ; CHECK-T2-NEXT: adds r2, r0, r1
47 ; CHECK-T2-NEXT: mov.w r3, #0
48 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
49 ; CHECK-T2-NEXT: it mi
50 ; CHECK-T2-NEXT: movmi r3, #1
51 ; CHECK-T2-NEXT: cmp r3, #0
52 ; CHECK-T2-NEXT: it ne
53 ; CHECK-T2-NEXT: mvnne r1, #-2147483648
54 ; CHECK-T2-NEXT: cmp r2, r0
55 ; CHECK-T2-NEXT: it vc
56 ; CHECK-T2-NEXT: movvc r1, r2
57 ; CHECK-T2-NEXT: mov r0, r1
58 ; CHECK-T2-NEXT: bx lr
59 ;
60 ; CHECK-ARM-LABEL: func:
61 ; CHECK-ARM: @ %bb.0:
62 ; CHECK-ARM-NEXT: adds r2, r0, r1
63 ; CHECK-ARM-NEXT: mov r3, #0
64 ; CHECK-ARM-NEXT: movwmi r3, #1
65 ; CHECK-ARM-NEXT: mov r1, #-2147483648
66 ; CHECK-ARM-NEXT: cmp r3, #0
67 ; CHECK-ARM-NEXT: mvnne r1, #-2147483648
68 ; CHECK-ARM-NEXT: cmp r2, r0
69 ; CHECK-ARM-NEXT: movvc r1, r2
70 ; CHECK-ARM-NEXT: mov r0, r1
71 ; CHECK-ARM-NEXT: bx lr
72 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
73 ret i32 %tmp
74 }
76 define i64 @func2(i64 %x, i64 %y) nounwind {
77 ; CHECK-T1-LABEL: func2:
78 ; CHECK-T1: @ %bb.0:
79 ; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
80 ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
81 ; CHECK-T1-NEXT: .pad #4
82 ; CHECK-T1-NEXT: sub sp, #4
83 ; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
84 ; CHECK-T1-NEXT: mov r2, r0
85 ; CHECK-T1-NEXT: movs r4, #1
86 ; CHECK-T1-NEXT: movs r0, #0
87 ; CHECK-T1-NEXT: cmp r3, #0
88 ; CHECK-T1-NEXT: mov r5, r4
89 ; CHECK-T1-NEXT: bge .LBB1_2
90 ; CHECK-T1-NEXT: @ %bb.1:
91 ; CHECK-T1-NEXT: mov r5, r0
92 ; CHECK-T1-NEXT: .LBB1_2:
93 ; CHECK-T1-NEXT: cmp r1, #0
94 ; CHECK-T1-NEXT: mov r7, r4
95 ; CHECK-T1-NEXT: bge .LBB1_4
96 ; CHECK-T1-NEXT: @ %bb.3:
97 ; CHECK-T1-NEXT: mov r7, r0
98 ; CHECK-T1-NEXT: .LBB1_4:
99 ; CHECK-T1-NEXT: subs r6, r7, r5
100 ; CHECK-T1-NEXT: rsbs r5, r6, #0
101 ; CHECK-T1-NEXT: adcs r5, r6
102 ; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
103 ; CHECK-T1-NEXT: adds r6, r2, r6
104 ; CHECK-T1-NEXT: adcs r1, r3
105 ; CHECK-T1-NEXT: cmp r1, #0
106 ; CHECK-T1-NEXT: mov r2, r4
107 ; CHECK-T1-NEXT: bge .LBB1_6
108 ; CHECK-T1-NEXT: @ %bb.5:
109 ; CHECK-T1-NEXT: mov r2, r0
110 ; CHECK-T1-NEXT: .LBB1_6:
111 ; CHECK-T1-NEXT: subs r0, r7, r2
112 ; CHECK-T1-NEXT: subs r2, r0, #1
113 ; CHECK-T1-NEXT: sbcs r0, r2
114 ; CHECK-T1-NEXT: ands r5, r0
115 ; CHECK-T1-NEXT: beq .LBB1_8
116 ; CHECK-T1-NEXT: @ %bb.7:
117 ; CHECK-T1-NEXT: asrs r6, r1, #31
118 ; CHECK-T1-NEXT: .LBB1_8:
119 ; CHECK-T1-NEXT: cmp r1, #0
120 ; CHECK-T1-NEXT: bmi .LBB1_10
121 ; CHECK-T1-NEXT: @ %bb.9:
122 ; CHECK-T1-NEXT: lsls r2, r4, #31
123 ; CHECK-T1-NEXT: cmp r5, #0
124 ; CHECK-T1-NEXT: beq .LBB1_11
125 ; CHECK-T1-NEXT: b .LBB1_12
126 ; CHECK-T1-NEXT: .LBB1_10:
127 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
128 ; CHECK-T1-NEXT: cmp r5, #0
129 ; CHECK-T1-NEXT: bne .LBB1_12
130 ; CHECK-T1-NEXT: .LBB1_11:
131 ; CHECK-T1-NEXT: mov r2, r1
132 ; CHECK-T1-NEXT: .LBB1_12:
133 ; CHECK-T1-NEXT: mov r0, r6
134 ; CHECK-T1-NEXT: mov r1, r2
135 ; CHECK-T1-NEXT: add sp, #4
136 ; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
137 ; CHECK-T1-NEXT: .p2align 2
138 ; CHECK-T1-NEXT: @ %bb.13:
139 ; CHECK-T1-NEXT: .LCPI1_0:
140 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
141 ;
142 ; CHECK-T2-LABEL: func2:
143 ; CHECK-T2: @ %bb.0:
144 ; CHECK-T2-NEXT: .save {r7, lr}
145 ; CHECK-T2-NEXT: push {r7, lr}
146 ; CHECK-T2-NEXT: cmp.w r1, #-1
147 ; CHECK-T2-NEXT: mov.w lr, #0
148 ; CHECK-T2-NEXT: it gt
149 ; CHECK-T2-NEXT: movgt.w lr, #1
150 ; CHECK-T2-NEXT: adds r0, r0, r2
151 ; CHECK-T2-NEXT: adc.w r2, r1, r3
152 ; CHECK-T2-NEXT: movs r1, #0
153 ; CHECK-T2-NEXT: cmp.w r2, #-1
154 ; CHECK-T2-NEXT: it gt
155 ; CHECK-T2-NEXT: movgt r1, #1
156 ; CHECK-T2-NEXT: subs.w r1, lr, r1
157 ; CHECK-T2-NEXT: mov.w r12, #0
158 ; CHECK-T2-NEXT: it ne
159 ; CHECK-T2-NEXT: movne r1, #1
160 ; CHECK-T2-NEXT: cmp.w r3, #-1
161 ; CHECK-T2-NEXT: it gt
162 ; CHECK-T2-NEXT: movgt.w r12, #1
163 ; CHECK-T2-NEXT: sub.w r3, lr, r12
164 ; CHECK-T2-NEXT: clz r3, r3
165 ; CHECK-T2-NEXT: lsrs r3, r3, #5
166 ; CHECK-T2-NEXT: ands r3, r1
167 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
168 ; CHECK-T2-NEXT: it ne
169 ; CHECK-T2-NEXT: asrne r0, r2, #31
170 ; CHECK-T2-NEXT: cmp r2, #0
171 ; CHECK-T2-NEXT: it mi
172 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
173 ; CHECK-T2-NEXT: cmp r3, #0
174 ; CHECK-T2-NEXT: it eq
175 ; CHECK-T2-NEXT: moveq r1, r2
176 ; CHECK-T2-NEXT: pop {r7, pc}
177 ;
178 ; CHECK-ARM-LABEL: func2:
179 ; CHECK-ARM: @ %bb.0:
180 ; CHECK-ARM-NEXT: .save {r11, lr}
181 ; CHECK-ARM-NEXT: push {r11, lr}
182 ; CHECK-ARM-NEXT: adds r0, r0, r2
183 ; CHECK-ARM-NEXT: mov r2, #0
184 ; CHECK-ARM-NEXT: adc r12, r1, r3
185 ; CHECK-ARM-NEXT: cmn r1, #1
186 ; CHECK-ARM-NEXT: mov r1, #0
187 ; CHECK-ARM-NEXT: mov lr, #0
188 ; CHECK-ARM-NEXT: movwgt r1, #1
189 ; CHECK-ARM-NEXT: cmn r12, #1
190 ; CHECK-ARM-NEXT: movwgt r2, #1
191 ; CHECK-ARM-NEXT: subs r2, r1, r2
192 ; CHECK-ARM-NEXT: movwne r2, #1
193 ; CHECK-ARM-NEXT: cmn r3, #1
194 ; CHECK-ARM-NEXT: movwgt lr, #1
195 ; CHECK-ARM-NEXT: sub r1, r1, lr
196 ; CHECK-ARM-NEXT: clz r1, r1
197 ; CHECK-ARM-NEXT: lsr r1, r1, #5
198 ; CHECK-ARM-NEXT: ands r2, r1, r2
199 ; CHECK-ARM-NEXT: asrne r0, r12, #31
200 ; CHECK-ARM-NEXT: mov r1, #-2147483648
201 ; CHECK-ARM-NEXT: cmp r12, #0
202 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
203 ; CHECK-ARM-NEXT: cmp r2, #0
204 ; CHECK-ARM-NEXT: moveq r1, r12
205 ; CHECK-ARM-NEXT: pop {r11, pc}
206 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
207 ret i64 %tmp
208 }
210 define i16 @func16(i16 %x, i16 %y) nounwind {
211 ; CHECK-T1-LABEL: func16:
212 ; CHECK-T1: @ %bb.0:
213 ; CHECK-T1-NEXT: lsls r3, r1, #16
214 ; CHECK-T1-NEXT: lsls r1, r0, #16
215 ; CHECK-T1-NEXT: movs r2, #1
216 ; CHECK-T1-NEXT: adds r0, r1, r3
217 ; CHECK-T1-NEXT: mov r3, r2
218 ; CHECK-T1-NEXT: bmi .LBB2_2
219 ; CHECK-T1-NEXT: @ %bb.1:
220 ; CHECK-T1-NEXT: movs r3, #0
221 ; CHECK-T1-NEXT: .LBB2_2:
222 ; CHECK-T1-NEXT: cmp r3, #0
223 ; CHECK-T1-NEXT: bne .LBB2_4
224 ; CHECK-T1-NEXT: @ %bb.3:
225 ; CHECK-T1-NEXT: lsls r2, r2, #31
226 ; CHECK-T1-NEXT: cmp r0, r1
227 ; CHECK-T1-NEXT: bvs .LBB2_5
228 ; CHECK-T1-NEXT: b .LBB2_6
229 ; CHECK-T1-NEXT: .LBB2_4:
230 ; CHECK-T1-NEXT: ldr r2, .LCPI2_0
231 ; CHECK-T1-NEXT: cmp r0, r1
232 ; CHECK-T1-NEXT: bvc .LBB2_6
233 ; CHECK-T1-NEXT: .LBB2_5:
234 ; CHECK-T1-NEXT: mov r0, r2
235 ; CHECK-T1-NEXT: .LBB2_6:
236 ; CHECK-T1-NEXT: asrs r0, r0, #16
237 ; CHECK-T1-NEXT: bx lr
238 ; CHECK-T1-NEXT: .p2align 2
239 ; CHECK-T1-NEXT: @ %bb.7:
240 ; CHECK-T1-NEXT: .LCPI2_0:
241 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
242 ;
243 ; CHECK-T2-LABEL: func16:
244 ; CHECK-T2: @ %bb.0:
245 ; CHECK-T2-NEXT: lsls r2, r0, #16
246 ; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #16
247 ; CHECK-T2-NEXT: movs r2, #0
248 ; CHECK-T2-NEXT: cmp r1, #0
249 ; CHECK-T2-NEXT: mov.w r3, #-2147483648
250 ; CHECK-T2-NEXT: it mi
251 ; CHECK-T2-NEXT: movmi r2, #1
252 ; CHECK-T2-NEXT: cmp r2, #0
253 ; CHECK-T2-NEXT: it ne
254 ; CHECK-T2-NEXT: mvnne r3, #-2147483648
255 ; CHECK-T2-NEXT: cmp.w r1, r0, lsl #16
256 ; CHECK-T2-NEXT: it vc
257 ; CHECK-T2-NEXT: movvc r3, r1
258 ; CHECK-T2-NEXT: asrs r0, r3, #16
259 ; CHECK-T2-NEXT: bx lr
260 ;
261 ; CHECK-ARM-LABEL: func16:
262 ; CHECK-ARM: @ %bb.0:
263 ; CHECK-ARM-NEXT: lsl r2, r0, #16
264 ; CHECK-ARM-NEXT: add r1, r2, r1, lsl #16
265 ; CHECK-ARM-NEXT: mov r2, #0
266 ; CHECK-ARM-NEXT: cmp r1, #0
267 ; CHECK-ARM-NEXT: movwmi r2, #1
268 ; CHECK-ARM-NEXT: mov r3, #-2147483648
269 ; CHECK-ARM-NEXT: cmp r2, #0
270 ; CHECK-ARM-NEXT: mvnne r3, #-2147483648
271 ; CHECK-ARM-NEXT: cmp r1, r0, lsl #16
272 ; CHECK-ARM-NEXT: movvc r3, r1
273 ; CHECK-ARM-NEXT: asr r0, r3, #16
274 ; CHECK-ARM-NEXT: bx lr
275 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
276 ret i16 %tmp
277 }
279 define i8 @func8(i8 %x, i8 %y) nounwind {
280 ; CHECK-T1-LABEL: func8:
281 ; CHECK-T1: @ %bb.0:
282 ; CHECK-T1-NEXT: lsls r3, r1, #24
283 ; CHECK-T1-NEXT: lsls r1, r0, #24
284 ; CHECK-T1-NEXT: movs r2, #1
285 ; CHECK-T1-NEXT: adds r0, r1, r3
286 ; CHECK-T1-NEXT: mov r3, r2
287 ; CHECK-T1-NEXT: bmi .LBB3_2
288 ; CHECK-T1-NEXT: @ %bb.1:
289 ; CHECK-T1-NEXT: movs r3, #0
290 ; CHECK-T1-NEXT: .LBB3_2:
291 ; CHECK-T1-NEXT: cmp r3, #0
292 ; CHECK-T1-NEXT: bne .LBB3_4
293 ; CHECK-T1-NEXT: @ %bb.3:
294 ; CHECK-T1-NEXT: lsls r2, r2, #31
295 ; CHECK-T1-NEXT: cmp r0, r1
296 ; CHECK-T1-NEXT: bvs .LBB3_5
297 ; CHECK-T1-NEXT: b .LBB3_6
298 ; CHECK-T1-NEXT: .LBB3_4:
299 ; CHECK-T1-NEXT: ldr r2, .LCPI3_0
300 ; CHECK-T1-NEXT: cmp r0, r1
301 ; CHECK-T1-NEXT: bvc .LBB3_6
302 ; CHECK-T1-NEXT: .LBB3_5:
303 ; CHECK-T1-NEXT: mov r0, r2
304 ; CHECK-T1-NEXT: .LBB3_6:
305 ; CHECK-T1-NEXT: asrs r0, r0, #24
306 ; CHECK-T1-NEXT: bx lr
307 ; CHECK-T1-NEXT: .p2align 2
308 ; CHECK-T1-NEXT: @ %bb.7:
309 ; CHECK-T1-NEXT: .LCPI3_0:
310 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
311 ;
312 ; CHECK-T2-LABEL: func8:
313 ; CHECK-T2: @ %bb.0:
314 ; CHECK-T2-NEXT: lsls r2, r0, #24
315 ; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #24
316 ; CHECK-T2-NEXT: movs r2, #0
317 ; CHECK-T2-NEXT: cmp r1, #0
318 ; CHECK-T2-NEXT: mov.w r3, #-2147483648
319 ; CHECK-T2-NEXT: it mi
320 ; CHECK-T2-NEXT: movmi r2, #1
321 ; CHECK-T2-NEXT: cmp r2, #0
322 ; CHECK-T2-NEXT: it ne
323 ; CHECK-T2-NEXT: mvnne r3, #-2147483648
324 ; CHECK-T2-NEXT: cmp.w r1, r0, lsl #24
325 ; CHECK-T2-NEXT: it vc
326 ; CHECK-T2-NEXT: movvc r3, r1
327 ; CHECK-T2-NEXT: asrs r0, r3, #24
328 ; CHECK-T2-NEXT: bx lr
329 ;
330 ; CHECK-ARM-LABEL: func8:
331 ; CHECK-ARM: @ %bb.0:
332 ; CHECK-ARM-NEXT: lsl r2, r0, #24
333 ; CHECK-ARM-NEXT: add r1, r2, r1, lsl #24
334 ; CHECK-ARM-NEXT: mov r2, #0
335 ; CHECK-ARM-NEXT: cmp r1, #0
336 ; CHECK-ARM-NEXT: movwmi r2, #1
337 ; CHECK-ARM-NEXT: mov r3, #-2147483648
338 ; CHECK-ARM-NEXT: cmp r2, #0
339 ; CHECK-ARM-NEXT: mvnne r3, #-2147483648
340 ; CHECK-ARM-NEXT: cmp r1, r0, lsl #24
341 ; CHECK-ARM-NEXT: movvc r3, r1
342 ; CHECK-ARM-NEXT: asr r0, r3, #24
343 ; CHECK-ARM-NEXT: bx lr
344 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
345 ret i8 %tmp
346 }
348 define i4 @func3(i4 %x, i4 %y) nounwind {
349 ; CHECK-T1-LABEL: func3:
350 ; CHECK-T1: @ %bb.0:
351 ; CHECK-T1-NEXT: lsls r3, r1, #28
352 ; CHECK-T1-NEXT: lsls r1, r0, #28
353 ; CHECK-T1-NEXT: movs r2, #1
354 ; CHECK-T1-NEXT: adds r0, r1, r3
355 ; CHECK-T1-NEXT: mov r3, r2
356 ; CHECK-T1-NEXT: bmi .LBB4_2
357 ; CHECK-T1-NEXT: @ %bb.1:
358 ; CHECK-T1-NEXT: movs r3, #0
359 ; CHECK-T1-NEXT: .LBB4_2:
360 ; CHECK-T1-NEXT: cmp r3, #0
361 ; CHECK-T1-NEXT: bne .LBB4_4
362 ; CHECK-T1-NEXT: @ %bb.3:
363 ; CHECK-T1-NEXT: lsls r2, r2, #31
364 ; CHECK-T1-NEXT: cmp r0, r1
365 ; CHECK-T1-NEXT: bvs .LBB4_5
366 ; CHECK-T1-NEXT: b .LBB4_6
367 ; CHECK-T1-NEXT: .LBB4_4:
368 ; CHECK-T1-NEXT: ldr r2, .LCPI4_0
369 ; CHECK-T1-NEXT: cmp r0, r1
370 ; CHECK-T1-NEXT: bvc .LBB4_6
371 ; CHECK-T1-NEXT: .LBB4_5:
372 ; CHECK-T1-NEXT: mov r0, r2
373 ; CHECK-T1-NEXT: .LBB4_6:
374 ; CHECK-T1-NEXT: asrs r0, r0, #28
375 ; CHECK-T1-NEXT: bx lr
376 ; CHECK-T1-NEXT: .p2align 2
377 ; CHECK-T1-NEXT: @ %bb.7:
378 ; CHECK-T1-NEXT: .LCPI4_0:
379 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
380 ;
381 ; CHECK-T2-LABEL: func3:
382 ; CHECK-T2: @ %bb.0:
383 ; CHECK-T2-NEXT: lsls r2, r0, #28
384 ; CHECK-T2-NEXT: add.w r1, r2, r1, lsl #28
385 ; CHECK-T2-NEXT: movs r2, #0
386 ; CHECK-T2-NEXT: cmp r1, #0
387 ; CHECK-T2-NEXT: mov.w r3, #-2147483648
388 ; CHECK-T2-NEXT: it mi
389 ; CHECK-T2-NEXT: movmi r2, #1
390 ; CHECK-T2-NEXT: cmp r2, #0
391 ; CHECK-T2-NEXT: it ne
392 ; CHECK-T2-NEXT: mvnne r3, #-2147483648
393 ; CHECK-T2-NEXT: cmp.w r1, r0, lsl #28
394 ; CHECK-T2-NEXT: it vc
395 ; CHECK-T2-NEXT: movvc r3, r1
396 ; CHECK-T2-NEXT: asrs r0, r3, #28
397 ; CHECK-T2-NEXT: bx lr
398 ;
399 ; CHECK-ARM-LABEL: func3:
400 ; CHECK-ARM: @ %bb.0:
401 ; CHECK-ARM-NEXT: lsl r2, r0, #28
402 ; CHECK-ARM-NEXT: add r1, r2, r1, lsl #28
403 ; CHECK-ARM-NEXT: mov r2, #0
404 ; CHECK-ARM-NEXT: cmp r1, #0
405 ; CHECK-ARM-NEXT: movwmi r2, #1
406 ; CHECK-ARM-NEXT: mov r3, #-2147483648
407 ; CHECK-ARM-NEXT: cmp r2, #0
408 ; CHECK-ARM-NEXT: mvnne r3, #-2147483648
409 ; CHECK-ARM-NEXT: cmp r1, r0, lsl #28
410 ; CHECK-ARM-NEXT: movvc r3, r1
411 ; CHECK-ARM-NEXT: asr r0, r3, #28
412 ; CHECK-ARM-NEXT: bx lr
413 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y)
414 ret i4 %tmp
415 }