1 ; RUN: llc -mtriple=aarch64-apple-ios -asm-verbose=false \
2 ; RUN: -aarch64-enable-collect-loh=false -aarch64-enable-global-merge \
3 ; RUN: -global-merge-group-by-use -global-merge-ignore-single-use %s -o - \
6 ; We assume that globals of the same size aren't reordered inside a set.
8 @m1 = internal global i32 0, align 4
9 @n1 = internal global i32 0, align 4
10 @o1 = internal global i32 0, align 4
13 define void @f1(i32 %a1, i32 %a2) #0 {
14 ; CHECK-NEXT: adrp x8, [[SET:__MergedGlobals]]@PAGE
15 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
16 ; CHECK-NEXT: stp w0, w1, [x8]
18 store i32 %a1, i32* @m1, align 4
19 store i32 %a2, i32* @n1, align 4
23 @m2 = internal global i32 0, align 4
24 @n2 = internal global i32 0, align 4
27 define void @f2(i32 %a1, i32 %a2, i32 %a3) #0 {
28 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
29 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF
30 ; CHECK-NEXT: stp w0, w1, [x8]
31 ; CHECK-NEXT: str w2, [x8, #8]
33 store i32 %a1, i32* @m1, align 4
34 store i32 %a2, i32* @n1, align 4
35 store i32 %a3, i32* @o1, align 4
40 define void @f3(i32 %a1, i32 %a2) #0 {
41 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE+12
42 ; CHECK-NEXT: add x8, x8, [[SET]]@PAGEOFF+12
43 ; CHECK-NEXT: stp w0, w1, [x8]
45 store i32 %a1, i32* @m2, align 4
46 store i32 %a2, i32* @n2, align 4
50 @o2 = internal global i32 0, align 4
53 define void @f4(i32 %a1) #0 {
54 ; CHECK-NEXT: adrp x8, _o2@PAGE
55 ; CHECK-NEXT: str w0, [x8, _o2@PAGEOFF]
57 store i32 %a1, i32* @o2, align 4
61 ; CHECK-DAG: .zerofill __DATA,__bss,[[SET]],20,2
62 ; CHECK-DAG: .zerofill __DATA,__bss,_o2,4,2
64 attributes #0 = { nounwind }