[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / ARC / MCTargetDesc / ARCInfo.h
blob57a77631a1fb5ab37157e2e26a78e03853edbf97
1 //===- ARCInfo.h - Additional ARC Info --------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the ARC target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
17 #define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
19 namespace llvm {
21 // Enums corresponding to ARC condition codes
22 namespace ARCCC {
24 enum CondCode {
25 AL = 0x0,
26 EQ = 0x1,
27 NE = 0x2,
28 P = 0x3,
29 N = 0x4,
30 LO = 0x5,
31 HS = 0x6,
32 VS = 0x7,
33 VC = 0x8,
34 GT = 0x9,
35 GE = 0xa,
36 LT = 0xb,
37 LE = 0xc,
38 HI = 0xd,
39 LS = 0xe,
40 PNZ = 0xf,
41 Z = 0x11, // Low 4-bits = EQ
42 NZ = 0x12 // Low 4-bits = NE
45 enum BRCondCode {
46 BREQ = 0x0,
47 BRNE = 0x1,
48 BRLT = 0x2,
49 BRGE = 0x3,
50 BRLO = 0x4,
51 BRHS = 0x5
54 } // end namespace ARCCC
56 } // end namespace llvm
58 #endif