lib/Target/X86/MCTargetDesc/X86BaseInfo.h

   1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains small standalone helper functions and enum definitions for
  10 // the X86 target useful for the compiler back-end and the MC libraries.
  11 // As such, it deliberately does not include references to LLVM core
  12 // code gen types, passes, etc..
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
  17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
  18
  19 #include "X86MCTargetDesc.h"
  20 #include "llvm/MC/MCInstrDesc.h"
  21 #include "llvm/Support/DataTypes.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23
  24 namespace llvm {
  25
  26 namespace X86 {
  27   // Enums for memory operand decoding.  Each memory operand is represented with
  28   // a 5 operand sequence in the form:
  29   //   [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
  30   // These enums help decode this.
  31   enum {
  32     AddrBaseReg = 0,
  33     AddrScaleAmt = 1,
  34     AddrIndexReg = 2,
  35     AddrDisp = 3,
  36
  37     /// AddrSegmentReg - The operand # of the segment in the memory operand.
  38     AddrSegmentReg = 4,
  39
  40     /// AddrNumOperands - Total number of operands in a memory reference.
  41     AddrNumOperands = 5
  42   };
  43
  44   /// AVX512 static rounding constants.  These need to match the values in
  45   /// avx512fintrin.h.
  46   enum STATIC_ROUNDING {
  47     TO_NEAREST_INT = 0,
  48     TO_NEG_INF = 1,
  49     TO_POS_INF = 2,
  50     TO_ZERO = 3,
  51     CUR_DIRECTION = 4,
  52     NO_EXC = 8
  53   };
  54
  55   /// The constants to describe instr prefixes if there are
  56   enum IPREFIXES {
  57     IP_NO_PREFIX = 0,
  58     IP_HAS_OP_SIZE = 1,
  59     IP_HAS_AD_SIZE = 2,
  60     IP_HAS_REPEAT_NE = 4,
  61     IP_HAS_REPEAT = 8,
  62     IP_HAS_LOCK = 16,
  63     IP_HAS_NOTRACK = 32,
  64     IP_USE_VEX3 = 64,
  65   };
  66
  67   enum OperandType : unsigned {
  68     /// AVX512 embedded rounding control. This should only have values 0-3.
  69     OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET,
  70     OPERAND_COND_CODE,
  71   };
  72
  73   // X86 specific condition code. These correspond to X86_*_COND in
  74   // X86InstrInfo.td. They must be kept in synch.
  75   enum CondCode {
  76     COND_O = 0,
  77     COND_NO = 1,
  78     COND_B = 2,
  79     COND_AE = 3,
  80     COND_E = 4,
  81     COND_NE = 5,
  82     COND_BE = 6,
  83     COND_A = 7,
  84     COND_S = 8,
  85     COND_NS = 9,
  86     COND_P = 10,
  87     COND_NP = 11,
  88     COND_L = 12,
  89     COND_GE = 13,
  90     COND_LE = 14,
  91     COND_G = 15,
  92     LAST_VALID_COND = COND_G,
  93
  94     // Artificial condition codes. These are used by AnalyzeBranch
  95     // to indicate a block terminated with two conditional branches that together
  96     // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
  97     // which can't be represented on x86 with a single condition. These
  98     // are never used in MachineInstrs and are inverses of one another.
  99     COND_NE_OR_P,
 100     COND_E_AND_NP,
 101
 102     COND_INVALID
 103   };
 104 } // end namespace X86;
 105
 106 /// X86II - This namespace holds all of the target specific flags that
 107 /// instruction info tracks.
 108 ///
 109 namespace X86II {
 110   /// Target Operand Flag enum.
 111   enum TOF {
 112     //===------------------------------------------------------------------===//
 113     // X86 Specific MachineOperand flags.
 114
 115     MO_NO_FLAG,
 116
 117     /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
 118     /// relocation of:
 119     ///    SYMBOL_LABEL + [. - PICBASELABEL]
 120     MO_GOT_ABSOLUTE_ADDRESS,
 121
 122     /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
 123     /// immediate should get the value of the symbol minus the PIC base label:
 124     ///    SYMBOL_LABEL - PICBASELABEL
 125     MO_PIC_BASE_OFFSET,
 126
 127     /// MO_GOT - On a symbol operand this indicates that the immediate is the
 128     /// offset to the GOT entry for the symbol name from the base of the GOT.
 129     ///
 130     /// See the X86-64 ELF ABI supplement for more details.
 131     ///    SYMBOL_LABEL @GOT
 132     MO_GOT,
 133
 134     /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
 135     /// the offset to the location of the symbol name from the base of the GOT.
 136     ///
 137     /// See the X86-64 ELF ABI supplement for more details.
 138     ///    SYMBOL_LABEL @GOTOFF
 139     MO_GOTOFF,
 140
 141     /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
 142     /// offset to the GOT entry for the symbol name from the current code
 143     /// location.
 144     ///
 145     /// See the X86-64 ELF ABI supplement for more details.
 146     ///    SYMBOL_LABEL @GOTPCREL
 147     MO_GOTPCREL,
 148
 149     /// MO_PLT - On a symbol operand this indicates that the immediate is
 150     /// offset to the PLT entry of symbol name from the current code location.
 151     ///
 152     /// See the X86-64 ELF ABI supplement for more details.
 153     ///    SYMBOL_LABEL @PLT
 154     MO_PLT,
 155
 156     /// MO_TLSGD - On a symbol operand this indicates that the immediate is
 157     /// the offset of the GOT entry with the TLS index structure that contains
 158     /// the module number and variable offset for the symbol. Used in the
 159     /// general dynamic TLS access model.
 160     ///
 161     /// See 'ELF Handling for Thread-Local Storage' for more details.
 162     ///    SYMBOL_LABEL @TLSGD
 163     MO_TLSGD,
 164
 165     /// MO_TLSLD - On a symbol operand this indicates that the immediate is
 166     /// the offset of the GOT entry with the TLS index for the module that
 167     /// contains the symbol. When this index is passed to a call to
 168     /// __tls_get_addr, the function will return the base address of the TLS
 169     /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
 170     ///
 171     /// See 'ELF Handling for Thread-Local Storage' for more details.
 172     ///    SYMBOL_LABEL @TLSLD
 173     MO_TLSLD,
 174
 175     /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
 176     /// the offset of the GOT entry with the TLS index for the module that
 177     /// contains the symbol. When this index is passed to a call to
 178     /// ___tls_get_addr, the function will return the base address of the TLS
 179     /// block for the symbol. Used in the IA32 local dynamic TLS access model.
 180     ///
 181     /// See 'ELF Handling for Thread-Local Storage' for more details.
 182     ///    SYMBOL_LABEL @TLSLDM
 183     MO_TLSLDM,
 184
 185     /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
 186     /// the offset of the GOT entry with the thread-pointer offset for the
 187     /// symbol. Used in the x86-64 initial exec TLS access model.
 188     ///
 189     /// See 'ELF Handling for Thread-Local Storage' for more details.
 190     ///    SYMBOL_LABEL @GOTTPOFF
 191     MO_GOTTPOFF,
 192
 193     /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
 194     /// the absolute address of the GOT entry with the negative thread-pointer
 195     /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
 196     /// model.
 197     ///
 198     /// See 'ELF Handling for Thread-Local Storage' for more details.
 199     ///    SYMBOL_LABEL @INDNTPOFF
 200     MO_INDNTPOFF,
 201
 202     /// MO_TPOFF - On a symbol operand this indicates that the immediate is
 203     /// the thread-pointer offset for the symbol. Used in the x86-64 local
 204     /// exec TLS access model.
 205     ///
 206     /// See 'ELF Handling for Thread-Local Storage' for more details.
 207     ///    SYMBOL_LABEL @TPOFF
 208     MO_TPOFF,
 209
 210     /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
 211     /// the offset of the GOT entry with the TLS offset of the symbol. Used
 212     /// in the local dynamic TLS access model.
 213     ///
 214     /// See 'ELF Handling for Thread-Local Storage' for more details.
 215     ///    SYMBOL_LABEL @DTPOFF
 216     MO_DTPOFF,
 217
 218     /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
 219     /// the negative thread-pointer offset for the symbol. Used in the IA32
 220     /// local exec TLS access model.
 221     ///
 222     /// See 'ELF Handling for Thread-Local Storage' for more details.
 223     ///    SYMBOL_LABEL @NTPOFF
 224     MO_NTPOFF,
 225
 226     /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
 227     /// the offset of the GOT entry with the negative thread-pointer offset for
 228     /// the symbol. Used in the PIC IA32 initial exec TLS access model.
 229     ///
 230     /// See 'ELF Handling for Thread-Local Storage' for more details.
 231     ///    SYMBOL_LABEL @GOTNTPOFF
 232     MO_GOTNTPOFF,
 233
 234     /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
 235     /// reference is actually to the "__imp_FOO" symbol.  This is used for
 236     /// dllimport linkage on windows.
 237     MO_DLLIMPORT,
 238
 239     /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
 240     /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
 241     /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 242     MO_DARWIN_NONLAZY,
 243
 244     /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
 245     /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
 246     /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 247     MO_DARWIN_NONLAZY_PIC_BASE,
 248
 249     /// MO_TLVP - On a symbol operand this indicates that the immediate is
 250     /// some TLS offset.
 251     ///
 252     /// This is the TLS offset for the Darwin TLS mechanism.
 253     MO_TLVP,
 254
 255     /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
 256     /// is some TLS offset from the picbase.
 257     ///
 258     /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
 259     MO_TLVP_PIC_BASE,
 260
 261     /// MO_SECREL - On a symbol operand this indicates that the immediate is
 262     /// the offset from beginning of section.
 263     ///
 264     /// This is the TLS offset for the COFF/Windows TLS mechanism.
 265     MO_SECREL,
 266
 267     /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
 268     /// to be an absolute symbol in range [0,128), so we can use the @ABS8
 269     /// symbol modifier.
 270     MO_ABS8,
 271
 272     /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
 273     /// reference is actually to the ".refptr.FOO" symbol.  This is used for
 274     /// stub symbols on windows.
 275     MO_COFFSTUB,
 276   };
 277
 278   enum : uint64_t {
 279     //===------------------------------------------------------------------===//
 280     // Instruction encodings.  These are the standard/most common forms for X86
 281     // instructions.
 282     //
 283
 284     // PseudoFrm - This represents an instruction that is a pseudo instruction
 285     // or one that has not been implemented yet.  It is illegal to code generate
 286     // it, but tolerated for intermediate implementation stages.
 287     Pseudo         = 0,
 288
 289     /// Raw - This form is for instructions that don't have any operands, so
 290     /// they are just a fixed opcode value, like 'leave'.
 291     RawFrm         = 1,
 292
 293     /// AddRegFrm - This form is used for instructions like 'push r32' that have
 294     /// their one register operand added to their opcode.
 295     AddRegFrm      = 2,
 296
 297     /// RawFrmMemOffs - This form is for instructions that store an absolute
 298     /// memory offset as an immediate with a possible segment override.
 299     RawFrmMemOffs  = 3,
 300
 301     /// RawFrmSrc - This form is for instructions that use the source index
 302     /// register SI/ESI/RSI with a possible segment override.
 303     RawFrmSrc      = 4,
 304
 305     /// RawFrmDst - This form is for instructions that use the destination index
 306     /// register DI/EDI/RDI.
 307     RawFrmDst      = 5,
 308
 309     /// RawFrmDstSrc - This form is for instructions that use the source index
 310     /// register SI/ESI/RSI with a possible segment override, and also the
 311     /// destination index register DI/EDI/RDI.
 312     RawFrmDstSrc   = 6,
 313
 314     /// RawFrmImm8 - This is used for the ENTER instruction, which has two
 315     /// immediates, the first of which is a 16-bit immediate (specified by
 316     /// the imm encoding) and the second is a 8-bit fixed value.
 317     RawFrmImm8 = 7,
 318
 319     /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
 320     /// immediates, the first of which is a 16 or 32-bit immediate (specified by
 321     /// the imm encoding) and the second is a 16-bit fixed value.  In the AMD
 322     /// manual, this operand is described as pntr16:32 and pntr16:16
 323     RawFrmImm16 = 8,
 324
 325     /// AddCCFrm - This form is used for Jcc that encode the condition code
 326     /// in the lower 4 bits of the opcode.
 327     AddCCFrm = 9,
 328
 329     /// MRM[0-7][rm] - These forms are used to represent instructions that use
 330     /// a Mod/RM byte, and use the middle field to hold extended opcode
 331     /// information.  In the intel manual these are represented as /0, /1, ...
 332     ///
 333
 334     /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
 335     /// to specify a destination, which in this case is memory.
 336     ///
 337     MRMDestMem     = 32,
 338
 339     /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
 340     /// to specify a source, which in this case is memory.
 341     ///
 342     MRMSrcMem      = 33,
 343
 344     /// MRMSrcMem4VOp3 - This form is used for instructions that encode
 345     /// operand 3 with VEX.VVVV and load from memory.
 346     ///
 347     MRMSrcMem4VOp3 = 34,
 348
 349     /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
 350     /// byte to specify the fourth source, which in this case is memory.
 351     ///
 352     MRMSrcMemOp4   = 35,
 353
 354     /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
 355     /// byte to specify the operands and also encodes a condition code.
 356     ///
 357     MRMSrcMemCC    = 36,
 358
 359     /// MRMXm - This form is used for instructions that use the Mod/RM byte
 360     /// to specify a memory source, but doesn't use the middle field. And has
 361     /// a condition code.
 362     ///
 363     MRMXmCC = 38,
 364
 365     /// MRMXm - This form is used for instructions that use the Mod/RM byte
 366     /// to specify a memory source, but doesn't use the middle field.
 367     ///
 368     MRMXm = 39,
 369
 370     // Next, instructions that operate on a memory r/m operand...
 371     MRM0m = 40,  MRM1m = 41,  MRM2m = 42,  MRM3m = 43, // Format /0 /1 /2 /3
 372     MRM4m = 44,  MRM5m = 45,  MRM6m = 46,  MRM7m = 47, // Format /4 /5 /6 /7
 373
 374     /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
 375     /// to specify a destination, which in this case is a register.
 376     ///
 377     MRMDestReg     = 48,
 378
 379     /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
 380     /// to specify a source, which in this case is a register.
 381     ///
 382     MRMSrcReg      = 49,
 383
 384     /// MRMSrcReg4VOp3 - This form is used for instructions that encode
 385     /// operand 3 with VEX.VVVV and do not load from memory.
 386     ///
 387     MRMSrcReg4VOp3 = 50,
 388
 389     /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
 390     /// byte to specify the fourth source, which in this case is a register.
 391     ///
 392     MRMSrcRegOp4   = 51,
 393
 394     /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
 395     /// byte to specify the operands and also encodes a condition code
 396     ///
 397     MRMSrcRegCC    = 52,
 398
 399     /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
 400     /// to specify a register source, but doesn't use the middle field. And has
 401     /// a condition code.
 402     ///
 403     MRMXrCC = 54,
 404
 405     /// MRMXr - This form is used for instructions that use the Mod/RM byte
 406     /// to specify a register source, but doesn't use the middle field.
 407     ///
 408     MRMXr = 55,
 409
 410     // Instructions that operate on a register r/m operand...
 411     MRM0r = 56,  MRM1r = 57,  MRM2r = 58,  MRM3r = 59, // Format /0 /1 /2 /3
 412     MRM4r = 60,  MRM5r = 61,  MRM6r = 62,  MRM7r = 63, // Format /4 /5 /6 /7
 413
 414     /// MRM_XX - A mod/rm byte of exactly 0xXX.
 415     MRM_C0 = 64,  MRM_C1 = 65,  MRM_C2 = 66,  MRM_C3 = 67,
 416     MRM_C4 = 68,  MRM_C5 = 69,  MRM_C6 = 70,  MRM_C7 = 71,
 417     MRM_C8 = 72,  MRM_C9 = 73,  MRM_CA = 74,  MRM_CB = 75,
 418     MRM_CC = 76,  MRM_CD = 77,  MRM_CE = 78,  MRM_CF = 79,
 419     MRM_D0 = 80,  MRM_D1 = 81,  MRM_D2 = 82,  MRM_D3 = 83,
 420     MRM_D4 = 84,  MRM_D5 = 85,  MRM_D6 = 86,  MRM_D7 = 87,
 421     MRM_D8 = 88,  MRM_D9 = 89,  MRM_DA = 90,  MRM_DB = 91,
 422     MRM_DC = 92,  MRM_DD = 93,  MRM_DE = 94,  MRM_DF = 95,
 423     MRM_E0 = 96,  MRM_E1 = 97,  MRM_E2 = 98,  MRM_E3 = 99,
 424     MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
 425     MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
 426     MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
 427     MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
 428     MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
 429     MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
 430     MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
 431
 432     FormMask       = 127,
 433
 434     //===------------------------------------------------------------------===//
 435     // Actual flags...
 436
 437     // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
 438     // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
 439     // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
 440     // prefix in 16-bit mode.
 441     OpSizeShift = 7,
 442     OpSizeMask = 0x3 << OpSizeShift,
 443
 444     OpSizeFixed  = 0 << OpSizeShift,
 445     OpSize16     = 1 << OpSizeShift,
 446     OpSize32     = 2 << OpSizeShift,
 447
 448     // AsSize - AdSizeX implies this instruction determines its need of 0x67
 449     // prefix from a normal ModRM memory operand. The other types indicate that
 450     // an operand is encoded with a specific width and a prefix is needed if
 451     // it differs from the current mode.
 452     AdSizeShift = OpSizeShift + 2,
 453     AdSizeMask  = 0x3 << AdSizeShift,
 454
 455     AdSizeX  = 0 << AdSizeShift,
 456     AdSize16 = 1 << AdSizeShift,
 457     AdSize32 = 2 << AdSizeShift,
 458     AdSize64 = 3 << AdSizeShift,
 459
 460     //===------------------------------------------------------------------===//
 461     // OpPrefix - There are several prefix bytes that are used as opcode
 462     // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
 463     // no prefix.
 464     //
 465     OpPrefixShift = AdSizeShift + 2,
 466     OpPrefixMask  = 0x3 << OpPrefixShift,
 467
 468     // PD - Prefix code for packed double precision vector floating point
 469     // operations performed in the SSE registers.
 470     PD = 1 << OpPrefixShift,
 471
 472     // XS, XD - These prefix codes are for single and double precision scalar
 473     // floating point operations performed in the SSE registers.
 474     XS = 2 << OpPrefixShift,  XD = 3 << OpPrefixShift,
 475
 476     //===------------------------------------------------------------------===//
 477     // OpMap - This field determines which opcode map this instruction
 478     // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
 479     //
 480     OpMapShift = OpPrefixShift + 2,
 481     OpMapMask  = 0x7 << OpMapShift,
 482
 483     // OB - OneByte - Set if this instruction has a one byte opcode.
 484     OB = 0 << OpMapShift,
 485
 486     // TB - TwoByte - Set if this instruction has a two byte opcode, which
 487     // starts with a 0x0F byte before the real opcode.
 488     TB = 1 << OpMapShift,
 489
 490     // T8, TA - Prefix after the 0x0F prefix.
 491     T8 = 2 << OpMapShift,  TA = 3 << OpMapShift,
 492
 493     // XOP8 - Prefix to include use of imm byte.
 494     XOP8 = 4 << OpMapShift,
 495
 496     // XOP9 - Prefix to exclude use of imm byte.
 497     XOP9 = 5 << OpMapShift,
 498
 499     // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
 500     XOPA = 6 << OpMapShift,
 501
 502     /// ThreeDNow - This indicates that the instruction uses the
 503     /// wacky 0x0F 0x0F prefix for 3DNow! instructions.  The manual documents
 504     /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
 505     /// storing a classifier in the imm8 field.  To simplify our implementation,
 506     /// we handle this by storeing the classifier in the opcode field and using
 507     /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
 508     ThreeDNow = 7 << OpMapShift,
 509
 510     //===------------------------------------------------------------------===//
 511     // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
 512     // They are used to specify GPRs and SSE registers, 64-bit operand size,
 513     // etc. We only cares about REX.W and REX.R bits and only the former is
 514     // statically determined.
 515     //
 516     REXShift    = OpMapShift + 3,
 517     REX_W       = 1 << REXShift,
 518
 519     //===------------------------------------------------------------------===//
 520     // This three-bit field describes the size of an immediate operand.  Zero is
 521     // unused so that we can tell if we forgot to set a value.
 522     ImmShift = REXShift + 1,
 523     ImmMask    = 15 << ImmShift,
 524     Imm8       = 1 << ImmShift,
 525     Imm8PCRel  = 2 << ImmShift,
 526     Imm8Reg    = 3 << ImmShift,
 527     Imm16      = 4 << ImmShift,
 528     Imm16PCRel = 5 << ImmShift,
 529     Imm32      = 6 << ImmShift,
 530     Imm32PCRel = 7 << ImmShift,
 531     Imm32S     = 8 << ImmShift,
 532     Imm64      = 9 << ImmShift,
 533
 534     //===------------------------------------------------------------------===//
 535     // FP Instruction Classification...  Zero is non-fp instruction.
 536
 537     // FPTypeMask - Mask for all of the FP types...
 538     FPTypeShift = ImmShift + 4,
 539     FPTypeMask  = 7 << FPTypeShift,
 540
 541     // NotFP - The default, set for instructions that do not use FP registers.
 542     NotFP      = 0 << FPTypeShift,
 543
 544     // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
 545     ZeroArgFP  = 1 << FPTypeShift,
 546
 547     // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
 548     OneArgFP   = 2 << FPTypeShift,
 549
 550     // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
 551     // result back to ST(0).  For example, fcos, fsqrt, etc.
 552     //
 553     OneArgFPRW = 3 << FPTypeShift,
 554
 555     // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
 556     // explicit argument, storing the result to either ST(0) or the implicit
 557     // argument.  For example: fadd, fsub, fmul, etc...
 558     TwoArgFP   = 4 << FPTypeShift,
 559
 560     // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
 561     // explicit argument, but have no destination.  Example: fucom, fucomi, ...
 562     CompareFP  = 5 << FPTypeShift,
 563
 564     // CondMovFP - "2 operand" floating point conditional move instructions.
 565     CondMovFP  = 6 << FPTypeShift,
 566
 567     // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
 568     SpecialFP  = 7 << FPTypeShift,
 569
 570     // Lock prefix
 571     LOCKShift = FPTypeShift + 3,
 572     LOCK = 1 << LOCKShift,
 573
 574     // REP prefix
 575     REPShift = LOCKShift + 1,
 576     REP = 1 << REPShift,
 577
 578     // Execution domain for SSE instructions.
 579     // 0 means normal, non-SSE instruction.
 580     SSEDomainShift = REPShift + 1,
 581
 582     // Encoding
 583     EncodingShift = SSEDomainShift + 2,
 584     EncodingMask = 0x3 << EncodingShift,
 585
 586     // VEX - encoding using 0xC4/0xC5
 587     VEX = 1 << EncodingShift,
 588
 589     /// XOP - Opcode prefix used by XOP instructions.
 590     XOP = 2 << EncodingShift,
 591
 592     // VEX_EVEX - Specifies that this instruction use EVEX form which provides
 593     // syntax support up to 32 512-bit register operands and up to 7 16-bit
 594     // mask operands as well as source operand data swizzling/memory operand
 595     // conversion, eviction hint, and rounding mode.
 596     EVEX = 3 << EncodingShift,
 597
 598     // Opcode
 599     OpcodeShift   = EncodingShift + 2,
 600
 601     /// VEX_W - Has a opcode specific functionality, but is used in the same
 602     /// way as REX_W is for regular SSE instructions.
 603     VEX_WShift  = OpcodeShift + 8,
 604     VEX_W       = 1ULL << VEX_WShift,
 605
 606     /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
 607     /// address instructions in SSE are represented as 3 address ones in AVX
 608     /// and the additional register is encoded in VEX_VVVV prefix.
 609     VEX_4VShift = VEX_WShift + 1,
 610     VEX_4V      = 1ULL << VEX_4VShift,
 611
 612     /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
 613     /// instruction uses 256-bit wide registers. This is usually auto detected
 614     /// if a VR256 register is used, but some AVX instructions also have this
 615     /// field marked when using a f256 memory references.
 616     VEX_LShift = VEX_4VShift + 1,
 617     VEX_L       = 1ULL << VEX_LShift,
 618
 619     // EVEX_K - Set if this instruction requires masking
 620     EVEX_KShift = VEX_LShift + 1,
 621     EVEX_K      = 1ULL << EVEX_KShift,
 622
 623     // EVEX_Z - Set if this instruction has EVEX.Z field set.
 624     EVEX_ZShift = EVEX_KShift + 1,
 625     EVEX_Z      = 1ULL << EVEX_ZShift,
 626
 627     // EVEX_L2 - Set if this instruction has EVEX.L' field set.
 628     EVEX_L2Shift = EVEX_ZShift + 1,
 629     EVEX_L2     = 1ULL << EVEX_L2Shift,
 630
 631     // EVEX_B - Set if this instruction has EVEX.B field set.
 632     EVEX_BShift = EVEX_L2Shift + 1,
 633     EVEX_B      = 1ULL << EVEX_BShift,
 634
 635     // The scaling factor for the AVX512's 8-bit compressed displacement.
 636     CD8_Scale_Shift = EVEX_BShift + 1,
 637     CD8_Scale_Mask = 127ULL << CD8_Scale_Shift,
 638
 639     /// Explicitly specified rounding control
 640     EVEX_RCShift = CD8_Scale_Shift + 7,
 641     EVEX_RC = 1ULL << EVEX_RCShift,
 642
 643     // NOTRACK prefix
 644     NoTrackShift = EVEX_RCShift + 1,
 645     NOTRACK = 1ULL << NoTrackShift
 646   };
 647
 648   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
 649   // specified machine instruction.
 650   //
 651   inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
 652     return TSFlags >> X86II::OpcodeShift;
 653   }
 654
 655   inline bool hasImm(uint64_t TSFlags) {
 656     return (TSFlags & X86II::ImmMask) != 0;
 657   }
 658
 659   /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
 660   /// of the specified instruction.
 661   inline unsigned getSizeOfImm(uint64_t TSFlags) {
 662     switch (TSFlags & X86II::ImmMask) {
 663     default: llvm_unreachable("Unknown immediate size");
 664     case X86II::Imm8:
 665     case X86II::Imm8PCRel:
 666     case X86II::Imm8Reg:    return 1;
 667     case X86II::Imm16:
 668     case X86II::Imm16PCRel: return 2;
 669     case X86II::Imm32:
 670     case X86II::Imm32S:
 671     case X86II::Imm32PCRel: return 4;
 672     case X86II::Imm64:      return 8;
 673     }
 674   }
 675
 676   /// isImmPCRel - Return true if the immediate of the specified instruction's
 677   /// TSFlags indicates that it is pc relative.
 678   inline unsigned isImmPCRel(uint64_t TSFlags) {
 679     switch (TSFlags & X86II::ImmMask) {
 680     default: llvm_unreachable("Unknown immediate size");
 681     case X86II::Imm8PCRel:
 682     case X86II::Imm16PCRel:
 683     case X86II::Imm32PCRel:
 684       return true;
 685     case X86II::Imm8:
 686     case X86II::Imm8Reg:
 687     case X86II::Imm16:
 688     case X86II::Imm32:
 689     case X86II::Imm32S:
 690     case X86II::Imm64:
 691       return false;
 692     }
 693   }
 694
 695   /// isImmSigned - Return true if the immediate of the specified instruction's
 696   /// TSFlags indicates that it is signed.
 697   inline unsigned isImmSigned(uint64_t TSFlags) {
 698     switch (TSFlags & X86II::ImmMask) {
 699     default: llvm_unreachable("Unknown immediate signedness");
 700     case X86II::Imm32S:
 701       return true;
 702     case X86II::Imm8:
 703     case X86II::Imm8PCRel:
 704     case X86II::Imm8Reg:
 705     case X86II::Imm16:
 706     case X86II::Imm16PCRel:
 707     case X86II::Imm32:
 708     case X86II::Imm32PCRel:
 709     case X86II::Imm64:
 710       return false;
 711     }
 712   }
 713
 714   /// getOperandBias - compute whether all of the def operands are repeated
 715   ///                  in the uses and therefore should be skipped.
 716   /// This determines the start of the unique operand list. We need to determine
 717   /// if all of the defs have a corresponding tied operand in the uses.
 718   /// Unfortunately, the tied operand information is encoded in the uses not
 719   /// the defs so we have to use some heuristics to find which operands to
 720   /// query.
 721   inline unsigned getOperandBias(const MCInstrDesc& Desc) {
 722     unsigned NumDefs = Desc.getNumDefs();
 723     unsigned NumOps = Desc.getNumOperands();
 724     switch (NumDefs) {
 725     default: llvm_unreachable("Unexpected number of defs");
 726     case 0:
 727       return 0;
 728     case 1:
 729       // Common two addr case.
 730       if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
 731         return 1;
 732       // Check for AVX-512 scatter which has a TIED_TO in the second to last
 733       // operand.
 734       if (NumOps == 8 &&
 735           Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
 736         return 1;
 737       return 0;
 738     case 2:
 739       // XCHG/XADD have two destinations and two sources.
 740       if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
 741           Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
 742         return 2;
 743       // Check for gather. AVX-512 has the second tied operand early. AVX2
 744       // has it as the last op.
 745       if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
 746           (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
 747            Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1))
 748         return 2;
 749       return 0;
 750     }
 751   }
 752
 753   /// getMemoryOperandNo - The function returns the MCInst operand # for the
 754   /// first field of the memory operand.  If the instruction doesn't have a
 755   /// memory operand, this returns -1.
 756   ///
 757   /// Note that this ignores tied operands.  If there is a tied register which
 758   /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
 759   /// counted as one operand.
 760   ///
 761   inline int getMemoryOperandNo(uint64_t TSFlags) {
 762     bool HasVEX_4V = TSFlags & X86II::VEX_4V;
 763     bool HasEVEX_K = TSFlags & X86II::EVEX_K;
 764
 765     switch (TSFlags & X86II::FormMask) {
 766     default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
 767     case X86II::Pseudo:
 768     case X86II::RawFrm:
 769     case X86II::AddRegFrm:
 770     case X86II::RawFrmImm8:
 771     case X86II::RawFrmImm16:
 772     case X86II::RawFrmMemOffs:
 773     case X86II::RawFrmSrc:
 774     case X86II::RawFrmDst:
 775     case X86II::RawFrmDstSrc:
 776     case X86II::AddCCFrm:
 777       return -1;
 778     case X86II::MRMDestMem:
 779       return 0;
 780     case X86II::MRMSrcMem:
 781       // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
 782       // mask register.
 783       return 1 + HasVEX_4V + HasEVEX_K;
 784     case X86II::MRMSrcMem4VOp3:
 785       // Skip registers encoded in reg.
 786       return 1 + HasEVEX_K;
 787     case X86II::MRMSrcMemOp4:
 788       // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
 789       return 3;
 790     case X86II::MRMSrcMemCC:
 791       // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
 792       // mask register.
 793       return 1;
 794     case X86II::MRMDestReg:
 795     case X86II::MRMSrcReg:
 796     case X86II::MRMSrcReg4VOp3:
 797     case X86II::MRMSrcRegOp4:
 798     case X86II::MRMSrcRegCC:
 799     case X86II::MRMXrCC:
 800     case X86II::MRMXr:
 801     case X86II::MRM0r: case X86II::MRM1r:
 802     case X86II::MRM2r: case X86II::MRM3r:
 803     case X86II::MRM4r: case X86II::MRM5r:
 804     case X86II::MRM6r: case X86II::MRM7r:
 805       return -1;
 806     case X86II::MRMXmCC:
 807     case X86II::MRMXm:
 808     case X86II::MRM0m: case X86II::MRM1m:
 809     case X86II::MRM2m: case X86II::MRM3m:
 810     case X86II::MRM4m: case X86II::MRM5m:
 811     case X86II::MRM6m: case X86II::MRM7m:
 812       // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
 813       return 0 + HasVEX_4V + HasEVEX_K;
 814     case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
 815     case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
 816     case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
 817     case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
 818     case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
 819     case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
 820     case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
 821     case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
 822     case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
 823     case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
 824     case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
 825     case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
 826     case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
 827     case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
 828     case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
 829     case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
 830     case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
 831     case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
 832     case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
 833     case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
 834     case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
 835     case X86II::MRM_FF:
 836       return -1;
 837     }
 838   }
 839
 840   /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
 841   /// higher) register?  e.g. r8, xmm8, xmm13, etc.
 842   inline bool isX86_64ExtendedReg(unsigned RegNo) {
 843     if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
 844         (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
 845         (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
 846       return true;
 847
 848     switch (RegNo) {
 849     default: break;
 850     case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
 851     case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
 852     case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
 853     case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
 854     case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
 855     case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
 856     case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
 857     case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
 858     case X86::CR8:   case X86::CR9:   case X86::CR10:  case X86::CR11:
 859     case X86::CR12:  case X86::CR13:  case X86::CR14:  case X86::CR15:
 860     case X86::DR8:   case X86::DR9:   case X86::DR10:  case X86::DR11:
 861     case X86::DR12:  case X86::DR13:  case X86::DR14:  case X86::DR15:
 862       return true;
 863     }
 864     return false;
 865   }
 866
 867   /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
 868   /// registers? e.g. zmm21, etc.
 869   static inline bool is32ExtendedReg(unsigned RegNo) {
 870     return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
 871             (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
 872             (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
 873   }
 874
 875
 876   inline bool isX86_64NonExtLowByteReg(unsigned reg) {
 877     return (reg == X86::SPL || reg == X86::BPL ||
 878             reg == X86::SIL || reg == X86::DIL);
 879   }
 880
 881   /// isKMasked - Is this a masked instruction.
 882   inline bool isKMasked(uint64_t TSFlags) {
 883     return (TSFlags & X86II::EVEX_K) != 0;
 884   }
 885
 886   /// isKMergedMasked - Is this a merge masked instruction.
 887   inline bool isKMergeMasked(uint64_t TSFlags) {
 888     return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
 889   }
 890 }
 891
 892 } // end namespace llvm;
 893
 894 #endif