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[AMDGPU] Check for immediate SrcC in mfma in AsmParser
[llvm-core.git] / lib / Target / X86 / MCTargetDesc / X86InstComments.cpp
blob73b1969b4e8227d5a83ade934e1dc05aab64952a
1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This defines functionality used to emit comments about X86 instructions to
10 // an output stream for -fverbose-asm.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86InstComments.h"
15 #include "X86ATTInstPrinter.h"
16 #include "X86BaseInfo.h"
17 #include "X86MCTargetDesc.h"
18 #include "Utils/X86ShuffleDecode.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/Support/raw_ostream.h"
22
23 using namespace llvm;
24
25 #define CASE_SSE_INS_COMMON(Inst, src) \
26 case X86::Inst##src:
27
28 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
29 case X86::V##Inst##Suffix##src:
30
31 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
32 case X86::V##Inst##Suffix##src##k:
33
34 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
35 case X86::V##Inst##Suffix##src##kz:
36
37 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
38 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
39 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
40 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
41
42 #define CASE_MOVDUP(Inst, src) \
43 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
44 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
45 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
46 CASE_AVX_INS_COMMON(Inst, , r##src) \
47 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
48 CASE_SSE_INS_COMMON(Inst, r##src)
49
50 #define CASE_MASK_MOVDUP(Inst, src) \
51 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
52 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
53 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
54
55 #define CASE_MASKZ_MOVDUP(Inst, src) \
56 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
57 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
58 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
59
60 #define CASE_PMOVZX(Inst, src) \
61 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
62 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
63 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
64 CASE_AVX_INS_COMMON(Inst, , r##src) \
65 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
66 CASE_SSE_INS_COMMON(Inst, r##src)
67
68 #define CASE_MASK_PMOVZX(Inst, src) \
69 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
70 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
71 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
72
73 #define CASE_MASKZ_PMOVZX(Inst, src) \
74 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
75 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
76 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
77
78 #define CASE_UNPCK(Inst, src) \
79 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
80 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
81 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
82 CASE_AVX_INS_COMMON(Inst, , r##src) \
83 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
84 CASE_SSE_INS_COMMON(Inst, r##src)
85
86 #define CASE_MASK_UNPCK(Inst, src) \
87 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
88 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
89 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
90
91 #define CASE_MASKZ_UNPCK(Inst, src) \
92 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
93 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
94 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
95
96 #define CASE_SHUF(Inst, suf) \
97 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
98 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
99 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
100 CASE_AVX_INS_COMMON(Inst, , suf) \
101 CASE_AVX_INS_COMMON(Inst, Y, suf) \
102 CASE_SSE_INS_COMMON(Inst, suf)
103
104 #define CASE_MASK_SHUF(Inst, src) \
105 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
106 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
107 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
108
109 #define CASE_MASKZ_SHUF(Inst, src) \
110 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
111 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
112 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
113
114 #define CASE_VPERMILPI(Inst, src) \
115 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
116 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
117 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
118 CASE_AVX_INS_COMMON(Inst, , src##i) \
119 CASE_AVX_INS_COMMON(Inst, Y, src##i)
120
121 #define CASE_MASK_VPERMILPI(Inst, src) \
122 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
123 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
124 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
125
126 #define CASE_MASKZ_VPERMILPI(Inst, src) \
127 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
128 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
129 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
130
131 #define CASE_VPERM(Inst, src) \
132 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
133 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
134 CASE_AVX_INS_COMMON(Inst, Y, src##i)
135
136 #define CASE_MASK_VPERM(Inst, src) \
137 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
138 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
139
140 #define CASE_MASKZ_VPERM(Inst, src) \
141 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
142 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
143
144 #define CASE_VSHUF(Inst, src) \
145 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
146 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
147 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
148 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
149
150 #define CASE_MASK_VSHUF(Inst, src) \
151 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
152 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
153 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
154 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
155
156 #define CASE_MASKZ_VSHUF(Inst, src) \
157 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
158 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
159 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
160 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
161
162 #define CASE_AVX512_FMA(Inst, suf) \
163 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
164 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
165 CASE_AVX512_INS_COMMON(Inst, Z128, suf)
166
167 #define CASE_FMA(Inst, suf) \
168 CASE_AVX512_FMA(Inst, suf) \
169 CASE_AVX_INS_COMMON(Inst, , suf) \
170 CASE_AVX_INS_COMMON(Inst, Y, suf)
171
172 #define CASE_FMA_PACKED_REG(Inst) \
173 CASE_FMA(Inst##PD, r) \
174 CASE_FMA(Inst##PS, r)
175
176 #define CASE_FMA_PACKED_MEM(Inst) \
177 CASE_FMA(Inst##PD, m) \
178 CASE_FMA(Inst##PS, m) \
179 CASE_AVX512_FMA(Inst##PD, mb) \
180 CASE_AVX512_FMA(Inst##PS, mb)
181
182 #define CASE_FMA_SCALAR_REG(Inst) \
183 CASE_AVX_INS_COMMON(Inst##SD, , r) \
184 CASE_AVX_INS_COMMON(Inst##SS, , r) \
185 CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \
186 CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \
187 CASE_AVX_INS_COMMON(Inst##SD, Z, r) \
188 CASE_AVX_INS_COMMON(Inst##SS, Z, r) \
189 CASE_AVX512_INS_COMMON(Inst##SD, Z, r_Int) \
190 CASE_AVX512_INS_COMMON(Inst##SS, Z, r_Int)
191
192 #define CASE_FMA_SCALAR_MEM(Inst) \
193 CASE_AVX_INS_COMMON(Inst##SD, , m) \
194 CASE_AVX_INS_COMMON(Inst##SS, , m) \
195 CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \
196 CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \
197 CASE_AVX_INS_COMMON(Inst##SD, Z, m) \
198 CASE_AVX_INS_COMMON(Inst##SS, Z, m) \
199 CASE_AVX512_INS_COMMON(Inst##SD, Z, m_Int) \
200 CASE_AVX512_INS_COMMON(Inst##SS, Z, m_Int)
201
202 static unsigned getVectorRegSize(unsigned RegNo) {
203 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
204 return 512;
205 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
206 return 256;
207 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
208 return 128;
209 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
210 return 64;
211
212 llvm_unreachable("Unknown vector reg!");
213 }
214
215 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
216 unsigned OperandIndex) {
217 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
218 return getVectorRegSize(OpReg) / ScalarSize;
219 }
220
221 static const char *getRegName(unsigned Reg) {
222 return X86ATTInstPrinter::getRegisterName(Reg);
223 }
224
225 /// Wraps the destination register name with AVX512 mask/maskz filtering.
226 static void printMasking(raw_ostream &OS, const MCInst *MI,
227 const MCInstrInfo &MCII) {
228 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
229 uint64_t TSFlags = Desc.TSFlags;
230
231 if (!(TSFlags & X86II::EVEX_K))
232 return;
233
234 bool MaskWithZero = (TSFlags & X86II::EVEX_Z);
235 unsigned MaskOp = Desc.getNumDefs();
236
237 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1)
238 ++MaskOp;
239
240 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
241
242 // MASK: zmmX {%kY}
243 OS << " {%" << MaskRegName << "}";
244
245 // MASKZ: zmmX {%kY} {z}
246 if (MaskWithZero)
247 OS << " {z}";
248 }
249
250 static bool printFMA3Comments(const MCInst *MI, raw_ostream &OS) {
251 const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr;
252 unsigned NumOperands = MI->getNumOperands();
253 bool RegForm = false;
254 bool Negate = false;
255 StringRef AccStr = "+";
256
257 // The operands for FMA instructions without rounding fall into two forms.
258 // dest, src1, src2, src3
259 // dest, src1, mask, src2, src3
260 // Where src3 is either a register or 5 memory address operands. So to find
261 // dest and src1 we can index from the front. To find src2 and src3 we can
262 // index from the end by taking into account memory vs register form when
263 // finding src2.
264
265 switch (MI->getOpcode()) {
266 default:
267 return false;
268 CASE_FMA_PACKED_REG(FMADD132)
269 CASE_FMA_SCALAR_REG(FMADD132)
270 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
271 RegForm = true;
272 LLVM_FALLTHROUGH;
273 CASE_FMA_PACKED_MEM(FMADD132)
274 CASE_FMA_SCALAR_MEM(FMADD132)
275 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
276 Mul1Name = getRegName(MI->getOperand(1).getReg());
277 break;
278
279 CASE_FMA_PACKED_REG(FMADD213)
280 CASE_FMA_SCALAR_REG(FMADD213)
281 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
282 RegForm = true;
283 LLVM_FALLTHROUGH;
284 CASE_FMA_PACKED_MEM(FMADD213)
285 CASE_FMA_SCALAR_MEM(FMADD213)
286 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
287 Mul2Name = getRegName(MI->getOperand(1).getReg());
288 break;
289
290 CASE_FMA_PACKED_REG(FMADD231)
291 CASE_FMA_SCALAR_REG(FMADD231)
292 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
293 RegForm = true;
294 LLVM_FALLTHROUGH;
295 CASE_FMA_PACKED_MEM(FMADD231)
296 CASE_FMA_SCALAR_MEM(FMADD231)
297 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
298 AccName = getRegName(MI->getOperand(1).getReg());
299 break;
300
301 CASE_FMA_PACKED_REG(FMSUB132)
302 CASE_FMA_SCALAR_REG(FMSUB132)
303 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
304 RegForm = true;
305 LLVM_FALLTHROUGH;
306 CASE_FMA_PACKED_MEM(FMSUB132)
307 CASE_FMA_SCALAR_MEM(FMSUB132)
308 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
309 Mul1Name = getRegName(MI->getOperand(1).getReg());
310 AccStr = "-";
311 break;
312
313 CASE_FMA_PACKED_REG(FMSUB213)
314 CASE_FMA_SCALAR_REG(FMSUB213)
315 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
316 RegForm = true;
317 LLVM_FALLTHROUGH;
318 CASE_FMA_PACKED_MEM(FMSUB213)
319 CASE_FMA_SCALAR_MEM(FMSUB213)
320 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
321 Mul2Name = getRegName(MI->getOperand(1).getReg());
322 AccStr = "-";
323 break;
324
325 CASE_FMA_PACKED_REG(FMSUB231)
326 CASE_FMA_SCALAR_REG(FMSUB231)
327 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
328 RegForm = true;
329 LLVM_FALLTHROUGH;
330 CASE_FMA_PACKED_MEM(FMSUB231)
331 CASE_FMA_SCALAR_MEM(FMSUB231)
332 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
333 AccName = getRegName(MI->getOperand(1).getReg());
334 AccStr = "-";
335 break;
336
337 CASE_FMA_PACKED_REG(FNMADD132)
338 CASE_FMA_SCALAR_REG(FNMADD132)
339 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
340 RegForm = true;
341 LLVM_FALLTHROUGH;
342 CASE_FMA_PACKED_MEM(FNMADD132)
343 CASE_FMA_SCALAR_MEM(FNMADD132)
344 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
345 Mul1Name = getRegName(MI->getOperand(1).getReg());
346 Negate = true;
347 break;
348
349 CASE_FMA_PACKED_REG(FNMADD213)
350 CASE_FMA_SCALAR_REG(FNMADD213)
351 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
352 RegForm = true;
353 LLVM_FALLTHROUGH;
354 CASE_FMA_PACKED_MEM(FNMADD213)
355 CASE_FMA_SCALAR_MEM(FNMADD213)
356 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
357 Mul2Name = getRegName(MI->getOperand(1).getReg());
358 Negate = true;
359 break;
360
361 CASE_FMA_PACKED_REG(FNMADD231)
362 CASE_FMA_SCALAR_REG(FNMADD231)
363 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
364 RegForm = true;
365 LLVM_FALLTHROUGH;
366 CASE_FMA_PACKED_MEM(FNMADD231)
367 CASE_FMA_SCALAR_MEM(FNMADD231)
368 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
369 AccName = getRegName(MI->getOperand(1).getReg());
370 Negate = true;
371 break;
372
373 CASE_FMA_PACKED_REG(FNMSUB132)
374 CASE_FMA_SCALAR_REG(FNMSUB132)
375 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
376 RegForm = true;
377 LLVM_FALLTHROUGH;
378 CASE_FMA_PACKED_MEM(FNMSUB132)
379 CASE_FMA_SCALAR_MEM(FNMSUB132)
380 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
381 Mul1Name = getRegName(MI->getOperand(1).getReg());
382 AccStr = "-";
383 Negate = true;
384 break;
385
386 CASE_FMA_PACKED_REG(FNMSUB213)
387 CASE_FMA_SCALAR_REG(FNMSUB213)
388 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
389 RegForm = true;
390 LLVM_FALLTHROUGH;
391 CASE_FMA_PACKED_MEM(FNMSUB213)
392 CASE_FMA_SCALAR_MEM(FNMSUB213)
393 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
394 Mul2Name = getRegName(MI->getOperand(1).getReg());
395 AccStr = "-";
396 Negate = true;
397 break;
398
399 CASE_FMA_PACKED_REG(FNMSUB231)
400 CASE_FMA_SCALAR_REG(FNMSUB231)
401 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
402 RegForm = true;
403 LLVM_FALLTHROUGH;
404 CASE_FMA_PACKED_MEM(FNMSUB231)
405 CASE_FMA_SCALAR_MEM(FNMSUB231)
406 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
407 AccName = getRegName(MI->getOperand(1).getReg());
408 AccStr = "-";
409 Negate = true;
410 break;
411
412 CASE_FMA_PACKED_REG(FMADDSUB132)
413 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
414 RegForm = true;
415 LLVM_FALLTHROUGH;
416 CASE_FMA_PACKED_MEM(FMADDSUB132)
417 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
418 Mul1Name = getRegName(MI->getOperand(1).getReg());
419 AccStr = "+/-";
420 break;
421
422 CASE_FMA_PACKED_REG(FMADDSUB213)
423 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
424 RegForm = true;
425 LLVM_FALLTHROUGH;
426 CASE_FMA_PACKED_MEM(FMADDSUB213)
427 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
428 Mul2Name = getRegName(MI->getOperand(1).getReg());
429 AccStr = "+/-";
430 break;
431
432 CASE_FMA_PACKED_REG(FMADDSUB231)
433 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
434 RegForm = true;
435 LLVM_FALLTHROUGH;
436 CASE_FMA_PACKED_MEM(FMADDSUB231)
437 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
438 AccName = getRegName(MI->getOperand(1).getReg());
439 AccStr = "+/-";
440 break;
441
442 CASE_FMA_PACKED_REG(FMSUBADD132)
443 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
444 RegForm = true;
445 LLVM_FALLTHROUGH;
446 CASE_FMA_PACKED_MEM(FMSUBADD132)
447 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
448 Mul1Name = getRegName(MI->getOperand(1).getReg());
449 AccStr = "-/+";
450 break;
451
452 CASE_FMA_PACKED_REG(FMSUBADD213)
453 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
454 RegForm = true;
455 LLVM_FALLTHROUGH;
456 CASE_FMA_PACKED_MEM(FMSUBADD213)
457 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
458 Mul2Name = getRegName(MI->getOperand(1).getReg());
459 AccStr = "-/+";
460 break;
461
462 CASE_FMA_PACKED_REG(FMSUBADD231)
463 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
464 RegForm = true;
465 LLVM_FALLTHROUGH;
466 CASE_FMA_PACKED_MEM(FMSUBADD231)
467 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
468 AccName = getRegName(MI->getOperand(1).getReg());
469 AccStr = "-/+";
470 break;
471 }
472
473 const char *DestName = getRegName(MI->getOperand(0).getReg());
474
475 if (!Mul1Name) Mul1Name = "mem";
476 if (!Mul2Name) Mul2Name = "mem";
477 if (!AccName) AccName = "mem";
478
479 OS << DestName << " = ";
480 // TODO: Print masking information?
481
482 if (Negate)
483 OS << '-';
484
485 OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' '
486 << AccName;
487
488 return true;
489 }
490
491
492 //===----------------------------------------------------------------------===//
493 // Top Level Entrypoint
494 //===----------------------------------------------------------------------===//
495
496 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
497 /// newline terminated strings to the specified string if desired. This
498 /// information is shown in disassembly dumps when verbose assembly is enabled.
499 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
500 const MCInstrInfo &MCII) {
501 // If this is a shuffle operation, the switch should fill in this state.
502 SmallVector<int, 8> ShuffleMask;
503 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
504 unsigned NumOperands = MI->getNumOperands();
505 bool RegForm = false;
506
507 if (printFMA3Comments(MI, OS))
508 return true;
509
510 switch (MI->getOpcode()) {
511 default:
512 // Not an instruction for which we can decode comments.
513 return false;
514
515 case X86::BLENDPDrri:
516 case X86::VBLENDPDrri:
517 case X86::VBLENDPDYrri:
518 Src2Name = getRegName(MI->getOperand(2).getReg());
519 LLVM_FALLTHROUGH;
520 case X86::BLENDPDrmi:
521 case X86::VBLENDPDrmi:
522 case X86::VBLENDPDYrmi:
523 if (MI->getOperand(NumOperands - 1).isImm())
524 DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0),
525 MI->getOperand(NumOperands - 1).getImm(),
526 ShuffleMask);
527 Src1Name = getRegName(MI->getOperand(1).getReg());
528 DestName = getRegName(MI->getOperand(0).getReg());
529 break;
530
531 case X86::BLENDPSrri:
532 case X86::VBLENDPSrri:
533 case X86::VBLENDPSYrri:
534 Src2Name = getRegName(MI->getOperand(2).getReg());
535 LLVM_FALLTHROUGH;
536 case X86::BLENDPSrmi:
537 case X86::VBLENDPSrmi:
538 case X86::VBLENDPSYrmi:
539 if (MI->getOperand(NumOperands - 1).isImm())
540 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
541 MI->getOperand(NumOperands - 1).getImm(),
542 ShuffleMask);
543 Src1Name = getRegName(MI->getOperand(1).getReg());
544 DestName = getRegName(MI->getOperand(0).getReg());
545 break;
546
547 case X86::PBLENDWrri:
548 case X86::VPBLENDWrri:
549 case X86::VPBLENDWYrri:
550 Src2Name = getRegName(MI->getOperand(2).getReg());
551 LLVM_FALLTHROUGH;
552 case X86::PBLENDWrmi:
553 case X86::VPBLENDWrmi:
554 case X86::VPBLENDWYrmi:
555 if (MI->getOperand(NumOperands - 1).isImm())
556 DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0),
557 MI->getOperand(NumOperands - 1).getImm(),
558 ShuffleMask);
559 Src1Name = getRegName(MI->getOperand(1).getReg());
560 DestName = getRegName(MI->getOperand(0).getReg());
561 break;
562
563 case X86::VPBLENDDrri:
564 case X86::VPBLENDDYrri:
565 Src2Name = getRegName(MI->getOperand(2).getReg());
566 LLVM_FALLTHROUGH;
567 case X86::VPBLENDDrmi:
568 case X86::VPBLENDDYrmi:
569 if (MI->getOperand(NumOperands - 1).isImm())
570 DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
571 MI->getOperand(NumOperands - 1).getImm(),
572 ShuffleMask);
573 Src1Name = getRegName(MI->getOperand(1).getReg());
574 DestName = getRegName(MI->getOperand(0).getReg());
575 break;
576
577 case X86::INSERTPSrr:
578 case X86::VINSERTPSrr:
579 case X86::VINSERTPSZrr:
580 Src2Name = getRegName(MI->getOperand(2).getReg());
581 LLVM_FALLTHROUGH;
582 case X86::INSERTPSrm:
583 case X86::VINSERTPSrm:
584 case X86::VINSERTPSZrm:
585 DestName = getRegName(MI->getOperand(0).getReg());
586 Src1Name = getRegName(MI->getOperand(1).getReg());
587 if (MI->getOperand(NumOperands - 1).isImm())
588 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
589 ShuffleMask);
590 break;
591
592 case X86::MOVLHPSrr:
593 case X86::VMOVLHPSrr:
594 case X86::VMOVLHPSZrr:
595 Src2Name = getRegName(MI->getOperand(2).getReg());
596 Src1Name = getRegName(MI->getOperand(1).getReg());
597 DestName = getRegName(MI->getOperand(0).getReg());
598 DecodeMOVLHPSMask(2, ShuffleMask);
599 break;
600
601 case X86::MOVHLPSrr:
602 case X86::VMOVHLPSrr:
603 case X86::VMOVHLPSZrr:
604 Src2Name = getRegName(MI->getOperand(2).getReg());
605 Src1Name = getRegName(MI->getOperand(1).getReg());
606 DestName = getRegName(MI->getOperand(0).getReg());
607 DecodeMOVHLPSMask(2, ShuffleMask);
608 break;
609
610 case X86::MOVHPDrm:
611 case X86::VMOVHPDrm:
612 case X86::VMOVHPDZ128rm:
613 Src1Name = getRegName(MI->getOperand(1).getReg());
614 DestName = getRegName(MI->getOperand(0).getReg());
615 DecodeInsertElementMask(2, 1, 1, ShuffleMask);
616 break;
617
618 case X86::MOVHPSrm:
619 case X86::VMOVHPSrm:
620 case X86::VMOVHPSZ128rm:
621 Src1Name = getRegName(MI->getOperand(1).getReg());
622 DestName = getRegName(MI->getOperand(0).getReg());
623 DecodeInsertElementMask(4, 2, 2, ShuffleMask);
624 break;
625
626 case X86::MOVLPDrm:
627 case X86::VMOVLPDrm:
628 case X86::VMOVLPDZ128rm:
629 Src1Name = getRegName(MI->getOperand(1).getReg());
630 DestName = getRegName(MI->getOperand(0).getReg());
631 DecodeInsertElementMask(2, 0, 1, ShuffleMask);
632 break;
633
634 case X86::MOVLPSrm:
635 case X86::VMOVLPSrm:
636 case X86::VMOVLPSZ128rm:
637 Src1Name = getRegName(MI->getOperand(1).getReg());
638 DestName = getRegName(MI->getOperand(0).getReg());
639 DecodeInsertElementMask(4, 0, 2, ShuffleMask);
640 break;
641
642 CASE_MOVDUP(MOVSLDUP, r)
643 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
644 LLVM_FALLTHROUGH;
645
646 CASE_MOVDUP(MOVSLDUP, m)
647 DestName = getRegName(MI->getOperand(0).getReg());
648 DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
649 break;
650
651 CASE_MOVDUP(MOVSHDUP, r)
652 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
653 LLVM_FALLTHROUGH;
654
655 CASE_MOVDUP(MOVSHDUP, m)
656 DestName = getRegName(MI->getOperand(0).getReg());
657 DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
658 break;
659
660 CASE_MOVDUP(MOVDDUP, r)
661 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
662 LLVM_FALLTHROUGH;
663
664 CASE_MOVDUP(MOVDDUP, m)
665 DestName = getRegName(MI->getOperand(0).getReg());
666 DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask);
667 break;
668
669 case X86::PSLLDQri:
670 case X86::VPSLLDQri:
671 case X86::VPSLLDQYri:
672 case X86::VPSLLDQZ128rr:
673 case X86::VPSLLDQZ256rr:
674 case X86::VPSLLDQZrr:
675 Src1Name = getRegName(MI->getOperand(1).getReg());
676 LLVM_FALLTHROUGH;
677 case X86::VPSLLDQZ128rm:
678 case X86::VPSLLDQZ256rm:
679 case X86::VPSLLDQZrm:
680 DestName = getRegName(MI->getOperand(0).getReg());
681 if (MI->getOperand(NumOperands - 1).isImm())
682 DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),
683 MI->getOperand(NumOperands - 1).getImm(),
684 ShuffleMask);
685 break;
686
687 case X86::PSRLDQri:
688 case X86::VPSRLDQri:
689 case X86::VPSRLDQYri:
690 case X86::VPSRLDQZ128rr:
691 case X86::VPSRLDQZ256rr:
692 case X86::VPSRLDQZrr:
693 Src1Name = getRegName(MI->getOperand(1).getReg());
694 LLVM_FALLTHROUGH;
695 case X86::VPSRLDQZ128rm:
696 case X86::VPSRLDQZ256rm:
697 case X86::VPSRLDQZrm:
698 DestName = getRegName(MI->getOperand(0).getReg());
699 if (MI->getOperand(NumOperands - 1).isImm())
700 DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),
701 MI->getOperand(NumOperands - 1).getImm(),
702 ShuffleMask);
703 break;
704
705 CASE_SHUF(PALIGNR, rri)
706 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
707 RegForm = true;
708 LLVM_FALLTHROUGH;
709
710 CASE_SHUF(PALIGNR, rmi)
711 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
712 DestName = getRegName(MI->getOperand(0).getReg());
713 if (MI->getOperand(NumOperands - 1).isImm())
714 DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0),
715 MI->getOperand(NumOperands - 1).getImm(),
716 ShuffleMask);
717 break;
718
719 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
720 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
721 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
722 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
723 RegForm = true;
724 LLVM_FALLTHROUGH;
725
726 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
727 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
728 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
729 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
730 DestName = getRegName(MI->getOperand(0).getReg());
731 if (MI->getOperand(NumOperands - 1).isImm())
732 DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0),
733 MI->getOperand(NumOperands - 1).getImm(),
734 ShuffleMask);
735 break;
736
737 CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
738 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
739 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
740 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
741 RegForm = true;
742 LLVM_FALLTHROUGH;
743
744 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
745 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
746 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
747 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
748 DestName = getRegName(MI->getOperand(0).getReg());
749 if (MI->getOperand(NumOperands - 1).isImm())
750 DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0),
751 MI->getOperand(NumOperands - 1).getImm(),
752 ShuffleMask);
753 break;
754
755 CASE_SHUF(PSHUFD, ri)
756 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
757 LLVM_FALLTHROUGH;
758
759 CASE_SHUF(PSHUFD, mi)
760 DestName = getRegName(MI->getOperand(0).getReg());
761 if (MI->getOperand(NumOperands - 1).isImm())
762 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
763 MI->getOperand(NumOperands - 1).getImm(),
764 ShuffleMask);
765 break;
766
767 CASE_SHUF(PSHUFHW, ri)
768 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
769 LLVM_FALLTHROUGH;
770
771 CASE_SHUF(PSHUFHW, mi)
772 DestName = getRegName(MI->getOperand(0).getReg());
773 if (MI->getOperand(NumOperands - 1).isImm())
774 DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0),
775 MI->getOperand(NumOperands - 1).getImm(),
776 ShuffleMask);
777 break;
778
779 CASE_SHUF(PSHUFLW, ri)
780 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
781 LLVM_FALLTHROUGH;
782
783 CASE_SHUF(PSHUFLW, mi)
784 DestName = getRegName(MI->getOperand(0).getReg());
785 if (MI->getOperand(NumOperands - 1).isImm())
786 DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0),
787 MI->getOperand(NumOperands - 1).getImm(),
788 ShuffleMask);
789 break;
790
791 case X86::MMX_PSHUFWri:
792 Src1Name = getRegName(MI->getOperand(1).getReg());
793 LLVM_FALLTHROUGH;
794
795 case X86::MMX_PSHUFWmi:
796 DestName = getRegName(MI->getOperand(0).getReg());
797 if (MI->getOperand(NumOperands - 1).isImm())
798 DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(),
799 ShuffleMask);
800 break;
801
802 case X86::PSWAPDrr:
803 Src1Name = getRegName(MI->getOperand(1).getReg());
804 LLVM_FALLTHROUGH;
805
806 case X86::PSWAPDrm:
807 DestName = getRegName(MI->getOperand(0).getReg());
808 DecodePSWAPMask(2, ShuffleMask);
809 break;
810
811 CASE_UNPCK(PUNPCKHBW, r)
812 case X86::MMX_PUNPCKHBWirr:
813 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
814 RegForm = true;
815 LLVM_FALLTHROUGH;
816
817 CASE_UNPCK(PUNPCKHBW, m)
818 case X86::MMX_PUNPCKHBWirm:
819 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
820 DestName = getRegName(MI->getOperand(0).getReg());
821 DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
822 break;
823
824 CASE_UNPCK(PUNPCKHWD, r)
825 case X86::MMX_PUNPCKHWDirr:
826 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
827 RegForm = true;
828 LLVM_FALLTHROUGH;
829
830 CASE_UNPCK(PUNPCKHWD, m)
831 case X86::MMX_PUNPCKHWDirm:
832 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
833 DestName = getRegName(MI->getOperand(0).getReg());
834 DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
835 break;
836
837 CASE_UNPCK(PUNPCKHDQ, r)
838 case X86::MMX_PUNPCKHDQirr:
839 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
840 RegForm = true;
841 LLVM_FALLTHROUGH;
842
843 CASE_UNPCK(PUNPCKHDQ, m)
844 case X86::MMX_PUNPCKHDQirm:
845 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
846 DestName = getRegName(MI->getOperand(0).getReg());
847 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
848 break;
849
850 CASE_UNPCK(PUNPCKHQDQ, r)
851 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
852 RegForm = true;
853 LLVM_FALLTHROUGH;
854
855 CASE_UNPCK(PUNPCKHQDQ, m)
856 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
857 DestName = getRegName(MI->getOperand(0).getReg());
858 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
859 break;
860
861 CASE_UNPCK(PUNPCKLBW, r)
862 case X86::MMX_PUNPCKLBWirr:
863 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
864 RegForm = true;
865 LLVM_FALLTHROUGH;
866
867 CASE_UNPCK(PUNPCKLBW, m)
868 case X86::MMX_PUNPCKLBWirm:
869 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
870 DestName = getRegName(MI->getOperand(0).getReg());
871 DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
872 break;
873
874 CASE_UNPCK(PUNPCKLWD, r)
875 case X86::MMX_PUNPCKLWDirr:
876 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
877 RegForm = true;
878 LLVM_FALLTHROUGH;
879
880 CASE_UNPCK(PUNPCKLWD, m)
881 case X86::MMX_PUNPCKLWDirm:
882 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
883 DestName = getRegName(MI->getOperand(0).getReg());
884 DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
885 break;
886
887 CASE_UNPCK(PUNPCKLDQ, r)
888 case X86::MMX_PUNPCKLDQirr:
889 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
890 RegForm = true;
891 LLVM_FALLTHROUGH;
892
893 CASE_UNPCK(PUNPCKLDQ, m)
894 case X86::MMX_PUNPCKLDQirm:
895 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
896 DestName = getRegName(MI->getOperand(0).getReg());
897 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
898 break;
899
900 CASE_UNPCK(PUNPCKLQDQ, r)
901 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
902 RegForm = true;
903 LLVM_FALLTHROUGH;
904
905 CASE_UNPCK(PUNPCKLQDQ, m)
906 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
907 DestName = getRegName(MI->getOperand(0).getReg());
908 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
909 break;
910
911 CASE_SHUF(SHUFPD, rri)
912 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
913 RegForm = true;
914 LLVM_FALLTHROUGH;
915
916 CASE_SHUF(SHUFPD, rmi)
917 if (MI->getOperand(NumOperands - 1).isImm())
918 DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64,
919 MI->getOperand(NumOperands - 1).getImm(), ShuffleMask);
920 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
921 DestName = getRegName(MI->getOperand(0).getReg());
922 break;
923
924 CASE_SHUF(SHUFPS, rri)
925 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
926 RegForm = true;
927 LLVM_FALLTHROUGH;
928
929 CASE_SHUF(SHUFPS, rmi)
930 if (MI->getOperand(NumOperands - 1).isImm())
931 DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32,
932 MI->getOperand(NumOperands - 1).getImm(),
933 ShuffleMask);
934 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
935 DestName = getRegName(MI->getOperand(0).getReg());
936 break;
937
938 CASE_VSHUF(64X2, r)
939 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
940 RegForm = true;
941 LLVM_FALLTHROUGH;
942
943 CASE_VSHUF(64X2, m)
944 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64,
945 MI->getOperand(NumOperands - 1).getImm(),
946 ShuffleMask);
947 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
948 DestName = getRegName(MI->getOperand(0).getReg());
949 break;
950
951 CASE_VSHUF(32X4, r)
952 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
953 RegForm = true;
954 LLVM_FALLTHROUGH;
955
956 CASE_VSHUF(32X4, m)
957 decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32,
958 MI->getOperand(NumOperands - 1).getImm(),
959 ShuffleMask);
960 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
961 DestName = getRegName(MI->getOperand(0).getReg());
962 break;
963
964 CASE_UNPCK(UNPCKLPD, r)
965 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
966 RegForm = true;
967 LLVM_FALLTHROUGH;
968
969 CASE_UNPCK(UNPCKLPD, m)
970 DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
971 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
972 DestName = getRegName(MI->getOperand(0).getReg());
973 break;
974
975 CASE_UNPCK(UNPCKLPS, r)
976 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
977 RegForm = true;
978 LLVM_FALLTHROUGH;
979
980 CASE_UNPCK(UNPCKLPS, m)
981 DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
982 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
983 DestName = getRegName(MI->getOperand(0).getReg());
984 break;
985
986 CASE_UNPCK(UNPCKHPD, r)
987 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
988 RegForm = true;
989 LLVM_FALLTHROUGH;
990
991 CASE_UNPCK(UNPCKHPD, m)
992 DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
993 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
994 DestName = getRegName(MI->getOperand(0).getReg());
995 break;
996
997 CASE_UNPCK(UNPCKHPS, r)
998 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
999 RegForm = true;
1000 LLVM_FALLTHROUGH;
1001
1002 CASE_UNPCK(UNPCKHPS, m)
1003 DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1004 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1005 DestName = getRegName(MI->getOperand(0).getReg());
1006 break;
1007
1008 CASE_VPERMILPI(PERMILPS, r)
1009 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1010 LLVM_FALLTHROUGH;
1011
1012 CASE_VPERMILPI(PERMILPS, m)
1013 if (MI->getOperand(NumOperands - 1).isImm())
1014 DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1015 MI->getOperand(NumOperands - 1).getImm(),
1016 ShuffleMask);
1017 DestName = getRegName(MI->getOperand(0).getReg());
1018 break;
1019
1020 CASE_VPERMILPI(PERMILPD, r)
1021 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1022 LLVM_FALLTHROUGH;
1023
1024 CASE_VPERMILPI(PERMILPD, m)
1025 if (MI->getOperand(NumOperands - 1).isImm())
1026 DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64,
1027 MI->getOperand(NumOperands - 1).getImm(),
1028 ShuffleMask);
1029 DestName = getRegName(MI->getOperand(0).getReg());
1030 break;
1031
1032 case X86::VPERM2F128rr:
1033 case X86::VPERM2I128rr:
1034 Src2Name = getRegName(MI->getOperand(2).getReg());
1035 LLVM_FALLTHROUGH;
1036
1037 case X86::VPERM2F128rm:
1038 case X86::VPERM2I128rm:
1039 // For instruction comments purpose, assume the 256-bit vector is v4i64.
1040 if (MI->getOperand(NumOperands - 1).isImm())
1041 DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
1042 ShuffleMask);
1043 Src1Name = getRegName(MI->getOperand(1).getReg());
1044 DestName = getRegName(MI->getOperand(0).getReg());
1045 break;
1046
1047 CASE_VPERM(PERMPD, r)
1048 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1049 LLVM_FALLTHROUGH;
1050
1051 CASE_VPERM(PERMPD, m)
1052 if (MI->getOperand(NumOperands - 1).isImm())
1053 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1054 MI->getOperand(NumOperands - 1).getImm(),
1055 ShuffleMask);
1056 DestName = getRegName(MI->getOperand(0).getReg());
1057 break;
1058
1059 CASE_VPERM(PERMQ, r)
1060 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1061 LLVM_FALLTHROUGH;
1062
1063 CASE_VPERM(PERMQ, m)
1064 if (MI->getOperand(NumOperands - 1).isImm())
1065 DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1066 MI->getOperand(NumOperands - 1).getImm(),
1067 ShuffleMask);
1068 DestName = getRegName(MI->getOperand(0).getReg());
1069 break;
1070
1071 case X86::MOVSDrr:
1072 case X86::VMOVSDrr:
1073 case X86::VMOVSDZrr:
1074 Src2Name = getRegName(MI->getOperand(2).getReg());
1075 Src1Name = getRegName(MI->getOperand(1).getReg());
1076 LLVM_FALLTHROUGH;
1077
1078 case X86::MOVSDrm_alt:
1079 case X86::MOVSDrm:
1080 case X86::VMOVSDrm_alt:
1081 case X86::VMOVSDrm:
1082 case X86::VMOVSDZrm:
1083 case X86::VMOVSDZrm_alt:
1084 DecodeScalarMoveMask(2, nullptr == Src2Name, ShuffleMask);
1085 DestName = getRegName(MI->getOperand(0).getReg());
1086 break;
1087
1088 case X86::MOVSSrr:
1089 case X86::VMOVSSrr:
1090 case X86::VMOVSSZrr:
1091 Src2Name = getRegName(MI->getOperand(2).getReg());
1092 Src1Name = getRegName(MI->getOperand(1).getReg());
1093 LLVM_FALLTHROUGH;
1094
1095 case X86::MOVSSrm:
1096 case X86::MOVSSrm_alt:
1097 case X86::VMOVSSrm:
1098 case X86::VMOVSSrm_alt:
1099 case X86::VMOVSSZrm:
1100 case X86::VMOVSSZrm_alt:
1101 DecodeScalarMoveMask(4, nullptr == Src2Name, ShuffleMask);
1102 DestName = getRegName(MI->getOperand(0).getReg());
1103 break;
1104
1105 case X86::MOVPQI2QIrr:
1106 case X86::MOVZPQILo2PQIrr:
1107 case X86::VMOVPQI2QIrr:
1108 case X86::VMOVPQI2QIZrr:
1109 case X86::VMOVZPQILo2PQIrr:
1110 case X86::VMOVZPQILo2PQIZrr:
1111 Src1Name = getRegName(MI->getOperand(1).getReg());
1112 LLVM_FALLTHROUGH;
1113
1114 case X86::MOVQI2PQIrm:
1115 case X86::VMOVQI2PQIrm:
1116 case X86::VMOVQI2PQIZrm:
1117 DecodeZeroMoveLowMask(2, ShuffleMask);
1118 DestName = getRegName(MI->getOperand(0).getReg());
1119 break;
1120
1121 case X86::MOVDI2PDIrm:
1122 case X86::VMOVDI2PDIrm:
1123 case X86::VMOVDI2PDIZrm:
1124 DecodeZeroMoveLowMask(4, ShuffleMask);
1125 DestName = getRegName(MI->getOperand(0).getReg());
1126 break;
1127
1128 case X86::EXTRQI:
1129 if (MI->getOperand(2).isImm() &&
1130 MI->getOperand(3).isImm())
1131 DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(),
1132 MI->getOperand(3).getImm(), ShuffleMask);
1133
1134 DestName = getRegName(MI->getOperand(0).getReg());
1135 Src1Name = getRegName(MI->getOperand(1).getReg());
1136 break;
1137
1138 case X86::INSERTQI:
1139 if (MI->getOperand(3).isImm() &&
1140 MI->getOperand(4).isImm())
1141 DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(),
1142 MI->getOperand(4).getImm(), ShuffleMask);
1143
1144 DestName = getRegName(MI->getOperand(0).getReg());
1145 Src1Name = getRegName(MI->getOperand(1).getReg());
1146 Src2Name = getRegName(MI->getOperand(2).getReg());
1147 break;
1148
1149 case X86::VBROADCASTF128:
1150 case X86::VBROADCASTI128:
1151 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1152 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
1153 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1154 DestName = getRegName(MI->getOperand(0).getReg());
1155 break;
1156 CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1157 CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1158 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1159 DestName = getRegName(MI->getOperand(0).getReg());
1160 break;
1161 CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1162 CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1163 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1164 DestName = getRegName(MI->getOperand(0).getReg());
1165 break;
1166 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1167 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1168 DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1169 DestName = getRegName(MI->getOperand(0).getReg());
1170 break;
1171 CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1172 CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1173 DecodeSubVectorBroadcast(16, 4, ShuffleMask);
1174 DestName = getRegName(MI->getOperand(0).getReg());
1175 break;
1176 CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1177 CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1178 DecodeSubVectorBroadcast(16, 8, ShuffleMask);
1179 DestName = getRegName(MI->getOperand(0).getReg());
1180 break;
1181 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, r)
1182 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1183 LLVM_FALLTHROUGH;
1184 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, m)
1185 DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1186 DestName = getRegName(MI->getOperand(0).getReg());
1187 break;
1188 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r)
1189 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r)
1190 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1191 LLVM_FALLTHROUGH;
1192 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m)
1193 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m)
1194 DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1195 DestName = getRegName(MI->getOperand(0).getReg());
1196 break;
1197 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r)
1198 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r)
1199 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1200 LLVM_FALLTHROUGH;
1201 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m)
1202 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m)
1203 DecodeSubVectorBroadcast(16, 2, ShuffleMask);
1204 DestName = getRegName(MI->getOperand(0).getReg());
1205 break;
1206
1207 CASE_PMOVZX(PMOVZXBW, r)
1208 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1209 LLVM_FALLTHROUGH;
1210 CASE_PMOVZX(PMOVZXBW, m)
1211 DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false,
1212 ShuffleMask);
1213 DestName = getRegName(MI->getOperand(0).getReg());
1214 break;
1215
1216 CASE_PMOVZX(PMOVZXBD, r)
1217 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1218 LLVM_FALLTHROUGH;
1219 CASE_PMOVZX(PMOVZXBD, m)
1220 DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false,
1221 ShuffleMask);
1222 DestName = getRegName(MI->getOperand(0).getReg());
1223 break;
1224
1225 CASE_PMOVZX(PMOVZXBQ, r)
1226 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1227 LLVM_FALLTHROUGH;
1228 CASE_PMOVZX(PMOVZXBQ, m)
1229 DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false,
1230 ShuffleMask);
1231 DestName = getRegName(MI->getOperand(0).getReg());
1232 break;
1233
1234 CASE_PMOVZX(PMOVZXWD, r)
1235 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1236 LLVM_FALLTHROUGH;
1237 CASE_PMOVZX(PMOVZXWD, m)
1238 DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false,
1239 ShuffleMask);
1240 DestName = getRegName(MI->getOperand(0).getReg());
1241 break;
1242
1243 CASE_PMOVZX(PMOVZXWQ, r)
1244 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1245 LLVM_FALLTHROUGH;
1246 CASE_PMOVZX(PMOVZXWQ, m)
1247 DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false,
1248 ShuffleMask);
1249 DestName = getRegName(MI->getOperand(0).getReg());
1250 break;
1251
1252 CASE_PMOVZX(PMOVZXDQ, r)
1253 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1254 LLVM_FALLTHROUGH;
1255 CASE_PMOVZX(PMOVZXDQ, m)
1256 DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false,
1257 ShuffleMask);
1258 DestName = getRegName(MI->getOperand(0).getReg());
1259 break;
1260 }
1261
1262 // The only comments we decode are shuffles, so give up if we were unable to
1263 // decode a shuffle mask.
1264 if (ShuffleMask.empty())
1265 return false;
1266
1267 if (!DestName) DestName = Src1Name;
1268 if (DestName) {
1269 OS << DestName;
1270 printMasking(OS, MI, MCII);
1271 } else
1272 OS << "mem";
1273
1274 OS << " = ";
1275
1276 // If the two sources are the same, canonicalize the input elements to be
1277 // from the first src so that we get larger element spans.
1278 if (Src1Name == Src2Name) {
1279 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1280 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1281 ShuffleMask[i] >= (int)e) // From second mask.
1282 ShuffleMask[i] -= e;
1283 }
1284 }
1285
1286 // The shuffle mask specifies which elements of the src1/src2 fill in the
1287 // destination, with a few sentinel values. Loop through and print them
1288 // out.
1289 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1290 if (i != 0)
1291 OS << ',';
1292 if (ShuffleMask[i] == SM_SentinelZero) {
1293 OS << "zero";
1294 continue;
1295 }
1296
1297 // Otherwise, it must come from src1 or src2. Print the span of elements
1298 // that comes from this src.
1299 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1300 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1301 OS << (SrcName ? SrcName : "mem") << '[';
1302 bool IsFirst = true;
1303 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1304 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1305 if (!IsFirst)
1306 OS << ',';
1307 else
1308 IsFirst = false;
1309 if (ShuffleMask[i] == SM_SentinelUndef)
1310 OS << "u";
1311 else
1312 OS << ShuffleMask[i] % ShuffleMask.size();
1313 ++i;
1314 }
1315 OS << ']';
1316 --i; // For loop increments element #.
1317 }
1318 OS << '\n';
1319
1320 // We successfully added a comment to this instruction.
1321 return true;
1322 }
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